From 8e61487206f5446172b08799e671f043ae7ca2bc Mon Sep 17 00:00:00 2001 From: Tom Stellard Date: Wed, 25 Apr 2012 13:41:39 -0400 Subject: AMDIL: Add R600/SI Tablegen definitions and generated files v3 The following files are generated by perl scripts: AMDGPUGenInstrEnums.pl => AMDGPUInstrEnums.include => AMDGPUInstrEnums.h.include => AMDGPUInstrEnums.td R600GenRegisterInfo.pl => R600RegisterInfo.td => R600HwRegInfo.include SIGenRegisterInfo.pl => SIRegisterInfo.td => SIRegisterGetHWRegNum.include --- lib/Target/AMDIL/AMDGPUGenInstrEnums.pl | 143 + lib/Target/AMDIL/AMDGPUInstrEnums.h.include | 101 + lib/Target/AMDIL/AMDGPUInstrEnums.include | 95 + lib/Target/AMDIL/AMDGPUInstrEnums.td | 108 + lib/Target/AMDIL/AMDGPUInstructions.td | 80 + lib/Target/AMDIL/AMDGPUIntrinsics.td | 64 + lib/Target/AMDIL/AMDGPURegisterInfo.td | 22 + lib/Target/AMDIL/AMDIL.td | 19 + lib/Target/AMDIL/AMDILBase.td | 109 + lib/Target/AMDIL/AMDILCallingConv.td | 562 ++++ lib/Target/AMDIL/AMDILConversions.td | 1022 +++++++ lib/Target/AMDIL/AMDILEnumeratedTypes.td | 522 ++++ lib/Target/AMDIL/AMDILFormats.td | 450 +++ lib/Target/AMDIL/AMDILInstrInfo.td | 115 + lib/Target/AMDIL/AMDILInstrPatterns.td | 66 + lib/Target/AMDIL/AMDILInstructions.td | 2436 +++++++++++++++ lib/Target/AMDIL/AMDILIntrinsics.td | 705 +++++ lib/Target/AMDIL/AMDILMultiClass.td | 1440 +++++++++ lib/Target/AMDIL/AMDILNodes.td | 325 ++ lib/Target/AMDIL/AMDILOperands.td | 37 + lib/Target/AMDIL/AMDILPatterns.td | 504 ++++ lib/Target/AMDIL/AMDILProfiles.td | 174 ++ lib/Target/AMDIL/AMDILRegisterInfo.td | 964 ++++++ lib/Target/AMDIL/AMDILTokenDesc.td | 120 + lib/Target/AMDIL/AMDILVersion.td | 75 + lib/Target/AMDIL/Processors.td | 28 + lib/Target/AMDIL/R600GenRegisterInfo.pl | 202 ++ lib/Target/AMDIL/R600HwRegInfo.include | 3864 ++++++++++++++++++++++++ lib/Target/AMDIL/R600Instructions.td | 1050 +++++++ lib/Target/AMDIL/R600Intrinsics.td | 16 + lib/Target/AMDIL/R600RegisterInfo.td | 1889 ++++++++++++ lib/Target/AMDIL/R600Schedule.td | 36 + lib/Target/AMDIL/SIGenRegisterInfo.pl | 282 ++ lib/Target/AMDIL/SIInstrFormats.td | 138 + lib/Target/AMDIL/SIInstrInfo.td | 463 +++ lib/Target/AMDIL/SIInstructions.td | 945 ++++++ lib/Target/AMDIL/SIIntrinsics.td | 34 + lib/Target/AMDIL/SIRegisterGetHWRegNum.include | 905 ++++++ lib/Target/AMDIL/SIRegisterInfo.td | 894 ++++++ lib/Target/AMDIL/SISchedule.td | 15 + 40 files changed, 21019 insertions(+) create mode 100644 lib/Target/AMDIL/AMDGPUGenInstrEnums.pl create mode 100644 lib/Target/AMDIL/AMDGPUInstrEnums.h.include create mode 100644 lib/Target/AMDIL/AMDGPUInstrEnums.include create mode 100644 lib/Target/AMDIL/AMDGPUInstrEnums.td create mode 100644 lib/Target/AMDIL/AMDGPUInstructions.td create mode 100644 lib/Target/AMDIL/AMDGPUIntrinsics.td create mode 100644 lib/Target/AMDIL/AMDGPURegisterInfo.td create mode 100644 lib/Target/AMDIL/AMDIL.td create mode 100644 lib/Target/AMDIL/AMDILBase.td create mode 100644 lib/Target/AMDIL/AMDILCallingConv.td create mode 100644 lib/Target/AMDIL/AMDILConversions.td create mode 100644 lib/Target/AMDIL/AMDILEnumeratedTypes.td create mode 100644 lib/Target/AMDIL/AMDILFormats.td create mode 100644 lib/Target/AMDIL/AMDILInstrInfo.td create mode 100644 lib/Target/AMDIL/AMDILInstrPatterns.td create mode 100644 lib/Target/AMDIL/AMDILInstructions.td create mode 100644 lib/Target/AMDIL/AMDILIntrinsics.td create mode 100644 lib/Target/AMDIL/AMDILMultiClass.td create mode 100644 lib/Target/AMDIL/AMDILNodes.td create mode 100644 lib/Target/AMDIL/AMDILOperands.td create mode 100644 lib/Target/AMDIL/AMDILPatterns.td create mode 100644 lib/Target/AMDIL/AMDILProfiles.td create mode 100644 lib/Target/AMDIL/AMDILRegisterInfo.td create mode 100644 lib/Target/AMDIL/AMDILTokenDesc.td create mode 100644 lib/Target/AMDIL/AMDILVersion.td create mode 100644 lib/Target/AMDIL/Processors.td create mode 100644 lib/Target/AMDIL/R600GenRegisterInfo.pl create mode 100644 lib/Target/AMDIL/R600HwRegInfo.include create mode 100644 lib/Target/AMDIL/R600Instructions.td create mode 100644 lib/Target/AMDIL/R600Intrinsics.td create mode 100644 lib/Target/AMDIL/R600RegisterInfo.td create mode 100644 lib/Target/AMDIL/R600Schedule.td create mode 100644 lib/Target/AMDIL/SIGenRegisterInfo.pl create mode 100644 lib/Target/AMDIL/SIInstrFormats.td create mode 100644 lib/Target/AMDIL/SIInstrInfo.td create mode 100644 lib/Target/AMDIL/SIInstructions.td create mode 100644 lib/Target/AMDIL/SIIntrinsics.td create mode 100644 lib/Target/AMDIL/SIRegisterGetHWRegNum.include create mode 100644 lib/Target/AMDIL/SIRegisterInfo.td create mode 100644 lib/Target/AMDIL/SISchedule.td diff --git a/lib/Target/AMDIL/AMDGPUGenInstrEnums.pl b/lib/Target/AMDIL/AMDGPUGenInstrEnums.pl new file mode 100644 index 00000000000..130eaac72bc --- /dev/null +++ b/lib/Target/AMDIL/AMDGPUGenInstrEnums.pl @@ -0,0 +1,143 @@ +#===-- AMDGPUGenInstrEnums.pl - Script for generating instruction enums ----===# +# +# The LLVM Compiler Infrastructure +# +# This file is distributed under the University of Illinois Open Source +# License. See LICENSE.TXT for details. +# +#===-----------------------------------------------------------------------===# +# +# This perl script is used to generate the following files: +# +# 1. perl AMDGPUGenInstrEnums.pl td > AMDGPUInstrEnums.td +# +# This file contains Tablegen constants used for matching hw instructions +# from R600 and SI with functionally similar AMDIL instruction. It aslo +# contains definitions of floating point constants like pi (in hex notation) +# that are used in some of the shader patterns. +# +# 2. perl AMDGPUGenInstrEnums.pl h > AMDGPUInstrEnums.h +# +# This file contains cpp enums that match the constant values in +# AMDGPUInstrEnums.td +# +# 3. perl AMDGPUGenInstrEnums.pl inc > AMDGPUInstrEnums.include +# +# This file contains a function called GetRealAMDILOpcode which maps the +# constant values defined in AMDGPUInstrEnums.h to the corresponding AMDIL +# instructions. +#===-----------------------------------------------------------------------===# + +use warnings; +use strict; + +my @F32_MULTICLASSES = qw { + UnaryIntrinsicFloat + UnaryIntrinsicFloatScalar + BinaryIntrinsicFloat + TernaryIntrinsicFloat + BinaryOpMCFloat +}; + +my @I32_MULTICLASSES = qw { + BinaryOpMCInt + BinaryOpMCi32 + BinaryOpMCi32Const +}; + +my @GENERATION_ENUM = qw { + R600_CAYMAN + R600 + EG + EG_CAYMAN + CAYMAN + SI +}; + +my $FILE_TYPE = $ARGV[0]; + +open AMDIL, '<', 'AMDILInstructions.td'; + +my @INST_ENUMS = ('NONE', 'FEQ', 'FGE', 'FLT', 'FNE', 'MOVE_f32', 'MOVE_i32', 'FTOI', 'ITOF', 'CMOVLOG_f32', 'UGT', 'IGE', 'INE', 'UGE', 'IEQ', 'BINARY_OR_i32', 'BINARY_NOT_i32'); + +while () { + if ($_ =~ /defm\s+([A-Z_]+)\s+:\s+([A-Za-z0-9]+)', @INST_ENUMS); + + print_td_enum('AMDGPUGen', 'AMDGPUGenEnums', 'field bits<3>', @GENERATION_ENUM); + + my %constants = ( + 'PI' => '0x40490fdb', + 'TWO_PI' => '0x40c90fdb', + 'TWO_PI_INV' => '0x3e22f983' + ); + + print "class Constants {\n"; + foreach (keys(%constants)) { + print "int $_ = $constants{$_};\n"; + } + print "}\n"; + print "def CONST : Constants;\n"; + +} elsif ($FILE_TYPE eq 'h') { + + print "unsigned GetRealAMDILOpcode(unsigned internalOpcode) const;\n"; + + print_h_enum('AMDILTblgenOpcode', @INST_ENUMS); + + print_h_enum('AMDGPUGen', @GENERATION_ENUM); + +} elsif ($FILE_TYPE eq 'inc') { + print "unsigned AMDGPUInstrInfo::GetRealAMDILOpcode(unsigned internalOpcode) const\n{\n"; + print " switch(internalOpcode) {\n"; + #Start at 1 so we skip NONE + for (my $i = 1; $i < scalar(@INST_ENUMS); $i++) { + my $inst = $INST_ENUMS[$i]; + print " case AMDGPUInstrInfo::$inst: return AMDIL::$inst;\n"; + } + print " default: abort();\n"; + print " }\n}\n"; +} + + +sub print_td_enum { + my ($instance, $class, $field, @values) = @_; + + print "class $class {\n"; + + for (my $i = 0; $i < scalar(@values); $i++) { + print " $field $values[$i] = $i;\n"; + } + print "}\n"; + + print "def $instance : $class;\n"; +} + +sub print_h_enum { + + my ($enum, @list) = @_; + print "enum $enum {\n"; + + for (my $i = 0; $i < scalar(@list); $i++) { + print " $list[$i] = $i"; + if ($i != $#list) { + print ','; + } + print "\n"; + } + print "};\n"; +} + diff --git a/lib/Target/AMDIL/AMDGPUInstrEnums.h.include b/lib/Target/AMDIL/AMDGPUInstrEnums.h.include new file mode 100644 index 00000000000..414489e40fa --- /dev/null +++ b/lib/Target/AMDIL/AMDGPUInstrEnums.h.include @@ -0,0 +1,101 @@ +unsigned GetRealAMDILOpcode(unsigned internalOpcode) const; +enum AMDILTblgenOpcode { + NONE = 0, + FEQ = 1, + FGE = 2, + FLT = 3, + FNE = 4, + MOVE_f32 = 5, + MOVE_i32 = 6, + FTOI = 7, + ITOF = 8, + CMOVLOG_f32 = 9, + UGT = 10, + IGE = 11, + INE = 12, + UGE = 13, + IEQ = 14, + BINARY_OR_i32 = 15, + BINARY_NOT_i32 = 16, + AND_i32 = 17, + SMAX_i32 = 18, + CMOVLOG_Y_i32 = 19, + CMOVLOG_Z_i32 = 20, + CMOVLOG_W_i32 = 21, + SMUL_i32 = 22, + SMULHI_i32 = 23, + SHL_i32 = 24, + SHR_i32 = 25, + SHLVEC_i32 = 26, + SHRVEC_i32 = 27, + ADD_i32 = 28, + CUSTOM_XOR_i32 = 29, + CUSTOM_ADD_i32 = 30, + EADD_i32 = 31, + INTTOANY_i32 = 32, + UMUL_i32 = 33, + UMULHI_i32 = 34, + USHR_i32 = 35, + USHRVEC_i32 = 36, + UDIV_i32 = 37, + MUL_IEEE_f32 = 38, + ADD_f32 = 39, + ABS_f32 = 40, + FRAC_f32 = 41, + PIREDUCE_f32 = 42, + ROUND_NEAREST_f32 = 43, + ROUND_NEGINF_f32 = 44, + ROUND_POSINF_f32 = 45, + ROUND_ZERO_f32 = 46, + ACOS_f32 = 47, + ATAN_f32 = 48, + ASIN_f32 = 49, + TAN_f32 = 50, + SIN_f32 = 51, + COS_f32 = 52, + SQRT_f32 = 53, + EXP_f32 = 54, + EXPVEC_f32 = 55, + SQRTVEC_f32 = 56, + COSVEC_f32 = 57, + SINVEC_f32 = 58, + LOGVEC_f32 = 59, + RSQVEC_f32 = 60, + EXN_f32 = 61, + SIGN_f32 = 62, + LENGTH_f32 = 63, + POW_f32 = 64, + MIN_f32 = 65, + MAX_f32 = 66, + MAD_f32 = 67, + LN_f32 = 68, + LOG_f32 = 69, + RSQ_f32 = 70, + DIV_f32 = 71, + CLAMP_f32 = 72, + FMA_f32 = 73, + LERP_f32 = 74, + NEG_f32 = 75, + INTTOANY_f32 = 76, + UAVARENALOAD_i32 = 77, + UAVARENALOAD_Y_i32 = 78, + UAVARENALOAD_Z_i32 = 79, + UAVARENALOAD_W_i32 = 80, + UAVRAWLOAD_i32 = 81, + UAVRAWLOADCACHED_i32 = 82, + UAVARENASTORE_i32 = 83, + UAVARENASTORE_Y_i32 = 84, + UAVARENASTORE_Z_i32 = 85, + UAVARENASTORE_W_i32 = 86, + UAVRAWSTORE_i32 = 87, + GET_PRINTF_OFFSET_i32 = 88, + GET_PRINTF_SIZE_i32 = 89 +}; +enum AMDGPUGen { + R600_CAYMAN = 0, + R600 = 1, + EG = 2, + EG_CAYMAN = 3, + CAYMAN = 4, + SI = 5 +}; diff --git a/lib/Target/AMDIL/AMDGPUInstrEnums.include b/lib/Target/AMDIL/AMDGPUInstrEnums.include new file mode 100644 index 00000000000..69f4c710541 --- /dev/null +++ b/lib/Target/AMDIL/AMDGPUInstrEnums.include @@ -0,0 +1,95 @@ +unsigned AMDGPUInstrInfo::GetRealAMDILOpcode(unsigned internalOpcode) const +{ + switch(internalOpcode) { + case AMDGPUInstrInfo::FEQ: return AMDIL::FEQ; + case AMDGPUInstrInfo::FGE: return AMDIL::FGE; + case AMDGPUInstrInfo::FLT: return AMDIL::FLT; + case AMDGPUInstrInfo::FNE: return AMDIL::FNE; + case AMDGPUInstrInfo::MOVE_f32: return AMDIL::MOVE_f32; + case AMDGPUInstrInfo::MOVE_i32: return AMDIL::MOVE_i32; + case AMDGPUInstrInfo::FTOI: return AMDIL::FTOI; + case AMDGPUInstrInfo::ITOF: return AMDIL::ITOF; + case AMDGPUInstrInfo::CMOVLOG_f32: return AMDIL::CMOVLOG_f32; + case AMDGPUInstrInfo::UGT: return AMDIL::UGT; + case AMDGPUInstrInfo::IGE: return AMDIL::IGE; + case AMDGPUInstrInfo::INE: return AMDIL::INE; + case AMDGPUInstrInfo::UGE: return AMDIL::UGE; + case AMDGPUInstrInfo::IEQ: return AMDIL::IEQ; + case AMDGPUInstrInfo::BINARY_OR_i32: return AMDIL::BINARY_OR_i32; + case AMDGPUInstrInfo::BINARY_NOT_i32: return AMDIL::BINARY_NOT_i32; + case AMDGPUInstrInfo::AND_i32: return AMDIL::AND_i32; + case AMDGPUInstrInfo::SMAX_i32: return AMDIL::SMAX_i32; + case AMDGPUInstrInfo::CMOVLOG_Y_i32: return AMDIL::CMOVLOG_Y_i32; + case AMDGPUInstrInfo::CMOVLOG_Z_i32: return AMDIL::CMOVLOG_Z_i32; + case AMDGPUInstrInfo::CMOVLOG_W_i32: return AMDIL::CMOVLOG_W_i32; + case AMDGPUInstrInfo::SMUL_i32: return AMDIL::SMUL_i32; + case AMDGPUInstrInfo::SMULHI_i32: return AMDIL::SMULHI_i32; + case AMDGPUInstrInfo::SHL_i32: return AMDIL::SHL_i32; + case AMDGPUInstrInfo::SHR_i32: return AMDIL::SHR_i32; + case AMDGPUInstrInfo::SHLVEC_i32: return AMDIL::SHLVEC_i32; + case AMDGPUInstrInfo::SHRVEC_i32: return AMDIL::SHRVEC_i32; + case AMDGPUInstrInfo::ADD_i32: return AMDIL::ADD_i32; + case AMDGPUInstrInfo::CUSTOM_XOR_i32: return AMDIL::CUSTOM_XOR_i32; + case AMDGPUInstrInfo::CUSTOM_ADD_i32: return AMDIL::CUSTOM_ADD_i32; + case AMDGPUInstrInfo::EADD_i32: return AMDIL::EADD_i32; + case AMDGPUInstrInfo::INTTOANY_i32: return AMDIL::INTTOANY_i32; + case AMDGPUInstrInfo::UMUL_i32: return AMDIL::UMUL_i32; + case AMDGPUInstrInfo::UMULHI_i32: return AMDIL::UMULHI_i32; + case AMDGPUInstrInfo::USHR_i32: return AMDIL::USHR_i32; + case AMDGPUInstrInfo::USHRVEC_i32: return AMDIL::USHRVEC_i32; + case AMDGPUInstrInfo::UDIV_i32: return AMDIL::UDIV_i32; + case AMDGPUInstrInfo::MUL_IEEE_f32: return AMDIL::MUL_IEEE_f32; + case AMDGPUInstrInfo::ADD_f32: return AMDIL::ADD_f32; + case AMDGPUInstrInfo::ABS_f32: return AMDIL::ABS_f32; + case AMDGPUInstrInfo::FRAC_f32: return AMDIL::FRAC_f32; + case AMDGPUInstrInfo::PIREDUCE_f32: return AMDIL::PIREDUCE_f32; + case AMDGPUInstrInfo::ROUND_NEAREST_f32: return AMDIL::ROUND_NEAREST_f32; + case AMDGPUInstrInfo::ROUND_NEGINF_f32: return AMDIL::ROUND_NEGINF_f32; + case AMDGPUInstrInfo::ROUND_POSINF_f32: return AMDIL::ROUND_POSINF_f32; + case AMDGPUInstrInfo::ROUND_ZERO_f32: return AMDIL::ROUND_ZERO_f32; + case AMDGPUInstrInfo::ACOS_f32: return AMDIL::ACOS_f32; + case AMDGPUInstrInfo::ATAN_f32: return AMDIL::ATAN_f32; + case AMDGPUInstrInfo::ASIN_f32: return AMDIL::ASIN_f32; + case AMDGPUInstrInfo::TAN_f32: return AMDIL::TAN_f32; + case AMDGPUInstrInfo::SIN_f32: return AMDIL::SIN_f32; + case AMDGPUInstrInfo::COS_f32: return AMDIL::COS_f32; + case AMDGPUInstrInfo::SQRT_f32: return AMDIL::SQRT_f32; + case AMDGPUInstrInfo::EXP_f32: return AMDIL::EXP_f32; + case AMDGPUInstrInfo::EXPVEC_f32: return AMDIL::EXPVEC_f32; + case AMDGPUInstrInfo::SQRTVEC_f32: return AMDIL::SQRTVEC_f32; + case AMDGPUInstrInfo::COSVEC_f32: return AMDIL::COSVEC_f32; + case AMDGPUInstrInfo::SINVEC_f32: return AMDIL::SINVEC_f32; + case AMDGPUInstrInfo::LOGVEC_f32: return AMDIL::LOGVEC_f32; + case AMDGPUInstrInfo::RSQVEC_f32: return AMDIL::RSQVEC_f32; + case AMDGPUInstrInfo::EXN_f32: return AMDIL::EXN_f32; + case AMDGPUInstrInfo::SIGN_f32: return AMDIL::SIGN_f32; + case AMDGPUInstrInfo::LENGTH_f32: return AMDIL::LENGTH_f32; + case AMDGPUInstrInfo::POW_f32: return AMDIL::POW_f32; + case AMDGPUInstrInfo::MIN_f32: return AMDIL::MIN_f32; + case AMDGPUInstrInfo::MAX_f32: return AMDIL::MAX_f32; + case AMDGPUInstrInfo::MAD_f32: return AMDIL::MAD_f32; + case AMDGPUInstrInfo::LN_f32: return AMDIL::LN_f32; + case AMDGPUInstrInfo::LOG_f32: return AMDIL::LOG_f32; + case AMDGPUInstrInfo::RSQ_f32: return AMDIL::RSQ_f32; + case AMDGPUInstrInfo::DIV_f32: return AMDIL::DIV_f32; + case AMDGPUInstrInfo::CLAMP_f32: return AMDIL::CLAMP_f32; + case AMDGPUInstrInfo::FMA_f32: return AMDIL::FMA_f32; + case AMDGPUInstrInfo::LERP_f32: return AMDIL::LERP_f32; + case AMDGPUInstrInfo::NEG_f32: return AMDIL::NEG_f32; + case AMDGPUInstrInfo::INTTOANY_f32: return AMDIL::INTTOANY_f32; + case AMDGPUInstrInfo::UAVARENALOAD_i32: return AMDIL::UAVARENALOAD_i32; + case AMDGPUInstrInfo::UAVARENALOAD_Y_i32: return AMDIL::UAVARENALOAD_Y_i32; + case AMDGPUInstrInfo::UAVARENALOAD_Z_i32: return AMDIL::UAVARENALOAD_Z_i32; + case AMDGPUInstrInfo::UAVARENALOAD_W_i32: return AMDIL::UAVARENALOAD_W_i32; + case AMDGPUInstrInfo::UAVRAWLOAD_i32: return AMDIL::UAVRAWLOAD_i32; + case AMDGPUInstrInfo::UAVRAWLOADCACHED_i32: return AMDIL::UAVRAWLOADCACHED_i32; + case AMDGPUInstrInfo::UAVARENASTORE_i32: return AMDIL::UAVARENASTORE_i32; + case AMDGPUInstrInfo::UAVARENASTORE_Y_i32: return AMDIL::UAVARENASTORE_Y_i32; + case AMDGPUInstrInfo::UAVARENASTORE_Z_i32: return AMDIL::UAVARENASTORE_Z_i32; + case AMDGPUInstrInfo::UAVARENASTORE_W_i32: return AMDIL::UAVARENASTORE_W_i32; + case AMDGPUInstrInfo::UAVRAWSTORE_i32: return AMDIL::UAVRAWSTORE_i32; + case AMDGPUInstrInfo::GET_PRINTF_OFFSET_i32: return AMDIL::GET_PRINTF_OFFSET_i32; + case AMDGPUInstrInfo::GET_PRINTF_SIZE_i32: return AMDIL::GET_PRINTF_SIZE_i32; + default: abort(); + } +} diff --git a/lib/Target/AMDIL/AMDGPUInstrEnums.td b/lib/Target/AMDIL/AMDGPUInstrEnums.td new file mode 100644 index 00000000000..c00bb66f8c8 --- /dev/null +++ b/lib/Target/AMDIL/AMDGPUInstrEnums.td @@ -0,0 +1,108 @@ +class AMDILInstEnums { + field bits<16> NONE = 0; + field bits<16> FEQ = 1; + field bits<16> FGE = 2; + field bits<16> FLT = 3; + field bits<16> FNE = 4; + field bits<16> MOVE_f32 = 5; + field bits<16> MOVE_i32 = 6; + field bits<16> FTOI = 7; + field bits<16> ITOF = 8; + field bits<16> CMOVLOG_f32 = 9; + field bits<16> UGT = 10; + field bits<16> IGE = 11; + field bits<16> INE = 12; + field bits<16> UGE = 13; + field bits<16> IEQ = 14; + field bits<16> BINARY_OR_i32 = 15; + field bits<16> BINARY_NOT_i32 = 16; + field bits<16> AND_i32 = 17; + field bits<16> SMAX_i32 = 18; + field bits<16> CMOVLOG_Y_i32 = 19; + field bits<16> CMOVLOG_Z_i32 = 20; + field bits<16> CMOVLOG_W_i32 = 21; + field bits<16> SMUL_i32 = 22; + field bits<16> SMULHI_i32 = 23; + field bits<16> SHL_i32 = 24; + field bits<16> SHR_i32 = 25; + field bits<16> SHLVEC_i32 = 26; + field bits<16> SHRVEC_i32 = 27; + field bits<16> ADD_i32 = 28; + field bits<16> CUSTOM_XOR_i32 = 29; + field bits<16> CUSTOM_ADD_i32 = 30; + field bits<16> EADD_i32 = 31; + field bits<16> INTTOANY_i32 = 32; + field bits<16> UMUL_i32 = 33; + field bits<16> UMULHI_i32 = 34; + field bits<16> USHR_i32 = 35; + field bits<16> USHRVEC_i32 = 36; + field bits<16> UDIV_i32 = 37; + field bits<16> MUL_IEEE_f32 = 38; + field bits<16> ADD_f32 = 39; + field bits<16> ABS_f32 = 40; + field bits<16> FRAC_f32 = 41; + field bits<16> PIREDUCE_f32 = 42; + field bits<16> ROUND_NEAREST_f32 = 43; + field bits<16> ROUND_NEGINF_f32 = 44; + field bits<16> ROUND_POSINF_f32 = 45; + field bits<16> ROUND_ZERO_f32 = 46; + field bits<16> ACOS_f32 = 47; + field bits<16> ATAN_f32 = 48; + field bits<16> ASIN_f32 = 49; + field bits<16> TAN_f32 = 50; + field bits<16> SIN_f32 = 51; + field bits<16> COS_f32 = 52; + field bits<16> SQRT_f32 = 53; + field bits<16> EXP_f32 = 54; + field bits<16> EXPVEC_f32 = 55; + field bits<16> SQRTVEC_f32 = 56; + field bits<16> COSVEC_f32 = 57; + field bits<16> SINVEC_f32 = 58; + field bits<16> LOGVEC_f32 = 59; + field bits<16> RSQVEC_f32 = 60; + field bits<16> EXN_f32 = 61; + field bits<16> SIGN_f32 = 62; + field bits<16> LENGTH_f32 = 63; + field bits<16> POW_f32 = 64; + field bits<16> MIN_f32 = 65; + field bits<16> MAX_f32 = 66; + field bits<16> MAD_f32 = 67; + field bits<16> LN_f32 = 68; + field bits<16> LOG_f32 = 69; + field bits<16> RSQ_f32 = 70; + field bits<16> DIV_f32 = 71; + field bits<16> CLAMP_f32 = 72; + field bits<16> FMA_f32 = 73; + field bits<16> LERP_f32 = 74; + field bits<16> NEG_f32 = 75; + field bits<16> INTTOANY_f32 = 76; + field bits<16> UAVARENALOAD_i32 = 77; + field bits<16> UAVARENALOAD_Y_i32 = 78; + field bits<16> UAVARENALOAD_Z_i32 = 79; + field bits<16> UAVARENALOAD_W_i32 = 80; + field bits<16> UAVRAWLOAD_i32 = 81; + field bits<16> UAVRAWLOADCACHED_i32 = 82; + field bits<16> UAVARENASTORE_i32 = 83; + field bits<16> UAVARENASTORE_Y_i32 = 84; + field bits<16> UAVARENASTORE_Z_i32 = 85; + field bits<16> UAVARENASTORE_W_i32 = 86; + field bits<16> UAVRAWSTORE_i32 = 87; + field bits<16> GET_PRINTF_OFFSET_i32 = 88; + field bits<16> GET_PRINTF_SIZE_i32 = 89; +} +def AMDILInst : AMDILInstEnums; +class AMDGPUGenEnums { + field bits<3> R600_CAYMAN = 0; + field bits<3> R600 = 1; + field bits<3> EG = 2; + field bits<3> EG_CAYMAN = 3; + field bits<3> CAYMAN = 4; + field bits<3> SI = 5; +} +def AMDGPUGen : AMDGPUGenEnums; +class Constants { +int TWO_PI = 0x40c90fdb; +int PI = 0x40490fdb; +int TWO_PI_INV = 0x3e22f983; +} +def CONST : Constants; diff --git a/lib/Target/AMDIL/AMDGPUInstructions.td b/lib/Target/AMDIL/AMDGPUInstructions.td new file mode 100644 index 00000000000..f689356e488 --- /dev/null +++ b/lib/Target/AMDIL/AMDGPUInstructions.td @@ -0,0 +1,80 @@ +//===-- AMDGPUInstructions.td - Common instruction defs ---*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains instruction defs that are common to all hw codegen +// targets. +// +//===----------------------------------------------------------------------===// + +include "AMDGPUInstrEnums.td" + +class AMDGPUInst pattern> : Instruction { + field bits<16> AMDILOp = 0; + field bits<3> Gen = 0; + + let Namespace = "AMDIL"; + let OutOperandList = outs; + let InOperandList = ins; + let AsmString = asm; + let Pattern = pattern; + let TSFlags{42-40} = Gen; + let TSFlags{63-48} = AMDILOp; +} + +class AMDGPUShaderInst pattern> + : AMDGPUInst { + + field bits<32> Inst = 0xffffffff; + +} + +let isCodeGenOnly = 1 in { + + def MASK_WRITE : AMDGPUShaderInst < + (outs), + (ins GPRF32:$src), + "MASK_WRITE $src", + [] + >; +} + +/* Generic helper patterns for intrinsics */ +/* -------------------------------------- */ + +class POW_Common : Pat < + (int_AMDGPU_pow rc:$src0, rc:$src1), + (exp_ieee (mul rc:$src1, (log_ieee rc:$src0))) +>; + +/* Other helper patterns */ +/* --------------------- */ + +/* Extract element pattern */ +class Extract_Element : Pat< + (sub_type (vector_extract (vec_type vec_class:$src), sub_idx)), + (EXTRACT_SUBREG vec_class:$src, sub_reg) +>; + +/* Insert element pattern */ +class Insert_Element : Pat < + + (vec_type (vector_insert (vec_type vec_class:$vec), + (elem_type elem_class:$elem), sub_idx)), + (INSERT_SUBREG vec_class:$vec, elem_class:$elem, sub_reg) +>; + +include "R600Instructions.td" + +include "SIInstrInfo.td" + diff --git a/lib/Target/AMDIL/AMDGPUIntrinsics.td b/lib/Target/AMDIL/AMDGPUIntrinsics.td new file mode 100644 index 00000000000..398fd11431f --- /dev/null +++ b/lib/Target/AMDIL/AMDGPUIntrinsics.td @@ -0,0 +1,64 @@ +//===-- AMDGPUIntrinsics.td - Common intrinsics -*- tablegen -*-----------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file defines intrinsics that are used by all hw codegen targets. +// +//===----------------------------------------------------------------------===// + +let TargetPrefix = "AMDGPU", isTarget = 1 in { + + def int_AMDGPU_load_const : Intrinsic<[llvm_float_ty], [llvm_i32_ty], []>; + def int_AMDGPU_load_imm : Intrinsic<[llvm_v4f32_ty], [llvm_i32_ty], []>; + def int_AMDGPU_reserve_reg : Intrinsic<[], [llvm_i32_ty], []>; + def int_AMDGPU_store_output : Intrinsic<[], [llvm_float_ty, llvm_i32_ty], []>; + def int_AMDGPU_swizzle : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty], []>; + + def int_AMDGPU_arl : Intrinsic<[llvm_i32_ty], [llvm_float_ty], []>; + def int_AMDGPU_cndlt : Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty, llvm_float_ty], []>; + def int_AMDGPU_cos : Intrinsic<[llvm_float_ty], [llvm_float_ty], []>; + def int_AMDGPU_div : Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty], []>; + def int_AMDGPU_dp4 : Intrinsic<[llvm_float_ty], [llvm_v4f32_ty, llvm_v4f32_ty], []>; + def int_AMDGPU_floor : Intrinsic<[llvm_float_ty], [llvm_float_ty], []>; + def int_AMDGPU_kill : Intrinsic<[], [llvm_float_ty], []>; + def int_AMDGPU_kilp : Intrinsic<[], [], []>; + def int_AMDGPU_lrp : Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty, llvm_float_ty], []>; + def int_AMDGPU_mul : Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty], []>; + def int_AMDGPU_pow : Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty], []>; + def int_AMDGPU_rcp : Intrinsic<[llvm_float_ty], [llvm_float_ty], []>; + def int_AMDGPU_rsq : Intrinsic<[llvm_float_ty], [llvm_float_ty], []>; + def int_AMDGPU_seq : Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty], []>; + def int_AMDGPU_sgt : Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty], []>; + def int_AMDGPU_sge : Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty], []>; + def int_AMDGPU_sin : Intrinsic<[llvm_float_ty], [llvm_float_ty], []>; + def int_AMDGPU_sle : Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty], []>; + def int_AMDGPU_sne : Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty], []>; + def int_AMDGPU_ssg : Intrinsic<[llvm_float_ty], [llvm_float_ty], []>; + def int_AMDGPU_mullit : Intrinsic<[llvm_v4f32_ty], [llvm_float_ty, llvm_float_ty, llvm_float_ty], []>; + def int_AMDGPU_tex : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty], []>; + def int_AMDGPU_txb : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty], []>; + def int_AMDGPU_txf : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty], []>; + def int_AMDGPU_txq : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty], []>; + def int_AMDGPU_txd : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty], []>; + def int_AMDGPU_txl : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty], []>; + def int_AMDGPU_trunc : Intrinsic<[llvm_float_ty], [llvm_float_ty], []>; + def int_AMDGPU_ddx : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty], []>; + def int_AMDGPU_ddy : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty], []>; + def int_AMDGPU_imax : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>; + def int_AMDGPU_imin : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>; + def int_AMDGPU_umax : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>; + def int_AMDGPU_umin : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>; + def int_AMDGPU_cube : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty], []>; +} + +let TargetPrefix = "TGSI", isTarget = 1 in { + + def int_TGSI_lit_z : Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty, llvm_float_ty],[]>; +} + +include "SIIntrinsics.td" diff --git a/lib/Target/AMDIL/AMDGPURegisterInfo.td b/lib/Target/AMDIL/AMDGPURegisterInfo.td new file mode 100644 index 00000000000..1707903ae7e --- /dev/null +++ b/lib/Target/AMDIL/AMDGPURegisterInfo.td @@ -0,0 +1,22 @@ +//===-- AMDGPURegisterInfo.td - AMDGPU register info -------*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// Tablegen register definitions common to all hw codegen targets. +// +//===----------------------------------------------------------------------===// + +let Namespace = "AMDIL" in { + def sel_x : SubRegIndex; + def sel_y : SubRegIndex; + def sel_z : SubRegIndex; + def sel_w : SubRegIndex; +} + +include "R600RegisterInfo.td" +include "SIRegisterInfo.td" diff --git a/lib/Target/AMDIL/AMDIL.td b/lib/Target/AMDIL/AMDIL.td new file mode 100644 index 00000000000..deee290fad5 --- /dev/null +++ b/lib/Target/AMDIL/AMDIL.td @@ -0,0 +1,19 @@ +//===-- AMDIL.td - AMDIL Tablegen files --*- tablegen -*-------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//==-----------------------------------------------------------------------===// +// This file specifies where the base TD file exists +// and where the version specific TD file exists. +include "AMDILBase.td" +include "AMDILVersion.td" + +include "R600Schedule.td" +include "SISchedule.td" +include "Processors.td" +include "AMDGPUIntrinsics.td" +include "AMDGPURegisterInfo.td" +include "AMDGPUInstructions.td" diff --git a/lib/Target/AMDIL/AMDILBase.td b/lib/Target/AMDIL/AMDILBase.td new file mode 100644 index 00000000000..31ebed31d72 --- /dev/null +++ b/lib/Target/AMDIL/AMDILBase.td @@ -0,0 +1,109 @@ +//===- AMDIL.td - AMDIL Target Machine -------------*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// Target-independent interfaces which we are implementing +//===----------------------------------------------------------------------===// + +include "llvm/Target/Target.td" + +//===----------------------------------------------------------------------===// +// AMDIL Subtarget features. +//===----------------------------------------------------------------------===// +def FeatureFP64 : SubtargetFeature<"fp64", + "CapsOverride[AMDILDeviceInfo::DoubleOps]", + "true", + "Enable 64bit double precision operations">; +def FeatureByteAddress : SubtargetFeature<"byte_addressable_store", + "CapsOverride[AMDILDeviceInfo::ByteStores]", + "true", + "Enable byte addressable stores">; +def FeatureBarrierDetect : SubtargetFeature<"barrier_detect", + "CapsOverride[AMDILDeviceInfo::BarrierDetect]", + "true", + "Enable duplicate barrier detection(HD5XXX or later).">; +def FeatureImages : SubtargetFeature<"images", + "CapsOverride[AMDILDeviceInfo::Images]", + "true", + "Enable image functions">; +def FeatureMultiUAV : SubtargetFeature<"multi_uav", + "CapsOverride[AMDILDeviceInfo::MultiUAV]", + "true", + "Generate multiple UAV code(HD5XXX family or later)">; +def FeatureMacroDB : SubtargetFeature<"macrodb", + "CapsOverride[AMDILDeviceInfo::MacroDB]", + "true", + "Use internal macrodb, instead of macrodb in driver">; +def FeatureNoAlias : SubtargetFeature<"noalias", + "CapsOverride[AMDILDeviceInfo::NoAlias]", + "true", + "assert that all kernel argument pointers are not aliased">; +def FeatureNoInline : SubtargetFeature<"no-inline", + "CapsOverride[AMDILDeviceInfo::NoInline]", + "true", + "specify whether to not inline functions">; + +def Feature64BitPtr : SubtargetFeature<"64BitPtr", + "mIs64bit", + "false", + "Specify if 64bit addressing should be used.">; + +def Feature32on64BitPtr : SubtargetFeature<"64on32BitPtr", + "mIs32on64bit", + "false", + "Specify if 64bit sized pointers with 32bit addressing should be used.">; +def FeatureDebug : SubtargetFeature<"debug", + "CapsOverride[AMDILDeviceInfo::Debug]", + "true", + "Debug mode is enabled, so disable hardware accelerated address spaces.">; +def FeatureDumpCode : SubtargetFeature <"DumpCode", + "mDumpCode", + "true", + "Dump MachineInstrs in the CodeEmitter">; + + +//===----------------------------------------------------------------------===// +// Register File, Calling Conv, Instruction Descriptions +//===----------------------------------------------------------------------===// + + +include "AMDILRegisterInfo.td" +include "AMDILCallingConv.td" +include "AMDILInstrInfo.td" + +def AMDILInstrInfo : InstrInfo {} + +//===----------------------------------------------------------------------===// +// AMDIL processors supported. +//===----------------------------------------------------------------------===// +//include "Processors.td" + +//===----------------------------------------------------------------------===// +// Declare the target which we are implementing +//===----------------------------------------------------------------------===// +def AMDILAsmWriter : AsmWriter { + string AsmWriterClassName = "AsmPrinter"; + int Variant = 0; +} + +def AMDILAsmParser : AsmParser { + string AsmParserClassName = "AsmParser"; + int Variant = 0; + + string CommentDelimiter = ";"; + + string RegisterPrefix = "r"; + +} + + +def AMDIL : Target { + // Pull in Instruction Info: + let InstructionSet = AMDILInstrInfo; + let AssemblyWriters = [AMDILAsmWriter]; + let AssemblyParsers = [AMDILAsmParser]; +} diff --git a/lib/Target/AMDIL/AMDILCallingConv.td b/lib/Target/AMDIL/AMDILCallingConv.td new file mode 100644 index 00000000000..ad4fe24088e --- /dev/null +++ b/lib/Target/AMDIL/AMDILCallingConv.td @@ -0,0 +1,562 @@ +//===- AMDILCallingConv.td - Calling Conventions AMDIL -----*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//==-----------------------------------------------------------------------===// +// +// This describes the calling conventions for the AMDIL architectures. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// Return Value Calling Conventions +//===----------------------------------------------------------------------===// + +// AMDIL 32-bit C return-value convention. +def RetCC_AMDIL32 : CallingConv<[ + // Since IL has no return values, all values can be emulated on the stack + // The stack can then be mapped to a number of sequential virtual registers + // in IL + + // Integer and FP scalar values get put on the stack at 16-byte alignment + // but with a size of 4 bytes + CCIfType<[i1, i8, i16, i32, f32, f64, i64], CCAssignToReg< + [ + R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, + R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, + R31, R32, R33, R34, R35, R36, R37, R38, R39, R40, R41, R42, R43, R44, + R45, R46, R47, R48, R49, R50, R51, R52, R53, R54, R55, R56, R57, R58, + R59, R60, R61, R62, R63, R64, R65, R66, R67, R68, R69, R70, R71, R72, + R73, R74, R75, R76, R77, R78, R79, R80, R81, R82, R83, R84, R85, R86, + R87, R88, R89, R90, R91, R92, R93, R94, R95, R96, R97, R98, R99, R100, + R101, R102, R103, R104, R105, R106, R107, R108, R109, R110, R111, R112, + R113, R114, R115, R116, R117, R118, R119, R120, R121, R122, R123, R124, + R125, R126, R127, R128, R129, R130, R131, R132, R133, R134, R135, R136, + R137, R138, R139, R140, R141, R142, R143, R144, R145, R146, R147, R148, + R149, R150, R151, R152, R153, R154, R155, R156, R157, R158, R159, R160, + R161, R162, R163, R164, R165, R166, R167, R168, R169, R170, R171, R172, + R173, R174, R175, R176, R177, R178, R179, R180, R181, R182, R183, R184, + R185, R186, R187, R188, R189, R190, R191, R192, R193, R194, R195, R196, + R197, R198, R199, R200, R201, R202, R203, R204, R205, R206, R207, R208, + R209, R210, R211, R212, R213, R214, R215, R216, R217, R218, R219, R220, + R221, R222, R223, R224, R225, R226, R227, R228, R229, R230, R231, R232, + R233, R234, R235, R236, R237, R238, R239, R240, R241, R242, R243, R244, + R245, R246, R247, R248, R249, R250, R251, R252, R253, R254, R255, R256, + R257, R258, R259, R260, R261, R262, R263, R264, R265, R266, R267, R268, + R269, R270, R271, R272, R273, R274, R275, R276, R277, R278, R279, R280, + R281, R282, R283, R284, R285, R286, R287, R288, R289, R290, R291, R292, + R293, R294, R295, R296, R297, R298, R299, R300, R301, R302, R303, R304, + R305, R306, R307, R308, R309, R310, R311, R312, R313, R314, R315, R316, + R317, R318, R319, R320, R321, R322, R323, R324, R325, R326, R327, R328, + R329, R330, R331, R332, R333, R334, R335, R336, R337, R338, R339, R340, + R341, R342, R343, R344, R345, R346, R347, R348, R349, R350, R351, R352, + R353, R354, R355, R356, R357, R358, R359, R360, R361, R362, R363, R364, + R365, R366, R367, R368, R369, R370, R371, R372, R373, R374, R375, R376, + R377, R378, R379, R380, R381, R382, R383, R384, R385, R386, R387, R388, + R389, R390, R391, R392, R393, R394, R395, R396, R397, R398, R399, R400, + R401, R402, R403, R404, R405, R406, R407, R408, R409, R410, R411, R412, + R413, R414, R415, R416, R417, R418, R419, R420, R421, R422, R423, R424, + R425, R426, R427, R428, R429, R430, R431, R432, R433, R434, R435, R436, + R437, R438, R439, R440, R441, R442, R443, R444, R445, R446, R447, R448, + R449, R450, R451, R452, R453, R454, R455, R456, R457, R458, R459, R460, + R461, R462, R463, R464, R465, R466, R467, R468, R469, R470, R471, R472, + R473, R474, R475, R476, R477, R478, R479, R480, R481, R482, R483, R484, + R485, R486, R487, R488, R489, R490, R491, R492, R493, R494, R495, R496, + R497, R498, R499, R500, R501, R502, R503, R504, R505, R506, R507, R508, + R509, R510, R511, R512, R513, R514, R515, R516, R517, R518, R519, R520, + R521, R522, R523, R524, R525, R526, R527, R528, R529, R530, R531, R532, + R533, R534, R535, R536, R537, R538, R539, R540, R541, R542, R543, R544, + R545, R546, R547, R548, R549, R550, R551, R552, R553, R554, R555, R556, + R557, R558, R559, R560, R561, R562, R563, R564, R565, R566, R567, R568, + R569, R570, R571, R572, R573, R574, R575, R576, R577, R578, R579, R580, + R581, R582, R583, R584, R585, R586, R587, R588, R589, R590, R591, R592, + R593, R594, R595, R596, R597, R598, R599, R600, R601, R602, R603, R604, + R605, R606, R607, R608, R609, R610, R611, R612, R613, R614, R615, R616, + R617, R618, R619, R620, R621, R622, R623, R624, R625, R626, R627, R628, + R629, R630, R631, R632, R633, R634, R635, R636, R637, R638, R639, R640, + R641, R642, R643, R644, R645, R646, R647, R648, R649, R650, R651, R652, + R653, R654, R655, R656, R657, R658, R659, R660, R661, R662, R663, R664, + R665, R666, R667, R668, R669, R670, R671, R672, R673, R674, R675, R676, + R677, R678, R679, R680, R681, R682, R683, R684, R685, R686, R687, R688, + R689, R690, R691, R692, R693, R694, R695, R696, R697, R698, R699, R700, + R701, R702, R703, R704, R705, R706, R707, R708, R709, R710, R711, R712, + R713, R714, R715, R716, R717, R718, R719, R720, R721, R722, R723, R724, + R725, R726, R727, R728, R729, R730, R731, R732, R733, R734, R735, R736, + R737, R738, R739, R740, R741, R742, R743, R744, R745, R746, R747, R748, + R749, R750, R751, R752, R753, R754, R755, R756, R757, R758, R759, R760, + R761, R762, R763, R764, R765, R766, R767 +]> >, + + // 2-element Short vector types get 16 byte alignment and size of 8 bytes + CCIfType<[v2i32, v2f32, v2i8, v4i8, v2i16, v4i16], CCAssignToReg< +[R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, +R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, +R31, R32, R33, R34, R35, R36, R37, R38, R39, R40, R41, R42, R43, R44, +R45, R46, R47, R48, R49, R50, R51, R52, R53, R54, R55, R56, R57, R58, +R59, R60, R61, R62, R63, R64, R65, R66, R67, R68, R69, R70, R71, R72, +R73, R74, R75, R76, R77, R78, R79, R80, R81, R82, R83, R84, R85, R86, +R87, R88, R89, R90, R91, R92, R93, R94, R95, R96, R97, R98, R99, R100, +R101, R102, R103, R104, R105, R106, R107, R108, R109, R110, R111, R112, +R113, R114, R115, R116, R117, R118, R119, R120, R121, R122, R123, R124, +R125, R126, R127, R128, R129, R130, R131, R132, R133, R134, R135, R136, +R137, R138, R139, R140, R141, R142, R143, R144, R145, R146, R147, R148, +R149, R150, R151, R152, R153, R154, R155, R156, R157, R158, R159, R160, +R161, R162, R163, R164, R165, R166, R167, R168, R169, R170, R171, R172, +R173, R174, R175, R176, R177, R178, R179, R180, R181, R182, R183, R184, +R185, R186, R187, R188, R189, R190, R191, R192, R193, R194, R195, R196, +R197, R198, R199, R200, R201, R202, R203, R204, R205, R206, R207, R208, +R209, R210, R211, R212, R213, R214, R215, R216, R217, R218, R219, R220, +R221, R222, R223, R224, R225, R226, R227, R228, R229, R230, R231, R232, +R233, R234, R235, R236, R237, R238, R239, R240, R241, R242, R243, R244, +R245, R246, R247, R248, R249, R250, R251, R252, R253, R254, R255, R256, +R257, R258, R259, R260, R261, R262, R263, R264, R265, R266, R267, R268, +R269, R270, R271, R272, R273, R274, R275, R276, R277, R278, R279, R280, +R281, R282, R283, R284, R285, R286, R287, R288, R289, R290, R291, R292, +R293, R294, R295, R296, R297, R298, R299, R300, R301, R302, R303, R304, +R305, R306, R307, R308, R309, R310, R311, R312, R313, R314, R315, R316, +R317, R318, R319, R320, R321, R322, R323, R324, R325, R326, R327, R328, +R329, R330, R331, R332, R333, R334, R335, R336, R337, R338, R339, R340, +R341, R342, R343, R344, R345, R346, R347, R348, R349, R350, R351, R352, +R353, R354, R355, R356, R357, R358, R359, R360, R361, R362, R363, R364, +R365, R366, R367, R368, R369, R370, R371, R372, R373, R374, R375, R376, +R377, R378, R379, R380, R381, R382, R383, R384, R385, R386, R387, R388, +R389, R390, R391, R392, R393, R394, R395, R396, R397, R398, R399, R400, +R401, R402, R403, R404, R405, R406, R407, R408, R409, R410, R411, R412, +R413, R414, R415, R416, R417, R418, R419, R420, R421, R422, R423, R424, +R425, R426, R427, R428, R429, R430, R431, R432, R433, R434, R435, R436, +R437, R438, R439, R440, R441, R442, R443, R444, R445, R446, R447, R448, +R449, R450, R451, R452, R453, R454, R455, R456, R457, R458, R459, R460, +R461, R462, R463, R464, R465, R466, R467, R468, R469, R470, R471, R472, +R473, R474, R475, R476, R477, R478, R479, R480, R481, R482, R483, R484, +R485, R486, R487, R488, R489, R490, R491, R492, R493, R494, R495, R496, +R497, R498, R499, R500, R501, R502, R503, R504, R505, R506, R507, R508, +R509, R510, R511, R512, R513, R514, R515, R516, R517, R518, R519, R520, +R521, R522, R523, R524, R525, R526, R527, R528, R529, R530, R531, R532, +R533, R534, R535, R536, R537, R538, R539, R540, R541, R542, R543, R544, +R545, R546, R547, R548, R549, R550, R551, R552, R553, R554, R555, R556, +R557, R558, R559, R560, R561, R562, R563, R564, R565, R566, R567, R568, +R569, R570, R571, R572, R573, R574, R575, R576, R577, R578, R579, R580, +R581, R582, R583, R584, R585, R586, R587, R588, R589, R590, R591, R592, +R593, R594, R595, R596, R597, R598, R599, R600, R601, R602, R603, R604, +R605, R606, R607, R608, R609, R610, R611, R612, R613, R614, R615, R616, +R617, R618, R619, R620, R621, R622, R623, R624, R625, R626, R627, R628, +R629, R630, R631, R632, R633, R634, R635, R636, R637, R638, R639, R640, +R641, R642, R643, R644, R645, R646, R647, R648, R649, R650, R651, R652, +R653, R654, R655, R656, R657, R658, R659, R660, R661, R662, R663, R664, +R665, R666, R667, R668, R669, R670, R671, R672, R673, R674, R675, R676, +R677, R678, R679, R680, R681, R682, R683, R684, R685, R686, R687, R688, +R689, R690, R691, R692, R693, R694, R695, R696, R697, R698, R699, R700, +R701, R702, R703, R704, R705, R706, R707, R708, R709, R710, R711, R712, +R713, R714, R715, R716, R717, R718, R719, R720, R721, R722, R723, R724, +R725, R726, R727, R728, R729, R730, R731, R732, R733, R734, R735, R736, +R737, R738, R739, R740, R741, R742, R743, R744, R745, R746, R747, R748, +R749, R750, R751, R752, R753, R754, R755, R756, R757, R758, R759, R760, +R761, R762, R763, R764, R765, R766, R767 ]> >, + + // 4-element Short vector types get 16 byte alignment and size of 16 bytes + CCIfType<[v4i32, v4f32], CCAssignToReg< +[R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, +R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, +R31, R32, R33, R34, R35, R36, R37, R38, R39, R40, R41, R42, R43, R44, +R45, R46, R47, R48, R49, R50, R51, R52, R53, R54, R55, R56, R57, R58, +R59, R60, R61, R62, R63, R64, R65, R66, R67, R68, R69, R70, R71, R72, +R73, R74, R75, R76, R77, R78, R79, R80, R81, R82, R83, R84, R85, R86, +R87, R88, R89, R90, R91, R92, R93, R94, R95, R96, R97, R98, R99, R100, +R101, R102, R103, R104, R105, R106, R107, R108, R109, R110, R111, R112, +R113, R114, R115, R116, R117, R118, R119, R120, R121, R122, R123, R124, +R125, R126, R127, R128, R129, R130, R131, R132, R133, R134, R135, R136, +R137, R138, R139, R140, R141, R142, R143, R144, R145, R146, R147, R148, +R149, R150, R151, R152, R153, R154, R155, R156, R157, R158, R159, R160, +R161, R162, R163, R164, R165, R166, R167, R168, R169, R170, R171, R172, +R173, R174, R175, R176, R177, R178, R179, R180, R181, R182, R183, R184, +R185, R186, R187, R188, R189, R190, R191, R192, R193, R194, R195, R196, +R197, R198, R199, R200, R201, R202, R203, R204, R205, R206, R207, R208, +R209, R210, R211, R212, R213, R214, R215, R216, R217, R218, R219, R220, +R221, R222, R223, R224, R225, R226, R227, R228, R229, R230, R231, R232, +R233, R234, R235, R236, R237, R238, R239, R240, R241, R242, R243, R244, +R245, R246, R247, R248, R249, R250, R251, R252, R253, R254, R255, R256, +R257, R258, R259, R260, R261, R262, R263, R264, R265, R266, R267, R268, +R269, R270, R271, R272, R273, R274, R275, R276, R277, R278, R279, R280, +R281, R282, R283, R284, R285, R286, R287, R288, R289, R290, R291, R292, +R293, R294, R295, R296, R297, R298, R299, R300, R301, R302, R303, R304, +R305, R306, R307, R308, R309, R310, R311, R312, R313, R314, R315, R316, +R317, R318, R319, R320, R321, R322, R323, R324, R325, R326, R327, R328, +R329, R330, R331, R332, R333, R334, R335, R336, R337, R338, R339, R340, +R341, R342, R343, R344, R345, R346, R347, R348, R349, R350, R351, R352, +R353, R354, R355, R356, R357, R358, R359, R360, R361, R362, R363, R364, +R365, R366, R367, R368, R369, R370, R371, R372, R373, R374, R375, R376, +R377, R378, R379, R380, R381, R382, R383, R384, R385, R386, R387, R388, +R389, R390, R391, R392, R393, R394, R395, R396, R397, R398, R399, R400, +R401, R402, R403, R404, R405, R406, R407, R408, R409, R410, R411, R412, +R413, R414, R415, R416, R417, R418, R419, R420, R421, R422, R423, R424, +R425, R426, R427, R428, R429, R430, R431, R432, R433, R434, R435, R436, +R437, R438, R439, R440, R441, R442, R443, R444, R445, R446, R447, R448, +R449, R450, R451, R452, R453, R454, R455, R456, R457, R458, R459, R460, +R461, R462, R463, R464, R465, R466, R467, R468, R469, R470, R471, R472, +R473, R474, R475, R476, R477, R478, R479, R480, R481, R482, R483, R484, +R485, R486, R487, R488, R489, R490, R491, R492, R493, R494, R495, R496, +R497, R498, R499, R500, R501, R502, R503, R504, R505, R506, R507, R508, +R509, R510, R511, R512, R513, R514, R515, R516, R517, R518, R519, R520, +R521, R522, R523, R524, R525, R526, R527, R528, R529, R530, R531, R532, +R533, R534, R535, R536, R537, R538, R539, R540, R541, R542, R543, R544, +R545, R546, R547, R548, R549, R550, R551, R552, R553, R554, R555, R556, +R557, R558, R559, R560, R561, R562, R563, R564, R565, R566, R567, R568, +R569, R570, R571, R572, R573, R574, R575, R576, R577, R578, R579, R580, +R581, R582, R583, R584, R585, R586, R587, R588, R589, R590, R591, R592, +R593, R594, R595, R596, R597, R598, R599, R600, R601, R602, R603, R604, +R605, R606, R607, R608, R609, R610, R611, R612, R613, R614, R615, R616, +R617, R618, R619, R620, R621, R622, R623, R624, R625, R626, R627, R628, +R629, R630, R631, R632, R633, R634, R635, R636, R637, R638, R639, R640, +R641, R642, R643, R644, R645, R646, R647, R648, R649, R650, R651, R652, +R653, R654, R655, R656, R657, R658, R659, R660, R661, R662, R663, R664, +R665, R666, R667, R668, R669, R670, R671, R672, R673, R674, R675, R676, +R677, R678, R679, R680, R681, R682, R683, R684, R685, R686, R687, R688, +R689, R690, R691, R692, R693, R694, R695, R696, R697, R698, R699, R700, +R701, R702, R703, R704, R705, R706, R707, R708, R709, R710, R711, R712, +R713, R714, R715, R716, R717, R718, R719, R720, R721, R722, R723, R724, +R725, R726, R727, R728, R729, R730, R731, R732, R733, R734, R735, R736, +R737, R738, R739, R740, R741, R742, R743, R744, R745, R746, R747, R748, +R749, R750, R751, R752, R753, R754, R755, R756, R757, R758, R759, R760, +R761, R762, R763, R764, R765, R766, R767 ]> >, + + // 2-element 64-bit vector types get aligned to 16 bytes with a size of 16 bytes + CCIfType<[v2f64, v2i64], CCAssignToReg< +[R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, +R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, +R31, R32, R33, R34, R35, R36, R37, R38, R39, R40, R41, R42, R43, R44, +R45, R46, R47, R48, R49, R50, R51, R52, R53, R54, R55, R56, R57, R58, +R59, R60, R61, R62, R63, R64, R65, R66, R67, R68, R69, R70, R71, R72, +R73, R74, R75, R76, R77, R78, R79, R80, R81, R82, R83, R84, R85, R86, +R87, R88, R89, R90, R91, R92, R93, R94, R95, R96, R97, R98, R99, R100, +R101, R102, R103, R104, R105, R106, R107, R108, R109, R110, R111, R112, +R113, R114, R115, R116, R117, R118, R119, R120, R121, R122, R123, R124, +R125, R126, R127, R128, R129, R130, R131, R132, R133, R134, R135, R136, +R137, R138, R139, R140, R141, R142, R143, R144, R145, R146, R147, R148, +R149, R150, R151, R152, R153, R154, R155, R156, R157, R158, R159, R160, +R161, R162, R163, R164, R165, R166, R167, R168, R169, R170, R171, R172, +R173, R174, R175, R176, R177, R178, R179, R180, R181, R182, R183, R184, +R185, R186, R187, R188, R189, R190, R191, R192, R193, R194, R195, R196, +R197, R198, R199, R200, R201, R202, R203, R204, R205, R206, R207, R208, +R209, R210, R211, R212, R213, R214, R215, R216, R217, R218, R219, R220, +R221, R222, R223, R224, R225, R226, R227, R228, R229, R230, R231, R232, +R233, R234, R235, R236, R237, R238, R239, R240, R241, R242, R243, R244, +R245, R246, R247, R248, R249, R250, R251, R252, R253, R254, R255, R256, +R257, R258, R259, R260, R261, R262, R263, R264, R265, R266, R267, R268, +R269, R270, R271, R272, R273, R274, R275, R276, R277, R278, R279, R280, +R281, R282, R283, R284, R285, R286, R287, R288, R289, R290, R291, R292, +R293, R294, R295, R296, R297, R298, R299, R300, R301, R302, R303, R304, +R305, R306, R307, R308, R309, R310, R311, R312, R313, R314, R315, R316, +R317, R318, R319, R320, R321, R322, R323, R324, R325, R326, R327, R328, +R329, R330, R331, R332, R333, R334, R335, R336, R337, R338, R339, R340, +R341, R342, R343, R344, R345, R346, R347, R348, R349, R350, R351, R352, +R353, R354, R355, R356, R357, R358, R359, R360, R361, R362, R363, R364, +R365, R366, R367, R368, R369, R370, R371, R372, R373, R374, R375, R376, +R377, R378, R379, R380, R381, R382, R383, R384, R385, R386, R387, R388, +R389, R390, R391, R392, R393, R394, R395, R396, R397, R398, R399, R400, +R401, R402, R403, R404, R405, R406, R407, R408, R409, R410, R411, R412, +R413, R414, R415, R416, R417, R418, R419, R420, R421, R422, R423, R424, +R425, R426, R427, R428, R429, R430, R431, R432, R433, R434, R435, R436, +R437, R438, R439, R440, R441, R442, R443, R444, R445, R446, R447, R448, +R449, R450, R451, R452, R453, R454, R455, R456, R457, R458, R459, R460, +R461, R462, R463, R464, R465, R466, R467, R468, R469, R470, R471, R472, +R473, R474, R475, R476, R477, R478, R479, R480, R481, R482, R483, R484, +R485, R486, R487, R488, R489, R490, R491, R492, R493, R494, R495, R496, +R497, R498, R499, R500, R501, R502, R503, R504, R505, R506, R507, R508, +R509, R510, R511, R512, R513, R514, R515, R516, R517, R518, R519, R520, +R521, R522, R523, R524, R525, R526, R527, R528, R529, R530, R531, R532, +R533, R534, R535, R536, R537, R538, R539, R540, R541, R542, R543, R544, +R545, R546, R547, R548, R549, R550, R551, R552, R553, R554, R555, R556, +R557, R558, R559, R560, R561, R562, R563, R564, R565, R566, R567, R568, +R569, R570, R571, R572, R573, R574, R575, R576, R577, R578, R579, R580, +R581, R582, R583, R584, R585, R586, R587, R588, R589, R590, R591, R592, +R593, R594, R595, R596, R597, R598, R599, R600, R601, R602, R603, R604, +R605, R606, R607, R608, R609, R610, R611, R612, R613, R614, R615, R616, +R617, R618, R619, R620, R621, R622, R623, R624, R625, R626, R627, R628, +R629, R630, R631, R632, R633, R634, R635, R636, R637, R638, R639, R640, +R641, R642, R643, R644, R645, R646, R647, R648, R649, R650, R651, R652, +R653, R654, R655, R656, R657, R658, R659, R660, R661, R662, R663, R664, +R665, R666, R667, R668, R669, R670, R671, R672, R673, R674, R675, R676, +R677, R678, R679, R680, R681, R682, R683, R684, R685, R686, R687, R688, +R689, R690, R691, R692, R693, R694, R695, R696, R697, R698, R699, R700, +R701, R702, R703, R704, R705, R706, R707, R708, R709, R710, R711, R712, +R713, R714, R715, R716, R717, R718, R719, R720, R721, R722, R723, R724, +R725, R726, R727, R728, R729, R730, R731, R732, R733, R734, R735, R736, +R737, R738, R739, R740, R741, R742, R743, R744, R745, R746, R747, R748, +R749, R750, R751, R752, R753, R754, R755, R756, R757, R758, R759, R760, +R761, R762, R763, R764, R765, R766, R767 ]> >, CCAssignToStack<16, 16> ]>; + +// AMDIL 32-bit C Calling convention. +def CC_AMDIL32 : CallingConv<[ + // Since IL has parameter values, all values can be emulated on the stack + // The stack can then be mapped to a number of sequential virtual registers + // in IL + // Integer and FP scalar values get put on the stack at 16-byte alignment + // but with a size of 4 bytes + // Integer and FP scalar values get put on the stack at 16-byte alignment + // but with a size of 4 bytes + CCIfType<[i1, i8, i16, i32, f32, f64, i64], CCAssignToReg< +[R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, +R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, +R31, R32, R33, R34, R35, R36, R37, R38, R39, R40, R41, R42, R43, R44, +R45, R46, R47, R48, R49, R50, R51, R52, R53, R54, R55, R56, R57, R58, +R59, R60, R61, R62, R63, R64, R65, R66, R67, R68, R69, R70, R71, R72, +R73, R74, R75, R76, R77, R78, R79, R80, R81, R82, R83, R84, R85, R86, +R87, R88, R89, R90, R91, R92, R93, R94, R95, R96, R97, R98, R99, R100, +R101, R102, R103, R104, R105, R106, R107, R108, R109, R110, R111, R112, +R113, R114, R115, R116, R117, R118, R119, R120, R121, R122, R123, R124, +R125, R126, R127, R128, R129, R130, R131, R132, R133, R134, R135, R136, +R137, R138, R139, R140, R141, R142, R143, R144, R145, R146, R147, R148, +R149, R150, R151, R152, R153, R154, R155, R156, R157, R158, R159, R160, +R161, R162, R163, R164, R165, R166, R167, R168, R169, R170, R171, R172, +R173, R174, R175, R176, R177, R178, R179, R180, R181, R182, R183, R184, +R185, R186, R187, R188, R189, R190, R191, R192, R193, R194, R195, R196, +R197, R198, R199, R200, R201, R202, R203, R204, R205, R206, R207, R208, +R209, R210, R211, R212, R213, R214, R215, R216, R217, R218, R219, R220, +R221, R222, R223, R224, R225, R226, R227, R228, R229, R230, R231, R232, +R233, R234, R235, R236, R237, R238, R239, R240, R241, R242, R243, R244, +R245, R246, R247, R248, R249, R250, R251, R252, R253, R254, R255, R256, +R257, R258, R259, R260, R261, R262, R263, R264, R265, R266, R267, R268, +R269, R270, R271, R272, R273, R274, R275, R276, R277, R278, R279, R280, +R281, R282, R283, R284, R285, R286, R287, R288, R289, R290, R291, R292, +R293, R294, R295, R296, R297, R298, R299, R300, R301, R302, R303, R304, +R305, R306, R307, R308, R309, R310, R311, R312, R313, R314, R315, R316, +R317, R318, R319, R320, R321, R322, R323, R324, R325, R326, R327, R328, +R329, R330, R331, R332, R333, R334, R335, R336, R337, R338, R339, R340, +R341, R342, R343, R344, R345, R346, R347, R348, R349, R350, R351, R352, +R353, R354, R355, R356, R357, R358, R359, R360, R361, R362, R363, R364, +R365, R366, R367, R368, R369, R370, R371, R372, R373, R374, R375, R376, +R377, R378, R379, R380, R381, R382, R383, R384, R385, R386, R387, R388, +R389, R390, R391, R392, R393, R394, R395, R396, R397, R398, R399, R400, +R401, R402, R403, R404, R405, R406, R407, R408, R409, R410, R411, R412, +R413, R414, R415, R416, R417, R418, R419, R420, R421, R422, R423, R424, +R425, R426, R427, R428, R429, R430, R431, R432, R433, R434, R435, R436, +R437, R438, R439, R440, R441, R442, R443, R444, R445, R446, R447, R448, +R449, R450, R451, R452, R453, R454, R455, R456, R457, R458, R459, R460, +R461, R462, R463, R464, R465, R466, R467, R468, R469, R470, R471, R472, +R473, R474, R475, R476, R477, R478, R479, R480, R481, R482, R483, R484, +R485, R486, R487, R488, R489, R490, R491, R492, R493, R494, R495, R496, +R497, R498, R499, R500, R501, R502, R503, R504, R505, R506, R507, R508, +R509, R510, R511, R512, R513, R514, R515, R516, R517, R518, R519, R520, +R521, R522, R523, R524, R525, R526, R527, R528, R529, R530, R531, R532, +R533, R534, R535, R536, R537, R538, R539, R540, R541, R542, R543, R544, +R545, R546, R547, R548, R549, R550, R551, R552, R553, R554, R555, R556, +R557, R558, R559, R560, R561, R562, R563, R564, R565, R566, R567, R568, +R569, R570, R571, R572, R573, R574, R575, R576, R577, R578, R579, R580, +R581, R582, R583, R584, R585, R586, R587, R588, R589, R590, R591, R592, +R593, R594, R595, R596, R597, R598, R599, R600, R601, R602, R603, R604, +R605, R606, R607, R608, R609, R610, R611, R612, R613, R614, R615, R616, +R617, R618, R619, R620, R621, R622, R623, R624, R625, R626, R627, R628, +R629, R630, R631, R632, R633, R634, R635, R636, R637, R638, R639, R640, +R641, R642, R643, R644, R645, R646, R647, R648, R649, R650, R651, R652, +R653, R654, R655, R656, R657, R658, R659, R660, R661, R662, R663, R664, +R665, R666, R667, R668, R669, R670, R671, R672, R673, R674, R675, R676, +R677, R678, R679, R680, R681, R682, R683, R684, R685, R686, R687, R688, +R689, R690, R691, R692, R693, R694, R695, R696, R697, R698, R699, R700, +R701, R702, R703, R704, R705, R706, R707, R708, R709, R710, R711, R712, +R713, R714, R715, R716, R717, R718, R719, R720, R721, R722, R723, R724, +R725, R726, R727, R728, R729, R730, R731, R732, R733, R734, R735, R736, +R737, R738, R739, R740, R741, R742, R743, R744, R745, R746, R747, R748, +R749, R750, R751, R752, R753, R754, R755, R756, R757, R758, R759, R760, +R761, R762, R763, R764, R765, R766, R767 ]> >, + + // 2-element Short vector types get 16 byte alignment and size of 8 bytes + CCIfType<[v2i32, v2f32, v2i8, v4i8, v2i16, v4i16], CCAssignToReg< +[R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, +R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, +R31, R32, R33, R34, R35, R36, R37, R38, R39, R40, R41, R42, R43, R44, +R45, R46, R47, R48, R49, R50, R51, R52, R53, R54, R55, R56, R57, R58, +R59, R60, R61, R62, R63, R64, R65, R66, R67, R68, R69, R70, R71, R72, +R73, R74, R75, R76, R77, R78, R79, R80, R81, R82, R83, R84, R85, R86, +R87, R88, R89, R90, R91, R92, R93, R94, R95, R96, R97, R98, R99, R100, +R101, R102, R103, R104, R105, R106, R107, R108, R109, R110, R111, R112, +R113, R114, R115, R116, R117, R118, R119, R120, R121, R122, R123, R124, +R125, R126, R127, R128, R129, R130, R131, R132, R133, R134, R135, R136, +R137, R138, R139, R140, R141, R142, R143, R144, R145, R146, R147, R148, +R149, R150, R151, R152, R153, R154, R155, R156, R157, R158, R159, R160, +R161, R162, R163, R164, R165, R166, R167, R168, R169, R170, R171, R172, +R173, R174, R175, R176, R177, R178, R179, R180, R181, R182, R183, R184, +R185, R186, R187, R188, R189, R190, R191, R192, R193, R194, R195, R196, +R197, R198, R199, R200, R201, R202, R203, R204, R205, R206, R207, R208, +R209, R210, R211, R212, R213, R214, R215, R216, R217, R218, R219, R220, +R221, R222, R223, R224, R225, R226, R227, R228, R229, R230, R231, R232, +R233, R234, R235, R236, R237, R238, R239, R240, R241, R242, R243, R244, +R245, R246, R247, R248, R249, R250, R251, R252, R253, R254, R255, R256, +R257, R258, R259, R260, R261, R262, R263, R264, R265, R266, R267, R268, +R269, R270, R271, R272, R273, R274, R275, R276, R277, R278, R279, R280, +R281, R282, R283, R284, R285, R286, R287, R288, R289, R290, R291, R292, +R293, R294, R295, R296, R297, R298, R299, R300, R301, R302, R303, R304, +R305, R306, R307, R308, R309, R310, R311, R312, R313, R314, R315, R316, +R317, R318, R319, R320, R321, R322, R323, R324, R325, R326, R327, R328, +R329, R330, R331, R332, R333, R334, R335, R336, R337, R338, R339, R340, +R341, R342, R343, R344, R345, R346, R347, R348, R349, R350, R351, R352, +R353, R354, R355, R356, R357, R358, R359, R360, R361, R362, R363, R364, +R365, R366, R367, R368, R369, R370, R371, R372, R373, R374, R375, R376, +R377, R378, R379, R380, R381, R382, R383, R384, R385, R386, R387, R388, +R389, R390, R391, R392, R393, R394, R395, R396, R397, R398, R399, R400, +R401, R402, R403, R404, R405, R406, R407, R408, R409, R410, R411, R412, +R413, R414, R415, R416, R417, R418, R419, R420, R421, R422, R423, R424, +R425, R426, R427, R428, R429, R430, R431, R432, R433, R434, R435, R436, +R437, R438, R439, R440, R441, R442, R443, R444, R445, R446, R447, R448, +R449, R450, R451, R452, R453, R454, R455, R456, R457, R458, R459, R460, +R461, R462, R463, R464, R465, R466, R467, R468, R469, R470, R471, R472, +R473, R474, R475, R476, R477, R478, R479, R480, R481, R482, R483, R484, +R485, R486, R487, R488, R489, R490, R491, R492, R493, R494, R495, R496, +R497, R498, R499, R500, R501, R502, R503, R504, R505, R506, R507, R508, +R509, R510, R511, R512, R513, R514, R515, R516, R517, R518, R519, R520, +R521, R522, R523, R524, R525, R526, R527, R528, R529, R530, R531, R532, +R533, R534, R535, R536, R537, R538, R539, R540, R541, R542, R543, R544, +R545, R546, R547, R548, R549, R550, R551, R552, R553, R554, R555, R556, +R557, R558, R559, R560, R561, R562, R563, R564, R565, R566, R567, R568, +R569, R570, R571, R572, R573, R574, R575, R576, R577, R578, R579, R580, +R581, R582, R583, R584, R585, R586, R587, R588, R589, R590, R591, R592, +R593, R594, R595, R596, R597, R598, R599, R600, R601, R602, R603, R604, +R605, R606, R607, R608, R609, R610, R611, R612, R613, R614, R615, R616, +R617, R618, R619, R620, R621, R622, R623, R624, R625, R626, R627, R628, +R629, R630, R631, R632, R633, R634, R635, R636, R637, R638, R639, R640, +R641, R642, R643, R644, R645, R646, R647, R648, R649, R650, R651, R652, +R653, R654, R655, R656, R657, R658, R659, R660, R661, R662, R663, R664, +R665, R666, R667, R668, R669, R670, R671, R672, R673, R674, R675, R676, +R677, R678, R679, R680, R681, R682, R683, R684, R685, R686, R687, R688, +R689, R690, R691, R692, R693, R694, R695, R696, R697, R698, R699, R700, +R701, R702, R703, R704, R705, R706, R707, R708, R709, R710, R711, R712, +R713, R714, R715, R716, R717, R718, R719, R720, R721, R722, R723, R724, +R725, R726, R727, R728, R729, R730, R731, R732, R733, R734, R735, R736, +R737, R738, R739, R740, R741, R742, R743, R744, R745, R746, R747, R748, +R749, R750, R751, R752, R753, R754, R755, R756, R757, R758, R759, R760, +R761, R762, R763, R764, R765, R766, R767 ]> >, + + // 4-element Short vector types get 16 byte alignment and size of 16 bytes + CCIfType<[v4i32, v4f32], CCAssignToReg< +[R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, +R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, +R31, R32, R33, R34, R35, R36, R37, R38, R39, R40, R41, R42, R43, R44, +R45, R46, R47, R48, R49, R50, R51, R52, R53, R54, R55, R56, R57, R58, +R59, R60, R61, R62, R63, R64, R65, R66, R67, R68, R69, R70, R71, R72, +R73, R74, R75, R76, R77, R78, R79, R80, R81, R82, R83, R84, R85, R86, +R87, R88, R89, R90, R91, R92, R93, R94, R95, R96, R97, R98, R99, R100, +R101, R102, R103, R104, R105, R106, R107, R108, R109, R110, R111, R112, +R113, R114, R115, R116, R117, R118, R119, R120, R121, R122, R123, R124, +R125, R126, R127, R128, R129, R130, R131, R132, R133, R134, R135, R136, +R137, R138, R139, R140, R141, R142, R143, R144, R145, R146, R147, R148, +R149, R150, R151, R152, R153, R154, R155, R156, R157, R158, R159, R160, +R161, R162, R163, R164, R165, R166, R167, R168, R169, R170, R171, R172, +R173, R174, R175, R176, R177, R178, R179, R180, R181, R182, R183, R184, +R185, R186, R187, R188, R189, R190, R191, R192, R193, R194, R195, R196, +R197, R198, R199, R200, R201, R202, R203, R204, R205, R206, R207, R208, +R209, R210, R211, R212, R213, R214, R215, R216, R217, R218, R219, R220, +R221, R222, R223, R224, R225, R226, R227, R228, R229, R230, R231, R232, +R233, R234, R235, R236, R237, R238, R239, R240, R241, R242, R243, R244, +R245, R246, R247, R248, R249, R250, R251, R252, R253, R254, R255, R256, +R257, R258, R259, R260, R261, R262, R263, R264, R265, R266, R267, R268, +R269, R270, R271, R272, R273, R274, R275, R276, R277, R278, R279, R280, +R281, R282, R283, R284, R285, R286, R287, R288, R289, R290, R291, R292, +R293, R294, R295, R296, R297, R298, R299, R300, R301, R302, R303, R304, +R305, R306, R307, R308, R309, R310, R311, R312, R313, R314, R315, R316, +R317, R318, R319, R320, R321, R322, R323, R324, R325, R326, R327, R328, +R329, R330, R331, R332, R333, R334, R335, R336, R337, R338, R339, R340, +R341, R342, R343, R344, R345, R346, R347, R348, R349, R350, R351, R352, +R353, R354, R355, R356, R357, R358, R359, R360, R361, R362, R363, R364, +R365, R366, R367, R368, R369, R370, R371, R372, R373, R374, R375, R376, +R377, R378, R379, R380, R381, R382, R383, R384, R385, R386, R387, R388, +R389, R390, R391, R392, R393, R394, R395, R396, R397, R398, R399, R400, +R401, R402, R403, R404, R405, R406, R407, R408, R409, R410, R411, R412, +R413, R414, R415, R416, R417, R418, R419, R420, R421, R422, R423, R424, +R425, R426, R427, R428, R429, R430, R431, R432, R433, R434, R435, R436, +R437, R438, R439, R440, R441, R442, R443, R444, R445, R446, R447, R448, +R449, R450, R451, R452, R453, R454, R455, R456, R457, R458, R459, R460, +R461, R462, R463, R464, R465, R466, R467, R468, R469, R470, R471, R472, +R473, R474, R475, R476, R477, R478, R479, R480, R481, R482, R483, R484, +R485, R486, R487, R488, R489, R490, R491, R492, R493, R494, R495, R496, +R497, R498, R499, R500, R501, R502, R503, R504, R505, R506, R507, R508, +R509, R510, R511, R512, R513, R514, R515, R516, R517, R518, R519, R520, +R521, R522, R523, R524, R525, R526, R527, R528, R529, R530, R531, R532, +R533, R534, R535, R536, R537, R538, R539, R540, R541, R542, R543, R544, +R545, R546, R547, R548, R549, R550, R551, R552, R553, R554, R555, R556, +R557, R558, R559, R560, R561, R562, R563, R564, R565, R566, R567, R568, +R569, R570, R571, R572, R573, R574, R575, R576, R577, R578, R579, R580, +R581, R582, R583, R584, R585, R586, R587, R588, R589, R590, R591, R592, +R593, R594, R595, R596, R597, R598, R599, R600, R601, R602, R603, R604, +R605, R606, R607, R608, R609, R610, R611, R612, R613, R614, R615, R616, +R617, R618, R619, R620, R621, R622, R623, R624, R625, R626, R627, R628, +R629, R630, R631, R632, R633, R634, R635, R636, R637, R638, R639, R640, +R641, R642, R643, R644, R645, R646, R647, R648, R649, R650, R651, R652, +R653, R654, R655, R656, R657, R658, R659, R660, R661, R662, R663, R664, +R665, R666, R667, R668, R669, R670, R671, R672, R673, R674, R675, R676, +R677, R678, R679, R680, R681, R682, R683, R684, R685, R686, R687, R688, +R689, R690, R691, R692, R693, R694, R695, R696, R697, R698, R699, R700, +R701, R702, R703, R704, R705, R706, R707, R708, R709, R710, R711, R712, +R713, R714, R715, R716, R717, R718, R719, R720, R721, R722, R723, R724, +R725, R726, R727, R728, R729, R730, R731, R732, R733, R734, R735, R736, +R737, R738, R739, R740, R741, R742, R743, R744, R745, R746, R747, R748, +R749, R750, R751, R752, R753, R754, R755, R756, R757, R758, R759, R760, +R761, R762, R763, R764, R765, R766, R767 ]> >, + + // 2-element 64-bit vector types get aligned to 16 bytes with a size of 16 bytes + CCIfType<[v2f64, v2i64], CCAssignToReg< +[R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, +R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, +R31, R32, R33, R34, R35, R36, R37, R38, R39, R40, R41, R42, R43, R44, +R45, R46, R47, R48, R49, R50, R51, R52, R53, R54, R55, R56, R57, R58, +R59, R60, R61, R62, R63, R64, R65, R66, R67, R68, R69, R70, R71, R72, +R73, R74, R75, R76, R77, R78, R79, R80, R81, R82, R83, R84, R85, R86, +R87, R88, R89, R90, R91, R92, R93, R94, R95, R96, R97, R98, R99, R100, +R101, R102, R103, R104, R105, R106, R107, R108, R109, R110, R111, R112, +R113, R114, R115, R116, R117, R118, R119, R120, R121, R122, R123, R124, +R125, R126, R127, R128, R129, R130, R131, R132, R133, R134, R135, R136, +R137, R138, R139, R140, R141, R142, R143, R144, R145, R146, R147, R148, +R149, R150, R151, R152, R153, R154, R155, R156, R157, R158, R159, R160, +R161, R162, R163, R164, R165, R166, R167, R168, R169, R170, R171, R172, +R173, R174, R175, R176, R177, R178, R179, R180, R181, R182, R183, R184, +R185, R186, R187, R188, R189, R190, R191, R192, R193, R194, R195, R196, +R197, R198, R199, R200, R201, R202, R203, R204, R205, R206, R207, R208, +R209, R210, R211, R212, R213, R214, R215, R216, R217, R218, R219, R220, +R221, R222, R223, R224, R225, R226, R227, R228, R229, R230, R231, R232, +R233, R234, R235, R236, R237, R238, R239, R240, R241, R242, R243, R244, +R245, R246, R247, R248, R249, R250, R251, R252, R253, R254, R255, R256, +R257, R258, R259, R260, R261, R262, R263, R264, R265, R266, R267, R268, +R269, R270, R271, R272, R273, R274, R275, R276, R277, R278, R279, R280, +R281, R282, R283, R284, R285, R286, R287, R288, R289, R290, R291, R292, +R293, R294, R295, R296, R297, R298, R299, R300, R301, R302, R303, R304, +R305, R306, R307, R308, R309, R310, R311, R312, R313, R314, R315, R316, +R317, R318, R319, R320, R321, R322, R323, R324, R325, R326, R327, R328, +R329, R330, R331, R332, R333, R334, R335, R336, R337, R338, R339, R340, +R341, R342, R343, R344, R345, R346, R347, R348, R349, R350, R351, R352, +R353, R354, R355, R356, R357, R358, R359, R360, R361, R362, R363, R364, +R365, R366, R367, R368, R369, R370, R371, R372, R373, R374, R375, R376, +R377, R378, R379, R380, R381, R382, R383, R384, R385, R386, R387, R388, +R389, R390, R391, R392, R393, R394, R395, R396, R397, R398, R399, R400, +R401, R402, R403, R404, R405, R406, R407, R408, R409, R410, R411, R412, +R413, R414, R415, R416, R417, R418, R419, R420, R421, R422, R423, R424, +R425, R426, R427, R428, R429, R430, R431, R432, R433, R434, R435, R436, +R437, R438, R439, R440, R441, R442, R443, R444, R445, R446, R447, R448, +R449, R450, R451, R452, R453, R454, R455, R456, R457, R458, R459, R460, +R461, R462, R463, R464, R465, R466, R467, R468, R469, R470, R471, R472, +R473, R474, R475, R476, R477, R478, R479, R480, R481, R482, R483, R484, +R485, R486, R487, R488, R489, R490, R491, R492, R493, R494, R495, R496, +R497, R498, R499, R500, R501, R502, R503, R504, R505, R506, R507, R508, +R509, R510, R511, R512, R513, R514, R515, R516, R517, R518, R519, R520, +R521, R522, R523, R524, R525, R526, R527, R528, R529, R530, R531, R532, +R533, R534, R535, R536, R537, R538, R539, R540, R541, R542, R543, R544, +R545, R546, R547, R548, R549, R550, R551, R552, R553, R554, R555, R556, +R557, R558, R559, R560, R561, R562, R563, R564, R565, R566, R567, R568, +R569, R570, R571, R572, R573, R574, R575, R576, R577, R578, R579, R580, +R581, R582, R583, R584, R585, R586, R587, R588, R589, R590, R591, R592, +R593, R594, R595, R596, R597, R598, R599, R600, R601, R602, R603, R604, +R605, R606, R607, R608, R609, R610, R611, R612, R613, R614, R615, R616, +R617, R618, R619, R620, R621, R622, R623, R624, R625, R626, R627, R628, +R629, R630, R631, R632, R633, R634, R635, R636, R637, R638, R639, R640, +R641, R642, R643, R644, R645, R646, R647, R648, R649, R650, R651, R652, +R653, R654, R655, R656, R657, R658, R659, R660, R661, R662, R663, R664, +R665, R666, R667, R668, R669, R670, R671, R672, R673, R674, R675, R676, +R677, R678, R679, R680, R681, R682, R683, R684, R685, R686, R687, R688, +R689, R690, R691, R692, R693, R694, R695, R696, R697, R698, R699, R700, +R701, R702, R703, R704, R705, R706, R707, R708, R709, R710, R711, R712, +R713, R714, R715, R716, R717, R718, R719, R720, R721, R722, R723, R724, +R725, R726, R727, R728, R729, R730, R731, R732, R733, R734, R735, R736, +R737, R738, R739, R740, R741, R742, R743, R744, R745, R746, R747, R748, +R749, R750, R751, R752, R753, R754, R755, R756, R757, R758, R759, R760, +R761, R762, R763, R764, R765, R766, R767 ]> >, CCAssignToStack<16, 16> ]>; + diff --git a/lib/Target/AMDIL/AMDILConversions.td b/lib/Target/AMDIL/AMDILConversions.td new file mode 100644 index 00000000000..1bc5e4ddf37 --- /dev/null +++ b/lib/Target/AMDIL/AMDILConversions.td @@ -0,0 +1,1022 @@ +//==- AMDILConversions.td - Type conversion tablegen patterns -*-tablegen -*-=// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//==-----------------------------------------------------------------------===// +def actos_i16:Pat < (i16 (anyext GPRI8:$src)), +(IL_ASSHORT_i32 + (USHR_i32 + (SHL_i32 +(IL_ASINT_i8 GPRI8:$src), + (LOADCONST_i32 24)), + (LOADCONST_i32 24))) >; + + +def uctos_i16:Pat < (i16 (zext GPRI8:$src)), +(IL_ASSHORT_i32 + (USHR_i32 + (SHL_i32 +(IL_ASINT_i8 GPRI8:$src), + (LOADCONST_i32 24)), + (LOADCONST_i32 24))) >; + + +def sctos_i16:Pat < (i16 (sext GPRI8:$src)), +(IL_ASSHORT_i32 + (SHR_i32 + (SHL_i32 +(IL_ASINT_i8 GPRI8:$src), + (LOADCONST_i32 24)), + (LOADCONST_i32 24))) >; + + +def actoi_i32:Pat < (i32 (anyext GPRI8:$src)), +(IL_ASINT_i32 + (USHR_i32 + (SHL_i32 +(IL_ASINT_i8 GPRI8:$src), + (LOADCONST_i32 24)), + (LOADCONST_i32 24))) >; + + +def uctoi_i32:Pat < (i32 (zext GPRI8:$src)), +(IL_ASINT_i32 + (USHR_i32 + (SHL_i32 +(IL_ASINT_i8 GPRI8:$src), + (LOADCONST_i32 24)), + (LOADCONST_i32 24))) >; + + +def sctoi_i32:Pat < (i32 (sext GPRI8:$src)), +(IL_ASINT_i32 + (SHR_i32 + (SHL_i32 +(IL_ASINT_i8 GPRI8:$src), + (LOADCONST_i32 24)), + (LOADCONST_i32 24))) >; + + +def actol_i64:Pat < (i64 (anyext GPRI8:$src)), +(LCREATE + (USHR_i32 + (SHL_i32 +(IL_ASINT_i8 GPRI8:$src), + (LOADCONST_i32 24)), + (LOADCONST_i32 24)), + (LOADCONST_i32 0)) >; + + +def uctol_i64:Pat < (i64 (zext GPRI8:$src)), +(LCREATE + (USHR_i32 + (SHL_i32 +(IL_ASINT_i8 GPRI8:$src), + (LOADCONST_i32 24)), + (LOADCONST_i32 24)), + (LOADCONST_i32 0)) >; + + +def sctol_i64:Pat < (i64 (sext GPRI8:$src)), +(LCREATE + (SHR_i32 + (SHL_i32 +(IL_ASINT_i8 GPRI8:$src), + (LOADCONST_i32 24)), + (LOADCONST_i32 24)), + (SHR_i32 + (SHL_i32 +(IL_ASINT_i8 GPRI8:$src), + (LOADCONST_i32 24)), + (LOADCONST_i32 31))) >; + + +def astoi_i32:Pat < (i32 (anyext GPRI16:$src)), +(IL_ASINT_i32 + (USHR_i32 + (SHL_i32 +(IL_ASINT_i16 GPRI16:$src), + (LOADCONST_i32 16)), + (LOADCONST_i32 16))) >; + + +def ustoi_i32:Pat < (i32 (zext GPRI16:$src)), +(IL_ASINT_i32 + (USHR_i32 + (SHL_i32 +(IL_ASINT_i16 GPRI16:$src), + (LOADCONST_i32 16)), + (LOADCONST_i32 16))) >; + + +def sstoi_i32:Pat < (i32 (sext GPRI16:$src)), +(IL_ASINT_i32 + (SHR_i32 + (SHL_i32 +(IL_ASINT_i16 GPRI16:$src), + (LOADCONST_i32 16)), + (LOADCONST_i32 16))) >; + + +def astol_i64:Pat < (i64 (anyext GPRI16:$src)), +(LCREATE + (USHR_i32 + (SHL_i32 +(IL_ASINT_i16 GPRI16:$src), + (LOADCONST_i32 16)), + (LOADCONST_i32 16)), + (LOADCONST_i32 0)) >; + + +def ustol_i64:Pat < (i64 (zext GPRI16:$src)), +(LCREATE + (USHR_i32 + (SHL_i32 +(IL_ASINT_i16 GPRI16:$src), + (LOADCONST_i32 16)), + (LOADCONST_i32 16)), + (LOADCONST_i32 0)) >; + + +def sstol_i64:Pat < (i64 (sext GPRI16:$src)), +(LCREATE + (SHR_i32 + (SHL_i32 +(IL_ASINT_i16 GPRI16:$src), + (LOADCONST_i32 16)), + (LOADCONST_i32 16)), + (SHR_i32 + (SHL_i32 +(IL_ASINT_i16 GPRI16:$src), + (LOADCONST_i32 16)), + (LOADCONST_i32 31))) >; + + +def aitol_i64:Pat < (i64 (anyext GPRI32:$src)), +(LCREATE + (USHR_i32 + (SHL_i32 +(IL_ASINT_i32 GPRI32:$src), + (LOADCONST_i32 0)), + (LOADCONST_i32 0)), + (LOADCONST_i32 0)) >; + + +def uitol_i64:Pat < (i64 (zext GPRI32:$src)), +(LCREATE + (USHR_i32 + (SHL_i32 +(IL_ASINT_i32 GPRI32:$src), + (LOADCONST_i32 0)), + (LOADCONST_i32 0)), + (LOADCONST_i32 0)) >; + + +def sitol_i64:Pat < (i64 (sext GPRI32:$src)), +(LCREATE + (SHR_i32 + (SHL_i32 +(IL_ASINT_i32 GPRI32:$src), + (LOADCONST_i32 0)), + (LOADCONST_i32 0)), + (SHR_i32 + (SHL_i32 +(IL_ASINT_i32 GPRI32:$src), + (LOADCONST_i32 0)), + (LOADCONST_i32 31))) >; + + + +def sctof_f32:Pat < (f32 (sint_to_fp GPRI8:$src)), +(f32 + (ITOF + (SHR_i32 + (SHL_i32 +(IL_ASINT_i8 GPRI8:$src), + (LOADCONST_i32 24)), + (LOADCONST_i32 24)))) >; + + +def uctof_f32:Pat < (f32 (uint_to_fp GPRI8:$src)), +(f32 + (UTOF + (USHR_i32 + (SHL_i32 +(IL_ASINT_i8 GPRI8:$src), + (LOADCONST_i32 24)), + (LOADCONST_i32 24)))) >; + + +def ftosc_i8:Pat < (i8 (fp_to_sint GPRF32:$src)), +(i8 + (IL_ASCHAR_i32 + (BINARY_AND_i32 +(FTOI GPRF32:$src), + (LOADCONST_i32 0x000000FF)))) >; + + +def ftouc_i8:Pat < (i8 (fp_to_uint GPRF32:$src)), +(i8 + (IL_ASCHAR_i32 + (BINARY_AND_i32 +(FTOU GPRF32:$src), + (LOADCONST_i32 0x000000FF)))) >; + + +def sctod_f64:Pat < (f64 (sint_to_fp GPRI8:$src)), +(f64 (FTOD + (ITOF + (SHR_i32 + (SHL_i32 +(IL_ASINT_i8 GPRI8:$src), + (LOADCONST_i32 24)), + (LOADCONST_i32 24))))) >; + + +def uctod_f64:Pat < (f64 (uint_to_fp GPRI8:$src)), +(f64 (FTOD + (UTOF + (USHR_i32 + (SHL_i32 +(IL_ASINT_i8 GPRI8:$src), + (LOADCONST_i32 24)), + (LOADCONST_i32 24))))) >; + + +def dtosc_i8:Pat < (i8 (fp_to_sint GPRF64:$src)), +(i8 + (IL_ASCHAR_i32 + (BINARY_AND_i32 +(FTOI (DTOF GPRF64:$src)), + (LOADCONST_i32 0x000000FF)))) >; + + +def dtouc_i8:Pat < (i8 (fp_to_uint GPRF64:$src)), +(i8 + (IL_ASCHAR_i32 + (BINARY_AND_i32 +(FTOU (DTOF GPRF64:$src)), + (LOADCONST_i32 0x000000FF)))) >; + + +def sstof_f32:Pat < (f32 (sint_to_fp GPRI16:$src)), +(f32 + (ITOF + (SHR_i32 + (SHL_i32 +(IL_ASINT_i16 GPRI16:$src), + (LOADCONST_i32 16)), + (LOADCONST_i32 16)))) >; + + +def ustof_f32:Pat < (f32 (uint_to_fp GPRI16:$src)), +(f32 + (UTOF + (USHR_i32 + (SHL_i32 +(IL_ASINT_i16 GPRI16:$src), + (LOADCONST_i32 16)), + (LOADCONST_i32 16)))) >; + + +def ftoss_i16:Pat < (i16 (fp_to_sint GPRF32:$src)), +(i16 + (IL_ASSHORT_i32 + (BINARY_AND_i32 +(FTOI GPRF32:$src), + (LOADCONST_i32 0x0000FFFF)))) >; + + +def ftous_i16:Pat < (i16 (fp_to_uint GPRF32:$src)), +(i16 + (IL_ASSHORT_i32 + (BINARY_AND_i32 +(FTOU GPRF32:$src), + (LOADCONST_i32 0x0000FFFF)))) >; + + +def sstod_f64:Pat < (f64 (sint_to_fp GPRI16:$src)), +(f64 (FTOD + (ITOF + (SHR_i32 + (SHL_i32 +(IL_ASINT_i16 GPRI16:$src), + (LOADCONST_i32 16)), + (LOADCONST_i32 16))))) >; + + +def ustod_f64:Pat < (f64 (uint_to_fp GPRI16:$src)), +(f64 (FTOD + (UTOF + (USHR_i32 + (SHL_i32 +(IL_ASINT_i16 GPRI16:$src), + (LOADCONST_i32 16)), + (LOADCONST_i32 16))))) >; + + +def dtoss_i16:Pat < (i16 (fp_to_sint GPRF64:$src)), +(i16 + (IL_ASSHORT_i32 + (BINARY_AND_i32 +(FTOI (DTOF GPRF64:$src)), + (LOADCONST_i32 0x0000FFFF)))) >; + + +def dtous_i16:Pat < (i16 (fp_to_uint GPRF64:$src)), +(i16 + (IL_ASSHORT_i32 + (BINARY_AND_i32 +(FTOU (DTOF GPRF64:$src)), + (LOADCONST_i32 0x0000FFFF)))) >; + + + + + +def stoc_i8:Pat < (i8 (trunc GPRI16:$src)), +(IL_ASCHAR_i32 + (IL_ASINT_i16 +(BINARY_AND_i16 GPRI16:$src, + (LOADCONST_i16 0x000000FF))) + ) >; + + +def itoc_i8:Pat < (i8 (trunc GPRI32:$src)), +(IL_ASCHAR_i32 + (IL_ASINT_i32 +(BINARY_AND_i32 GPRI32:$src, + (LOADCONST_i32 0x000000FF))) + ) >; + + +def itos_i16:Pat < (i16 (trunc GPRI32:$src)), +(IL_ASSHORT_i32 + (IL_ASINT_i32 +(BINARY_AND_i32 GPRI32:$src, + (LOADCONST_i32 0x0000FFFF))) + ) >; + + +def ltoc_i8:Pat < (i8 (trunc GPRI64:$src)), +(IL_ASCHAR_i32 + (BINARY_AND_i32 +(LLO GPRI64:$src), + (LOADCONST_i32 0x000000FF)) + ) >; + + +def ltos_i16:Pat < (i16 (trunc GPRI64:$src)), +(IL_ASSHORT_i32 + (BINARY_AND_i32 +(LLO GPRI64:$src), + (LOADCONST_i32 0x0000FFFF)) + ) >; + + +def ltoi_i32:Pat < (i32 (trunc GPRI64:$src)), +(IL_ASINT_i32 + (BINARY_AND_i32 +(LLO GPRI64:$src), + (LOADCONST_i32 0xFFFFFFFF)) + ) >; + + +def actos_v2i16:Pat < (v2i16 (anyext GPRV2I8:$src)), +(IL_ASV2SHORT_v2i32 + (USHRVEC_v2i32 + (SHLVEC_v2i32 +(IL_ASV2INT_v2i8 GPRV2I8:$src), + (VCREATE_v2i32 (LOADCONST_i32 24))), + (VCREATE_v2i32 (LOADCONST_i32 24)))) >; + + +def uctos_v2i16:Pat < (v2i16 (zext GPRV2I8:$src)), +(IL_ASV2SHORT_v2i32 + (USHRVEC_v2i32 + (SHLVEC_v2i32 +(IL_ASV2INT_v2i8 GPRV2I8:$src), + (VCREATE_v2i32 (LOADCONST_i32 24))), + (VCREATE_v2i32 (LOADCONST_i32 24)))) >; + + +def sctos_v2i16:Pat < (v2i16 (sext GPRV2I8:$src)), +(IL_ASV2SHORT_v2i32 + (SHRVEC_v2i32 + (SHLVEC_v2i32 +(IL_ASV2INT_v2i8 GPRV2I8:$src), + (VCREATE_v2i32 (LOADCONST_i32 24))), + (VCREATE_v2i32 (LOADCONST_i32 24)))) >; + + +def actoi_v2i32:Pat < (v2i32 (anyext GPRV2I8:$src)), +(IL_ASV2INT_v2i32 + (USHRVEC_v2i32 + (SHLVEC_v2i32 +(IL_ASV2INT_v2i8 GPRV2I8:$src), + (VCREATE_v2i32 (LOADCONST_i32 24))), + (VCREATE_v2i32 (LOADCONST_i32 24)))) >; + + +def uctoi_v2i32:Pat < (v2i32 (zext GPRV2I8:$src)), +(IL_ASV2INT_v2i32 + (USHRVEC_v2i32 + (SHLVEC_v2i32 +(IL_ASV2INT_v2i8 GPRV2I8:$src), + (VCREATE_v2i32 (LOADCONST_i32 24))), + (VCREATE_v2i32 (LOADCONST_i32 24)))) >; + + +def sctoi_v2i32:Pat < (v2i32 (sext GPRV2I8:$src)), +(IL_ASV2INT_v2i32 + (SHRVEC_v2i32 + (SHLVEC_v2i32 +(IL_ASV2INT_v2i8 GPRV2I8:$src), + (VCREATE_v2i32 (LOADCONST_i32 24))), + (VCREATE_v2i32 (LOADCONST_i32 24)))) >; + + +def actol_v2i64:Pat < (v2i64 (anyext GPRV2I8:$src)), +(LCREATE_v2i64 + (USHRVEC_v2i32 + (SHLVEC_v2i32 +(IL_ASV2INT_v2i8 GPRV2I8:$src), + (VCREATE_v2i32 (LOADCONST_i32 24))), + (VCREATE_v2i32 (LOADCONST_i32 24))), + (VCREATE_v2i32 (LOADCONST_i32 0))) >; + + +def uctol_v2i64:Pat < (v2i64 (zext GPRV2I8:$src)), +(LCREATE_v2i64 + (USHRVEC_v2i32 + (SHLVEC_v2i32 +(IL_ASV2INT_v2i8 GPRV2I8:$src), + (VCREATE_v2i32 (LOADCONST_i32 24))), + (VCREATE_v2i32 (LOADCONST_i32 24))), + (VCREATE_v2i32 (LOADCONST_i32 0))) >; + + +def sctol_v2i64:Pat < (v2i64 (sext GPRV2I8:$src)), +(LCREATE_v2i64 + (SHRVEC_v2i32 + (SHLVEC_v2i32 +(IL_ASV2INT_v2i8 GPRV2I8:$src), + (VCREATE_v2i32 (LOADCONST_i32 24))), + (VCREATE_v2i32 (LOADCONST_i32 24))), + (SHRVEC_v2i32 + (SHLVEC_v2i32 +(IL_ASV2INT_v2i8 GPRV2I8:$src), + (VCREATE_v2i32 (LOADCONST_i32 24))), + (VCREATE_v2i32 (LOADCONST_i32 31)))) >; + + +def astoi_v2i32:Pat < (v2i32 (anyext GPRV2I16:$src)), +(IL_ASV2INT_v2i32 + (USHRVEC_v2i32 + (SHLVEC_v2i32 +(IL_ASV2INT_v2i16 GPRV2I16:$src), + (VCREATE_v2i32 (LOADCONST_i32 16))), + (VCREATE_v2i32 (LOADCONST_i32 16)))) >; + + +def ustoi_v2i32:Pat < (v2i32 (zext GPRV2I16:$src)), +(IL_ASV2INT_v2i32 + (USHRVEC_v2i32 + (SHLVEC_v2i32 +(IL_ASV2INT_v2i16 GPRV2I16:$src), + (VCREATE_v2i32 (LOADCONST_i32 16))), + (VCREATE_v2i32 (LOADCONST_i32 16)))) >; + + +def sstoi_v2i32:Pat < (v2i32 (sext GPRV2I16:$src)), +(IL_ASV2INT_v2i32 + (SHRVEC_v2i32 + (SHLVEC_v2i32 +(IL_ASV2INT_v2i16 GPRV2I16:$src), + (VCREATE_v2i32 (LOADCONST_i32 16))), + (VCREATE_v2i32 (LOADCONST_i32 16)))) >; + + +def astol_v2i64:Pat < (v2i64 (anyext GPRV2I16:$src)), +(LCREATE_v2i64 + (USHRVEC_v2i32 + (SHLVEC_v2i32 +(IL_ASV2INT_v2i16 GPRV2I16:$src), + (VCREATE_v2i32 (LOADCONST_i32 16))), + (VCREATE_v2i32 (LOADCONST_i32 16))), + (VCREATE_v2i32 (LOADCONST_i32 0))) >; + + +def ustol_v2i64:Pat < (v2i64 (zext GPRV2I16:$src)), +(LCREATE_v2i64 + (USHRVEC_v2i32 + (SHLVEC_v2i32 +(IL_ASV2INT_v2i16 GPRV2I16:$src), + (VCREATE_v2i32 (LOADCONST_i32 16))), + (VCREATE_v2i32 (LOADCONST_i32 16))), + (VCREATE_v2i32 (LOADCONST_i32 0))) >; + + +def sstol_v2i64:Pat < (v2i64 (sext GPRV2I16:$src)), +(LCREATE_v2i64 + (SHRVEC_v2i32 + (SHLVEC_v2i32 +(IL_ASV2INT_v2i16 GPRV2I16:$src), + (VCREATE_v2i32 (LOADCONST_i32 16))), + (VCREATE_v2i32 (LOADCONST_i32 16))), + (SHRVEC_v2i32 + (SHLVEC_v2i32 +(IL_ASV2INT_v2i16 GPRV2I16:$src), + (VCREATE_v2i32 (LOADCONST_i32 16))), + (VCREATE_v2i32 (LOADCONST_i32 31)))) >; + + +def aitol_v2i64:Pat < (v2i64 (anyext GPRV2I32:$src)), +(LCREATE_v2i64 + (USHRVEC_v2i32 + (SHLVEC_v2i32 +(IL_ASV2INT_v2i32 GPRV2I32:$src), + (VCREATE_v2i32 (LOADCONST_i32 0))), + (VCREATE_v2i32 (LOADCONST_i32 0))), + (VCREATE_v2i32 (LOADCONST_i32 0))) >; + + +def uitol_v2i64:Pat < (v2i64 (zext GPRV2I32:$src)), +(LCREATE_v2i64 + (USHRVEC_v2i32 + (SHLVEC_v2i32 +(IL_ASV2INT_v2i32 GPRV2I32:$src), + (VCREATE_v2i32 (LOADCONST_i32 0))), + (VCREATE_v2i32 (LOADCONST_i32 0))), + (VCREATE_v2i32 (LOADCONST_i32 0))) >; + + +def sitol_v2i64:Pat < (v2i64 (sext GPRV2I32:$src)), +(LCREATE_v2i64 + (SHRVEC_v2i32 + (SHLVEC_v2i32 +(IL_ASV2INT_v2i32 GPRV2I32:$src), + (VCREATE_v2i32 (LOADCONST_i32 0))), + (VCREATE_v2i32 (LOADCONST_i32 0))), + (SHRVEC_v2i32 + (SHLVEC_v2i32 +(IL_ASV2INT_v2i32 GPRV2I32:$src), + (VCREATE_v2i32 (LOADCONST_i32 0))), + (VCREATE_v2i32 (LOADCONST_i32 31)))) >; + + + +def sctof_v2f32:Pat < (v2f32 (sint_to_fp GPRV2I8:$src)), +(v2f32 + (ITOF_v2f32 + (SHRVEC_v2i32 + (SHLVEC_v2i32 +(IL_ASV2INT_v2i8 GPRV2I8:$src), + (VCREATE_v2i32 (LOADCONST_i32 24))), + (VCREATE_v2i32 (LOADCONST_i32 24))))) >; + + +def uctof_v2f32:Pat < (v2f32 (uint_to_fp GPRV2I8:$src)), +(v2f32 + (UTOF_v2f32 + (USHRVEC_v2i32 + (SHLVEC_v2i32 +(IL_ASV2INT_v2i8 GPRV2I8:$src), + (VCREATE_v2i32 (LOADCONST_i32 24))), + (VCREATE_v2i32 (LOADCONST_i32 24))))) >; + + +def ftosc_v2i8:Pat < (v2i8 (fp_to_sint GPRV2F32:$src)), +(v2i8 + (IL_ASV2CHAR_v2i32 + (BINARY_AND_v2i32 +(FTOI_v2i32 GPRV2F32:$src), + (VCREATE_v2i32 (LOADCONST_i32 0x000000FF))))) >; + + +def ftouc_v2i8:Pat < (v2i8 (fp_to_uint GPRV2F32:$src)), +(v2i8 + (IL_ASV2CHAR_v2i32 + (BINARY_AND_v2i32 +(FTOU_v2i32 GPRV2F32:$src), + (VCREATE_v2i32 (LOADCONST_i32 0x000000FF))))) >; + +def sctod_v2f64:Pat < (v2f64 (sint_to_fp GPRV2I8:$src)), +(v2f64 + (VINSERT_v2f64 + (VCREATE_v2f64 + (FTOD + (VEXTRACT_v2f32 + (ITOF_v2f32 + (SHRVEC_v2i32 + (SHLVEC_v2i32 +(IL_ASV2INT_v2i8 GPRV2I8:$src), + (VCREATE_v2i32 (LOADCONST_i32 24))), + (VCREATE_v2i32 (LOADCONST_i32 24)))), + 1) + )), + (FTOD + (VEXTRACT_v2f32 + (ITOF_v2f32 + (SHRVEC_v2i32 + (SHLVEC_v2i32 +(IL_ASV2INT_v2i8 GPRV2I8:$src), + (VCREATE_v2i32 (LOADCONST_i32 24))), + (VCREATE_v2i32 (LOADCONST_i32 24)))), + 2) + ), 1, 256) + ) >; + +def uctod_v2f64:Pat < (v2f64 (uint_to_fp GPRV2I8:$src)), +(v2f64 + (VINSERT_v2f64 + (VCREATE_v2f64 + (FTOD + (VEXTRACT_v2f32 + (UTOF_v2f32 + (USHRVEC_v2i32 + (SHLVEC_v2i32 +(IL_ASV2INT_v2i8 GPRV2I8:$src), + (VCREATE_v2i32 (LOADCONST_i32 24))), + (VCREATE_v2i32 (LOADCONST_i32 24)))), + 1) + )), + (FTOD + (VEXTRACT_v2f32 + (UTOF_v2f32 + (USHRVEC_v2i32 + (SHLVEC_v2i32 +(IL_ASV2INT_v2i8 GPRV2I8:$src), + (VCREATE_v2i32 (LOADCONST_i32 24))), + (VCREATE_v2i32 (LOADCONST_i32 24)))), + 2) + ), 1, 256) + ) >; + + +def dtosc_v2i8:Pat < (v2i8 (fp_to_sint GPRV2F64:$src)), +(v2i8 + (IL_ASV2CHAR_v2i32 + (BINARY_AND_v2i32 +(FTOI_v2i32 (VINSERT_v2f32 + (VCREATE_v2f32 + (DTOF (VEXTRACT_v2f64 GPRV2F64:$src, 1))), + (DTOF (VEXTRACT_v2f64 GPRV2F64:$src, 2)), 1, 256)), + (VCREATE_v2i32 (LOADCONST_i32 0x000000FF))))) >; + + +def dtouc_v2i8:Pat < (v2i8 (fp_to_uint GPRV2F64:$src)), +(v2i8 + (IL_ASV2CHAR_v2i32 + (BINARY_AND_v2i32 +(FTOU_v2i32 (VINSERT_v2f32 + (VCREATE_v2f32 + (DTOF (VEXTRACT_v2f64 GPRV2F64:$src, 1))), + (DTOF (VEXTRACT_v2f64 GPRV2F64:$src, 2)), 1, 256)), + (VCREATE_v2i32 (LOADCONST_i32 0x000000FF))))) >; + + +def sstof_v2f32:Pat < (v2f32 (sint_to_fp GPRV2I16:$src)), +(v2f32 + (ITOF_v2f32 + (SHRVEC_v2i32 + (SHLVEC_v2i32 +(IL_ASV2INT_v2i16 GPRV2I16:$src), + (VCREATE_v2i32 (LOADCONST_i32 16))), + (VCREATE_v2i32 (LOADCONST_i32 16))))) >; + + +def ustof_v2f32:Pat < (v2f32 (uint_to_fp GPRV2I16:$src)), +(v2f32 + (UTOF_v2f32 + (USHRVEC_v2i32 + (SHLVEC_v2i32 +(IL_ASV2INT_v2i16 GPRV2I16:$src), + (VCREATE_v2i32 (LOADCONST_i32 16))), + (VCREATE_v2i32 (LOADCONST_i32 16))))) >; + + +def ftoss_v2i16:Pat < (v2i16 (fp_to_sint GPRV2F32:$src)), +(v2i16 + (IL_ASV2SHORT_v2i32 + (BINARY_AND_v2i32 +(FTOI_v2i32 GPRV2F32:$src), + (VCREATE_v2i32 (LOADCONST_i32 0x0000FFFF))))) >; + + +def ftous_v2i16:Pat < (v2i16 (fp_to_uint GPRV2F32:$src)), +(v2i16 + (IL_ASV2SHORT_v2i32 + (BINARY_AND_v2i32 +(FTOU_v2i32 GPRV2F32:$src), + (VCREATE_v2i32 (LOADCONST_i32 0x0000FFFF))))) >; + + +def sstod_v2f64:Pat < (v2f64 (sint_to_fp GPRV2I16:$src)), +(v2f64 + (VINSERT_v2f64 + (VCREATE_v2f64 + (FTOD + (VEXTRACT_v2f32 + (ITOF_v2f32 + (SHRVEC_v2i32 + (SHLVEC_v2i32 +(IL_ASV2INT_v2i16 GPRV2I16:$src), + (VCREATE_v2i32 (LOADCONST_i32 16))), + (VCREATE_v2i32 (LOADCONST_i32 16)))), + 1) + )), + (FTOD + (VEXTRACT_v2f32 + (ITOF_v2f32 + (SHRVEC_v2i32 + (SHLVEC_v2i32 +(IL_ASV2INT_v2i16 GPRV2I16:$src), + (VCREATE_v2i32 (LOADCONST_i32 16))), + (VCREATE_v2i32 (LOADCONST_i32 16)))), + 2) + ), 1, 256) + ) >; + +def ustod_v2f64:Pat < (v2f64 (uint_to_fp GPRV2I16:$src)), +(v2f64 + (VINSERT_v2f64 + (VCREATE_v2f64 + (FTOD + (VEXTRACT_v2f32 + (UTOF_v2f32 + (USHRVEC_v2i32 + (SHLVEC_v2i32 +(IL_ASV2INT_v2i16 GPRV2I16:$src), + (VCREATE_v2i32 (LOADCONST_i32 16))), + (VCREATE_v2i32 (LOADCONST_i32 16)))), + 1) + )), + (FTOD + (VEXTRACT_v2f32 + (UTOF_v2f32 + (USHRVEC_v2i32 + (SHLVEC_v2i32 +(IL_ASV2INT_v2i16 GPRV2I16:$src), + (VCREATE_v2i32 (LOADCONST_i32 16))), + (VCREATE_v2i32 (LOADCONST_i32 16)))), + 2) + ), 1, 256) + ) >; + + +def dtoss_v2i16:Pat < (v2i16 (fp_to_sint GPRV2F64:$src)), +(v2i16 + (IL_ASV2SHORT_v2i32 + (BINARY_AND_v2i32 +(FTOI_v2i32 (VINSERT_v2f32 + (VCREATE_v2f32 + (DTOF (VEXTRACT_v2f64 GPRV2F64:$src, 1))), + (DTOF (VEXTRACT_v2f64 GPRV2F64:$src, 2)), 1, 256)), + (VCREATE_v2i32 (LOADCONST_i32 0x0000FFFF))))) >; + + +def dtous_v2i16:Pat < (v2i16 (fp_to_uint GPRV2F64:$src)), +(v2i16 + (IL_ASV2SHORT_v2i32 + (BINARY_AND_v2i32 +(FTOU_v2i32 (VINSERT_v2f32 + (VCREATE_v2f32 + (DTOF (VEXTRACT_v2f64 GPRV2F64:$src, 1))), + (DTOF (VEXTRACT_v2f64 GPRV2F64:$src, 2)), 1, 256)), + (VCREATE_v2i32 (LOADCONST_i32 0x0000FFFF))))) >; + +def stoc_v2i8:Pat < (v2i8 (trunc GPRV2I16:$src)), +(IL_ASV2CHAR_v2i32 + (IL_ASV2INT_v2i16 +(BINARY_AND_v2i16 GPRV2I16:$src, + (VCREATE_v2i16 (LOADCONST_i16 0x000000FF)))) + ) >; + + +def itoc_v2i8:Pat < (v2i8 (trunc GPRV2I32:$src)), +(IL_ASV2CHAR_v2i32 + (IL_ASV2INT_v2i32 +(BINARY_AND_v2i32 GPRV2I32:$src, + (VCREATE_v2i32 (LOADCONST_i32 0x000000FF)))) + ) >; + + +def itos_v2i16:Pat < (v2i16 (trunc GPRV2I32:$src)), +(IL_ASV2SHORT_v2i32 + (IL_ASV2INT_v2i32 +(BINARY_AND_v2i32 GPRV2I32:$src, + (VCREATE_v2i32 (LOADCONST_i32 0x0000FFFF)))) + ) >; + + +def ltoc_v2i8:Pat < (v2i8 (trunc GPRV2I64:$src)), +(IL_ASV2CHAR_v2i32 + (BINARY_AND_v2i32 +(LLO_v2i64 GPRV2I64:$src), + (VCREATE_v2i32 (LOADCONST_i32 0x000000FF))) + ) >; + + +def ltos_v2i16:Pat < (v2i16 (trunc GPRV2I64:$src)), +(IL_ASV2SHORT_v2i32 + (BINARY_AND_v2i32 +(LLO_v2i64 GPRV2I64:$src), + (VCREATE_v2i32 (LOADCONST_i32 0x0000FFFF))) + ) >; + + +def ltoi_v2i32:Pat < (v2i32 (trunc GPRV2I64:$src)), +(IL_ASV2INT_v2i32 + (BINARY_AND_v2i32 +(LLO_v2i64 GPRV2I64:$src), + (VCREATE_v2i32 (LOADCONST_i32 0xFFFFFFFF))) + ) >; + + + + +def actos_v4i16:Pat < (v4i16 (anyext GPRV4I8:$src)), +(IL_ASV4SHORT_v4i32 + (USHRVEC_v4i32 + (SHLVEC_v4i32 +(IL_ASV4INT_v4i8 GPRV4I8:$src), + (VCREATE_v4i32 (LOADCONST_i32 24))), + (VCREATE_v4i32 (LOADCONST_i32 24)))) >; + + +def uctos_v4i16:Pat < (v4i16 (zext GPRV4I8:$src)), +(IL_ASV4SHORT_v4i32 + (USHRVEC_v4i32 + (SHLVEC_v4i32 +(IL_ASV4INT_v4i8 GPRV4I8:$src), + (VCREATE_v4i32 (LOADCONST_i32 24))), + (VCREATE_v4i32 (LOADCONST_i32 24)))) >; + + +def sctos_v4i16:Pat < (v4i16 (sext GPRV4I8:$src)), +(IL_ASV4SHORT_v4i32 + (SHRVEC_v4i32 + (SHLVEC_v4i32 +(IL_ASV4INT_v4i8 GPRV4I8:$src), + (VCREATE_v4i32 (LOADCONST_i32 24))), + (VCREATE_v4i32 (LOADCONST_i32 24)))) >; + + +def actoi_v4i32:Pat < (v4i32 (anyext GPRV4I8:$src)), +(IL_ASV4INT_v4i32 + (USHRVEC_v4i32 + (SHLVEC_v4i32 +(IL_ASV4INT_v4i8 GPRV4I8:$src), + (VCREATE_v4i32 (LOADCONST_i32 24))), + (VCREATE_v4i32 (LOADCONST_i32 24)))) >; + + +def uctoi_v4i32:Pat < (v4i32 (zext GPRV4I8:$src)), +(IL_ASV4INT_v4i32 + (USHRVEC_v4i32 + (SHLVEC_v4i32 +(IL_ASV4INT_v4i8 GPRV4I8:$src), + (VCREATE_v4i32 (LOADCONST_i32 24))), + (VCREATE_v4i32 (LOADCONST_i32 24)))) >; + + +def sctoi_v4i32:Pat < (v4i32 (sext GPRV4I8:$src)), +(IL_ASV4INT_v4i32 + (SHRVEC_v4i32 + (SHLVEC_v4i32 +(IL_ASV4INT_v4i8 GPRV4I8:$src), + (VCREATE_v4i32 (LOADCONST_i32 24))), + (VCREATE_v4i32 (LOADCONST_i32 24)))) >; + + +def astoi_v4i32:Pat < (v4i32 (anyext GPRV4I16:$src)), +(IL_ASV4INT_v4i32 + (USHRVEC_v4i32 + (SHLVEC_v4i32 +(IL_ASV4INT_v4i16 GPRV4I16:$src), + (VCREATE_v4i32 (LOADCONST_i32 16))), + (VCREATE_v4i32 (LOADCONST_i32 16)))) >; + + +def ustoi_v4i32:Pat < (v4i32 (zext GPRV4I16:$src)), +(IL_ASV4INT_v4i32 + (USHRVEC_v4i32 + (SHLVEC_v4i32 +(IL_ASV4INT_v4i16 GPRV4I16:$src), + (VCREATE_v4i32 (LOADCONST_i32 16))), + (VCREATE_v4i32 (LOADCONST_i32 16)))) >; + + +def sstoi_v4i32:Pat < (v4i32 (sext GPRV4I16:$src)), +(IL_ASV4INT_v4i32 + (SHRVEC_v4i32 + (SHLVEC_v4i32 +(IL_ASV4INT_v4i16 GPRV4I16:$src), + (VCREATE_v4i32 (LOADCONST_i32 16))), + (VCREATE_v4i32 (LOADCONST_i32 16)))) >; + + + +def sctof_v4f32:Pat < (v4f32 (sint_to_fp GPRV4I8:$src)), +(v4f32 + (ITOF_v4f32 + (SHRVEC_v4i32 + (SHLVEC_v4i32 +(IL_ASV4INT_v4i8 GPRV4I8:$src), + (VCREATE_v4i32 (LOADCONST_i32 24))), + (VCREATE_v4i32 (LOADCONST_i32 24))))) >; + + +def uctof_v4f32:Pat < (v4f32 (uint_to_fp GPRV4I8:$src)), +(v4f32 + (UTOF_v4f32 + (USHRVEC_v4i32 + (SHLVEC_v4i32 +(IL_ASV4INT_v4i8 GPRV4I8:$src), + (VCREATE_v4i32 (LOADCONST_i32 24))), + (VCREATE_v4i32 (LOADCONST_i32 24))))) >; + + +def ftosc_v4i8:Pat < (v4i8 (fp_to_sint GPRV4F32:$src)), +(v4i8 + (IL_ASV4CHAR_v4i32 + (BINARY_AND_v4i32 +(FTOI_v4i32 GPRV4F32:$src), + (VCREATE_v4i32 (LOADCONST_i32 0x000000FF))))) >; + + +def ftouc_v4i8:Pat < (v4i8 (fp_to_uint GPRV4F32:$src)), +(v4i8 + (IL_ASV4CHAR_v4i32 + (BINARY_AND_v4i32 +(FTOU_v4i32 GPRV4F32:$src), + (VCREATE_v4i32 (LOADCONST_i32 0x000000FF))))) >; + + +def sstof_v4f32:Pat < (v4f32 (sint_to_fp GPRV4I16:$src)), +(v4f32 + (ITOF_v4f32 + (SHRVEC_v4i32 + (SHLVEC_v4i32 +(IL_ASV4INT_v4i16 GPRV4I16:$src), + (VCREATE_v4i32 (LOADCONST_i32 16))), + (VCREATE_v4i32 (LOADCONST_i32 16))))) >; + + +def ustof_v4f32:Pat < (v4f32 (uint_to_fp GPRV4I16:$src)), +(v4f32 + (UTOF_v4f32 + (USHRVEC_v4i32 + (SHLVEC_v4i32 +(IL_ASV4INT_v4i16 GPRV4I16:$src), + (VCREATE_v4i32 (LOADCONST_i32 16))), + (VCREATE_v4i32 (LOADCONST_i32 16))))) >; + + +def ftoss_v4i16:Pat < (v4i16 (fp_to_sint GPRV4F32:$src)), +(v4i16 + (IL_ASV4SHORT_v4i32 + (BINARY_AND_v4i32 +(FTOI_v4i32 GPRV4F32:$src), + (VCREATE_v4i32 (LOADCONST_i32 0x0000FFFF))))) >; + + +def ftous_v4i16:Pat < (v4i16 (fp_to_uint GPRV4F32:$src)), +(v4i16 + (IL_ASV4SHORT_v4i32 + (BINARY_AND_v4i32 +(FTOU_v4i32 GPRV4F32:$src), + (VCREATE_v4i32 (LOADCONST_i32 0x0000FFFF))))) >; + + + + + +def stoc_v4i8:Pat < (v4i8 (trunc GPRV4I16:$src)), +(IL_ASV4CHAR_v4i32 + (IL_ASV4INT_v4i16 +(BINARY_AND_v4i16 GPRV4I16:$src, + (VCREATE_v4i16 (LOADCONST_i16 0x000000FF)))) + ) >; + + +def itoc_v4i8:Pat < (v4i8 (trunc GPRV4I32:$src)), +(IL_ASV4CHAR_v4i32 + (IL_ASV4INT_v4i32 +(BINARY_AND_v4i32 GPRV4I32:$src, + (VCREATE_v4i32 (LOADCONST_i32 0x000000FF)))) + ) >; + + +def itos_v4i16:Pat < (v4i16 (trunc GPRV4I32:$src)), +(IL_ASV4SHORT_v4i32 + (IL_ASV4INT_v4i32 +(BINARY_AND_v4i32 GPRV4I32:$src, + (VCREATE_v4i32 (LOADCONST_i32 0x0000FFFF)))) + ) >; + + diff --git a/lib/Target/AMDIL/AMDILEnumeratedTypes.td b/lib/Target/AMDIL/AMDILEnumeratedTypes.td new file mode 100644 index 00000000000..f10936b8c6c --- /dev/null +++ b/lib/Target/AMDIL/AMDILEnumeratedTypes.td @@ -0,0 +1,522 @@ +//===-- AMDILEnumeratedTypes.td - IL Type definitions --*- tablegen -*-----===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//==-----------------------------------------------------------------------===// +// ILEnumreatedTypes.td - The IL Enumerated Types +//===--------------------------------------------------------------------===// + +// Section 5.1 IL Shader +class ILShader val> { + bits<8> Value = val; +} +// Table 5-1 +def IL_SHADER_PIXEL : ILShader<0>; +def IL_SHADER_COMPUTE : ILShader<1>; + +// Section 5.2 IL RegType +class ILRegType val> { + bits<6> Value = val; +} +// Table 5-2 +def IL_REGTYPE_TEMP : ILRegType<0>; +def IL_REGTYPE_WINCOORD : ILRegType<1>; +def IL_REGTYPE_CONST_BUF : ILRegType<2>; +def IL_REGTYPE_LITERAL : ILRegType<3>; +def IL_REGTYPE_ITEMP : ILRegType<4>; +def IL_REGTYPE_GLOBAL : ILRegType<5>; + +// Section 5.3 IL Component Select +class ILComponentSelect val, string text> { + bits<3> Value = val; + string Text = text; +} +// Table 5-3 +def IL_COMPSEL_X : ILComponentSelect<0, "x">; +def IL_COMPSEL_Y : ILComponentSelect<1, "y">; +def IL_COMPSEL_Z : ILComponentSelect<2, "z">; +def IL_COMPSEL_W : ILComponentSelect<3, "w">; +def IL_COMPSEL_0 : ILComponentSelect<4, "0">; +def IL_COMPSEL_1 : ILComponentSelect<5, "1">; + +// Section 5.4 IL Mod Dst Comp +class ILModDstComp val, string text> { + bits<2> Value = val; + string Text = text; +} +// Table 5-4 +def IL_MODCOMP_NOWRITE : ILModDstComp<0, "_">; +def IL_MODCOMP_WRITE_X : ILModDstComp<1, "x">; +def IL_MODCOMP_WRITE_y : ILModDstComp<1, "y">; +def IL_MODCOMP_WRITE_z : ILModDstComp<1, "z">; +def IL_MODCOMP_WRITE_w : ILModDstComp<1, "w">; +def IL_MODCOMP_0 : ILModDstComp<2, "0">; +def IL_MODCOMP_1 : ILModDstComp<3, "1">; + +// Section 5.5 IL Import Usage +class ILImportUsage val, string usage> { + bits<1> Value = val; + string Text = usage; +} +// Table 5-5 +def IL_IMPORTUSAGE_WINCOORD : ILImportUsage<0, "_usage(wincoord)">; + +// Section 5.6 Il Shift Scale +class ILShiftScale val, string scale> { + bits<4> Value = val; + string Text = scale; +} + +// Table 5-6 +def IL_SHIFT_NONE : ILShiftScale<0, "">; +def IL_SHIFT_X2 : ILShiftScale<1, "_x2">; +def IL_SHIFT_X4 : ILShiftScale<2, "_x4">; +def IL_SHIFT_X8 : ILShiftScale<3, "_x8">; +def IL_SHIFT_D2 : ILShiftScale<4, "_d2">; +def IL_SHIFT_D4 : ILShiftScale<5, "_d4">; +def IL_SHIFT_D8 : ILShiftScale<6, "_d8">; + +// Section 5.7 IL Divide Component +class ILDivComp val, string divcomp> { + bits<3> Value = val; + string Text = divcomp; +} + +// Table 5-7 +def IL_DIVCOMP_NONE : ILDivComp<0, "_divcomp(none)">; +def IL_DIVCOMP_Y : ILDivComp<1, "_divcomp(y)">; +def IL_DIVCOMP_Z : ILDivComp<2, "_divcomp(z)">; +def IL_DIVCOMP_W : ILDivComp<3, "_divcomp(w)">; +//def IL_DIVCOMP_UNKNOWN : ILDivComp<4, "_divcomp(unknown)">; + +// Section 5.8 IL Relational Op +class ILRelOp val, string op> { + bits<3> Value = val; + string Text = op; +} + +// Table 5-8 +def IL_RELOP_EQ : ILRelOp<0, "_relop(eq)">; +def IL_RELOP_NE : ILRelOp<1, "_relop(ne)">; +def IL_RELOP_GT : ILRelOp<2, "_relop(gt)">; +def IL_RELOP_GE : ILRelOp<3, "_relop(ge)">; +def IL_RELOP_LT : ILRelOp<4, "_relop(lt)">; +def IL_RELOP_LE : ILRelOp<5, "_relop(le)">; + +// Section 5.9 IL Zero Op +class ILZeroOp val, string behavior> { + bits<3> Value = val; + string Text = behavior; +} + +// Table 5-9 +def IL_ZEROOP_FLTMAX : ILZeroOp<0, "_zeroop(fltmax)">; +def IL_ZEROOP_0 : ILZeroOp<1, "_zeroop(zero)">; +def IL_ZEROOP_INFINITY : ILZeroOp<2, "_zeroop(infinity)">; +def IL_ZEROOP_INF_ELSE_MAX : ILZeroOp<3, "_zeroop(inf_else_max)">; + +// Section 5.10 IL Cmp Value +class ILCmpValue val, string num> { + bits<3> Value = val; + string Text = num; +} + +// Table 5-10 +def IL_CMPVAL_0_0 : ILCmpValue<0, "0.0">; +def IL_CMPVAL_0_5 : ILCmpValue<1, "0.5">; +def IL_CMPVAL_1_0 : ILCmpValue<2, "1.0">; +def IL_CMPVAL_NEG_0_5 : ILCmpValue<3, "-0.5">; +def IL_CMPVAL_NEG_1_0 : ILCmpValue<4, "-1.0">; + +// Section 5.11 IL Addressing +class ILAddressing val> { + bits<3> Value = val; +} + +// Table 5-11 +def IL_ADDR_ABSOLUTE : ILAddressing<0>; +def IL_ADDR_RELATIVE : ILAddressing<1>; +def IL_ADDR_REG_RELATIVE : ILAddressing<2>; + +// Section 5.11 IL Element Format +class ILElementFormat val> { + bits<5> Value = val; +} + +// Table 5-11 +def IL_ELEMENTFORMAT_UNKNOWN : ILElementFormat<0>; +def IL_ELEMENTFORMAT_SNORM : ILElementFormat<1>; +def IL_ELEMENTFORMAT_UNORM : ILElementFormat<2>; +def IL_ELEMENTFORMAT_SINT : ILElementFormat<3>; +def IL_ELEMENTFORMAT_UINT : ILElementFormat<4>; +def IL_ELEMENTFORMAT_FLOAT : ILElementFormat<5>; +def IL_ELEMENTFORMAT_SRGB : ILElementFormat<6>; +def IL_ELEMENTFORMAT_MIXED : ILElementFormat<7>; +def IL_ELEMENTFORMAT_Last : ILElementFormat<8>; + +// Section 5.12 IL Op Code +class ILOpCode val = -1, string cmd> { + bits<16> Value = val; + string Text = cmd; +} + +// Table 5-12 +def IL_DCL_CONST_BUFFER : ILOpCode<0, "dcl_cb">; +def IL_DCL_INDEXED_TEMP_ARRAY : ILOpCode<1, "dcl_index_temp_array">; +def IL_DCL_INPUT : ILOpCode<2, "dcl_input">; +def IL_DCL_LITERAL : ILOpCode<3, "dcl_literal">; +def IL_DCL_OUTPUT : ILOpCode<4, "dcl_output">; +def IL_DCL_RESOURCE : ILOpCode<5, "dcl_resource">; +def IL_OP_ABS : ILOpCode<6, "abs">; +def IL_OP_ADD : ILOpCode<7, "add">; +def IL_OP_AND : ILOpCode<8, "iand">; +def IL_OP_BREAK : ILOpCode<9, "break">; +def IL_OP_BREAK_LOGICALNZ : ILOpCode<10, "break_logicalnz">; +def IL_OP_BREAK_LOGICALZ : ILOpCode<11, "break_logicalz">; +def IL_OP_BREAKC : ILOpCode<12, "breakc">; +def IL_OP_CALL : ILOpCode<13, "call">; +def IL_OP_CALL_LOGICALNZ : ILOpCode<14, "call_logicalnz">; +def IL_OP_CALL_LOGICALZ : ILOpCode<15, "call_logicalz">; +def IL_OP_CASE : ILOpCode<16, "case">; +def IL_OP_CLG : ILOpCode<17, "clg">; +def IL_OP_CMOV : ILOpCode<18, "cmov">; +def IL_OP_CMOV_LOGICAL : ILOpCode<19, "cmov_logical">; +def IL_OP_CMP : ILOpCode<20, "cmp">; +def IL_OP_CONTINUE : ILOpCode<21, "continue">; +def IL_OP_CONTINUE_LOGICALNZ : ILOpCode<22, "continue_logicalnz">; +def IL_OP_CONTINUE_LOGICALZ : ILOpCode<23, "continue_logicalz">; +def IL_OP_CONTINUEC : ILOpCode<24, "continuec">; +def IL_OP_COS : ILOpCode<25, "cos">; +def IL_OP_COS_VEC : ILOpCode<26, "cos_vec">; +def IL_OP_D_2_F : ILOpCode<27, "d2f">; +def IL_OP_D_ADD : ILOpCode<28, "dadd">; +def IL_OP_D_EQ : ILOpCode<29, "deq">; +def IL_OP_D_FRC : ILOpCode<30, "dfrac">; +def IL_OP_D_FREXP : ILOpCode<31, "dfrexp">; +def IL_OP_D_GE : ILOpCode<32, "dge">; +def IL_OP_D_LDEXP : ILOpCode<33, "dldexp">; +def IL_OP_D_LT : ILOpCode<34, "dlt">; +def IL_OP_D_MAD : ILOpCode<35, "dmad">; +def IL_OP_D_MUL : ILOpCode<36, "dmul">; +def IL_OP_D_NE : ILOpCode<37, "dne">; +def IL_OP_DEFAULT : ILOpCode<38, "default">; +def IL_OP_DISCARD_LOGICALNZ : ILOpCode<39, "discard_logicalnz">; +def IL_OP_DISCARD_LOGICALZ : ILOpCode<40, "discard_logicalz">; +def IL_OP_DIV : ILOpCode<41, "div_zeroop(infinity)">; +def IL_OP_DP2 : ILOpCode<42, "dp2">; +def IL_OP_DP3 : ILOpCode<43, "dp3">; +def IL_OP_DP4 : ILOpCode<44, "dp4">; +def IL_OP_ELSE : ILOpCode<45, "else">; +def IL_OP_END : ILOpCode<46, "end">; +def IL_OP_ENDFUNC : ILOpCode<47, "endfunc">; +def IL_OP_ENDIF : ILOpCode<48, "endif">; +def IL_OP_ENDLOOP : ILOpCode<49, "endloop">; +def IL_OP_ENDMAIN : ILOpCode<50, "endmain">; +def IL_OP_ENDSWITCH : ILOpCode<51, "endswitch">; +def IL_OP_EQ : ILOpCode<52, "eq">; +def IL_OP_EXP : ILOpCode<53, "exp">; +def IL_OP_EXP_VEC : ILOpCode<54, "exp_vec">; +def IL_OP_F_2_D : ILOpCode<55, "f2d">; +def IL_OP_FLR : ILOpCode<56, "flr">; +def IL_OP_FRC : ILOpCode<57, "frc">; +def IL_OP_FTOI : ILOpCode<58, "ftoi">; +def IL_OP_FTOU : ILOpCode<59, "ftou">; +def IL_OP_FUNC : ILOpCode<60, "func">; +def IL_OP_GE : ILOpCode<61, "ge">; +def IL_OP_I_ADD : ILOpCode<62, "iadd">; +def IL_OP_I_EQ : ILOpCode<63, "ieq">; +def IL_OP_I_GE : ILOpCode<64, "ige">; +def IL_OP_I_LT : ILOpCode<65, "ilt">; +def IL_OP_I_MAD : ILOpCode<66, "imad">; +def IL_OP_I_MAX : ILOpCode<67, "imax">; +def IL_OP_I_MIN : ILOpCode<68, "imin">; +def IL_OP_I_MUL : ILOpCode<69, "imul">; +def IL_OP_I_MUL_HIGH : ILOpCode<70, "imul_high">; +def IL_OP_I_NE : ILOpCode<71, "ine">; +def IL_OP_I_NEGATE : ILOpCode<72, "inegate">; +def IL_OP_I_NOT : ILOpCode<73, "inot">; +def IL_OP_I_OR : ILOpCode<74, "ior">; +def IL_OP_I_SHL : ILOpCode<75, "ishl">; +def IL_OP_I_SHR : ILOpCode<76, "ishr">; +def IL_OP_I_XOR : ILOpCode<77, "ixor">; +def IL_OP_IF_LOGICALNZ : ILOpCode<78, "if_logicalnz">; +def IL_OP_IF_LOGICALZ : ILOpCode<79, "if_logicalz">; +def IL_OP_IFC : ILOpCode<80, "ifc">; +def IL_OP_ITOF : ILOpCode<81, "itof">; +def IL_OP_LN : ILOpCode<82, "ln">; +def IL_OP_LOG : ILOpCode<83, "log">; +def IL_OP_LOG_VEC : ILOpCode<84, "log_vec">; +def IL_OP_LOOP : ILOpCode<85, "loop">; +def IL_OP_LT : ILOpCode<86, "lt">; +def IL_OP_MAD : ILOpCode<87, "mad_ieee">; +def IL_OP_MAX : ILOpCode<88, "max_ieee">; +def IL_OP_MIN : ILOpCode<89, "min_ieee">; +def IL_OP_MOD : ILOpCode<90, "mod_ieee">; +def IL_OP_MOV : ILOpCode<91, "mov">; +def IL_OP_MUL_IEEE : ILOpCode<92, "mul_ieee">; +def IL_OP_NE : ILOpCode<93, "ne">; +def IL_OP_NRM : ILOpCode<94, "nrm_nrm4_zeroop(zero)">; +def IL_OP_POW : ILOpCode<95, "pow">; +def IL_OP_RCP : ILOpCode<96, "rcp">; +def IL_OP_RET : ILOpCode<97, "ret">; +def IL_OP_RET_DYN : ILOpCode<98, "ret_dyn">; +def IL_OP_RET_LOGICALNZ : ILOpCode<99, "ret_logicalnz">; +def IL_OP_RET_LOGICALZ : ILOpCode<100, "ret_logicalz">; +def IL_OP_RND : ILOpCode<101, "rnd">; +def IL_OP_ROUND_NEAR : ILOpCode<102, "round_nearest">; +def IL_OP_ROUND_NEG_INF : ILOpCode<103, "round_neginf">; +def IL_OP_ROUND_POS_INF : ILOpCode<104, "round_plusinf">; +def IL_OP_ROUND_ZERO : ILOpCode<105, "round_z">; +def IL_OP_RSQ : ILOpCode<106, "rsq">; +def IL_OP_RSQ_VEC : ILOpCode<107, "rsq_vec">; +def IL_OP_SAMPLE : ILOpCode<108, "sample">; +def IL_OP_SAMPLE_L : ILOpCode<109, "sample_l">; +def IL_OP_SET : ILOpCode<110, "set">; +def IL_OP_SGN : ILOpCode<111, "sgn">; +def IL_OP_SIN : ILOpCode<112, "sin">; +def IL_OP_SIN_VEC : ILOpCode<113, "sin_vec">; +def IL_OP_SUB : ILOpCode<114, "sub">; +def IL_OP_SWITCH : ILOpCode<115, "switch">; +def IL_OP_TRC : ILOpCode<116, "trc">; +def IL_OP_U_DIV : ILOpCode<117, "udiv">; +def IL_OP_U_GE : ILOpCode<118, "uge">; +def IL_OP_U_LT : ILOpCode<119, "ult">; +def IL_OP_U_MAD : ILOpCode<120, "umad">; +def IL_OP_U_MAX : ILOpCode<121, "umax">; +def IL_OP_U_MIN : ILOpCode<122, "umin">; +def IL_OP_U_MOD : ILOpCode<123, "umod">; +def IL_OP_U_MUL : ILOpCode<124, "umul">; +def IL_OP_U_MUL_HIGH : ILOpCode<125, "umul_high">; +def IL_OP_U_SHR : ILOpCode<126, "ushr">; +def IL_OP_UTOF : ILOpCode<127, "utof">; +def IL_OP_WHILE : ILOpCode<128, "whileloop">; +// SC IL instructions that are not in CAL IL +def IL_OP_ACOS : ILOpCode<129, "acos">; +def IL_OP_ASIN : ILOpCode<130, "asin">; +def IL_OP_EXN : ILOpCode<131, "exn">; +def IL_OP_UBIT_REVERSE : ILOpCode<132, "ubit_reverse">; +def IL_OP_UBIT_EXTRACT : ILOpCode<133, "ubit_extract">; +def IL_OP_IBIT_EXTRACT : ILOpCode<134, "ibit_extract">; +def IL_OP_SQRT : ILOpCode<135, "sqrt">; +def IL_OP_SQRT_VEC : ILOpCode<136, "sqrt_vec">; +def IL_OP_ATAN : ILOpCode<137, "atan">; +def IL_OP_TAN : ILOpCode<137, "tan">; +def IL_OP_D_DIV : ILOpCode<138, "ddiv">; +def IL_OP_F_NEG : ILOpCode<139, "mov">; +def IL_OP_GT : ILOpCode<140, "gt">; +def IL_OP_LE : ILOpCode<141, "lt">; +def IL_OP_DIST : ILOpCode<142, "dist">; +def IL_OP_LEN : ILOpCode<143, "len">; +def IL_OP_MACRO : ILOpCode<144, "mcall">; +def IL_OP_INTR : ILOpCode<145, "call">; +def IL_OP_I_FFB_HI : ILOpCode<146, "ffb_hi">; +def IL_OP_I_FFB_LO : ILOpCode<147, "ffb_lo">; +def IL_OP_BARRIER : ILOpCode<148, "fence_threads_memory_lds">; +def IL_OP_BARRIER_LOCAL : ILOpCode<149, "fence_threads_lds">; +def IL_OP_BARRIER_GLOBAL : ILOpCode<150, "fence_threads_memory">; +def IL_OP_FENCE : ILOpCode<151, "fence_lds_memory">; +def IL_OP_FENCE_READ_ONLY : ILOpCode<152, "fence_lds_mem_read_only">; +def IL_OP_FENCE_WRITE_ONLY : ILOpCode<153, "fence_lds_mem_write_only">; +def IL_PSEUDO_INST : ILOpCode<154, ";Pseudo Op">; +def IL_OP_UNPACK_0 : ILOpCode<155, "unpack0">; +def IL_OP_UNPACK_1 : ILOpCode<156, "unpack1">; +def IL_OP_UNPACK_2 : ILOpCode<157, "unpack2">; +def IL_OP_UNPACK_3 : ILOpCode<158, "unpack3">; +def IL_OP_PI_REDUCE : ILOpCode<159, "pireduce">; +def IL_OP_IBIT_COUNT : ILOpCode<160, "icbits">; +def IL_OP_I_FFB_SGN : ILOpCode<161, "ffb_shi">; +def IL_OP_F2U4 : ILOpCode<162, "f_2_u4">; +def IL_OP_BIT_ALIGN : ILOpCode<163, "bitalign">; +def IL_OP_BYTE_ALIGN : ILOpCode<164, "bytealign">; +def IL_OP_U4_LERP : ILOpCode<165, "u4lerp">; +def IL_OP_SAD : ILOpCode<166, "sad">; +def IL_OP_SAD_HI : ILOpCode<167, "sadhi">; +def IL_OP_SAD4 : ILOpCode<168, "sad4">; +def IL_OP_UBIT_INSERT : ILOpCode<169, "ubit_insert">; +def IL_OP_I_CARRY : ILOpCode<170, "icarry">; +def IL_OP_I_BORROW : ILOpCode<171, "iborrow">; +def IL_OP_U_MAD24 : ILOpCode<172, "umad24">; +def IL_OP_U_MUL24 : ILOpCode<173, "umul24">; +def IL_OP_I_MAD24 : ILOpCode<174, "imad24">; +def IL_OP_I_MUL24 : ILOpCode<175, "imul24">; +def IL_OP_CLAMP : ILOpCode<176, "clamp">; +def IL_OP_LERP : ILOpCode<177, "lrp">; +def IL_OP_FMA : ILOpCode<178, "fma">; +def IL_OP_D_MIN : ILOpCode<179, "dmin">; +def IL_OP_D_MAX : ILOpCode<180, "dmax">; +def IL_OP_D_SQRT : ILOpCode<181, "dsqrt">; +def IL_OP_DP2_ADD : ILOpCode<182, "dp2add">; +def IL_OP_F16_TO_F32 : ILOpCode<183, "f162f">; +def IL_OP_F32_TO_F16 : ILOpCode<184, "f2f16">; +def IL_REG_LOCAL_ID_FLAT : ILOpCode<185, "vTidInGrpFlat">; +def IL_REG_LOCAL_ID : ILOpCode<186, "vTidInGrp">; +def IL_REG_GLOBAL_ID_FLAT : ILOpCode<187, "vAbsTidFlag">; +def IL_REG_GLOBAL_ID : ILOpCode<188, "vAbsTid">; +def IL_REG_GROUP_ID_FLAT : ILOpCode<189, "vThreadGrpIDFlat">; +def IL_REG_GROUP_ID : ILOpCode<190, "vThreadGrpID">; +def IL_OP_D_RCP : ILOpCode<191, "drcp_zeroop(infinity)">; +def IL_OP_D_RSQ : ILOpCode<192, "drsq_zeroop(infinity)">; +def IL_OP_D_MOV : ILOpCode<193, "dmov">; +def IL_OP_D_MOVC : ILOpCode<194, "dmovc">; +def IL_OP_NOP : ILOpCode<195, "nop">; +def IL_OP_UAV_ADD : ILOpCode<196, "uav_add">; +def IL_OP_UAV_AND : ILOpCode<197, "uav_and">; +def IL_OP_UAV_MAX : ILOpCode<198, "uav_max">; +def IL_OP_UAV_MIN : ILOpCode<199, "uav_min">; +def IL_OP_UAV_OR : ILOpCode<200, "uav_or">; +def IL_OP_UAV_RSUB : ILOpCode<201, "uav_rsub">; +def IL_OP_UAV_SUB : ILOpCode<202, "uav_sub">; +def IL_OP_UAV_UMAX : ILOpCode<203, "uav_umax">; +def IL_OP_UAV_UMIN : ILOpCode<204, "uav_umin">; +def IL_OP_UAV_XOR : ILOpCode<205, "uav_xor">; +def IL_OP_UAV_INC : ILOpCode<206, "uav_uinc">; +def IL_OP_UAV_DEC : ILOpCode<207, "uav_udec">; +def IL_OP_UAV_CMP : ILOpCode<208, "uav_cmp">; +def IL_OP_UAV_READ_ADD : ILOpCode<209, "uav_read_add">; +def IL_OP_UAV_READ_AND : ILOpCode<210, "uav_read_and">; +def IL_OP_UAV_READ_MAX : ILOpCode<211, "uav_read_max">; +def IL_OP_UAV_READ_MIN : ILOpCode<212, "uav_read_min">; +def IL_OP_UAV_READ_OR : ILOpCode<213, "uav_read_or">; +def IL_OP_UAV_READ_RSUB : ILOpCode<214, "uav_read_rsub">; +def IL_OP_UAV_READ_SUB : ILOpCode<215, "uav_read_sub">; +def IL_OP_UAV_READ_UMAX : ILOpCode<216, "uav_read_umax">; +def IL_OP_UAV_READ_UMIN : ILOpCode<217, "uav_read_umin">; +def IL_OP_UAV_READ_XOR : ILOpCode<218, "uav_read_xor">; +def IL_OP_UAV_READ_INC : ILOpCode<219, "uav_read_uinc">; +def IL_OP_UAV_READ_DEC : ILOpCode<220, "uav_read_udec">; +def IL_OP_UAV_READ_XCHG : ILOpCode<221, "uav_read_xchg">; +def IL_OP_UAV_READ_CMPXCHG : ILOpCode<222, "uav_read_cmp_xchg">; +def IL_OP_LDS_ADD : ILOpCode<223, "lds_add">; +def IL_OP_LDS_AND : ILOpCode<224, "lds_and">; +def IL_OP_LDS_MAX : ILOpCode<225, "lds_max">; +def IL_OP_LDS_MIN : ILOpCode<226, "lds_min">; +def IL_OP_LDS_OR : ILOpCode<227, "lds_or">; +def IL_OP_LDS_RSUB : ILOpCode<228, "lds_rsub">; +def IL_OP_LDS_SUB : ILOpCode<229, "lds_sub">; +def IL_OP_LDS_UMAX : ILOpCode<230, "lds_umax">; +def IL_OP_LDS_UMIN : ILOpCode<231, "lds_umin">; +def IL_OP_LDS_XOR : ILOpCode<232, "lds_xor">; +def IL_OP_LDS_INC : ILOpCode<233, "lds_inc">; +def IL_OP_LDS_DEC : ILOpCode<234, "lds_dec">; +def IL_OP_LDS_CMP : ILOpCode<235, "lds_cmp">; +def IL_OP_LDS_READ_ADD : ILOpCode<236, "lds_read_add">; +def IL_OP_LDS_READ_AND : ILOpCode<237, "lds_read_and">; +def IL_OP_LDS_READ_MAX : ILOpCode<238, "lds_read_max">; +def IL_OP_LDS_READ_MIN : ILOpCode<239, "lds_read_min">; +def IL_OP_LDS_READ_OR : ILOpCode<240, "lds_read_or">; +def IL_OP_LDS_READ_RSUB : ILOpCode<241, "lds_read_rsub">; +def IL_OP_LDS_READ_SUB : ILOpCode<242, "lds_read_sub">; +def IL_OP_LDS_READ_UMAX : ILOpCode<243, "lds_read_umax">; +def IL_OP_LDS_READ_UMIN : ILOpCode<244, "lds_read_umin">; +def IL_OP_LDS_READ_XOR : ILOpCode<245, "lds_read_xor">; +def IL_OP_LDS_READ_INC : ILOpCode<246, "lds_read_inc">; +def IL_OP_LDS_READ_DEC : ILOpCode<247, "lds_read_dec">; +def IL_OP_LDS_READ_XCHG : ILOpCode<248, "lds_read_xchg">; +def IL_OP_LDS_READ_CMPXCHG : ILOpCode<249, "lds_read_cmp_xchg">; +def IL_OP_GDS_ADD : ILOpCode<250, "gds_add">; +def IL_OP_GDS_AND : ILOpCode<251, "gds_and">; +def IL_OP_GDS_MAX : ILOpCode<252, "gds_max">; +def IL_OP_GDS_MIN : ILOpCode<253, "gds_min">; +def IL_OP_GDS_OR : ILOpCode<254, "gds_or">; +def IL_OP_GDS_RSUB : ILOpCode<255, "gds_rsub">; +def IL_OP_GDS_SUB : ILOpCode<256, "gds_sub">; +def IL_OP_GDS_UMAX : ILOpCode<257, "gds_umax">; +def IL_OP_GDS_UMIN : ILOpCode<258, "gds_umin">; +def IL_OP_GDS_MSKOR : ILOpCode<259, "gds_mskor">; +def IL_OP_GDS_XOR : ILOpCode<260, "gds_xor">; +def IL_OP_GDS_INC : ILOpCode<261, "gds_inc">; +def IL_OP_GDS_DEC : ILOpCode<262, "gds_dec">; +def IL_OP_GDS_CMP : ILOpCode<263, "gds_cmp">; +def IL_OP_GDS_READ_ADD : ILOpCode<264, "gds_read_add">; +def IL_OP_GDS_READ_AND : ILOpCode<265, "gds_read_and">; +def IL_OP_GDS_READ_MAX : ILOpCode<266, "gds_read_max">; +def IL_OP_GDS_READ_MIN : ILOpCode<267, "gds_read_min">; +def IL_OP_GDS_READ_OR : ILOpCode<268, "gds_read_or">; +def IL_OP_GDS_READ_RSUB : ILOpCode<269, "gds_read_rsub">; +def IL_OP_GDS_READ_SUB : ILOpCode<270, "gds_read_sub">; +def IL_OP_GDS_READ_UMAX : ILOpCode<271, "gds_read_umax">; +def IL_OP_GDS_READ_UMIN : ILOpCode<272, "gds_read_umin">; +def IL_OP_GDS_READ_MSKOR : ILOpCode<273, "gds_read_mskor">; +def IL_OP_GDS_READ_XOR : ILOpCode<274, "gds_read_xor">; +def IL_OP_GDS_READ_INC : ILOpCode<275, "gds_read_inc">; +def IL_OP_GDS_READ_DEC : ILOpCode<276, "gds_read_dec">; +def IL_OP_GDS_READ_XCHG : ILOpCode<277, "gds_read_xchg">; +def IL_OP_GDS_READ_CMPXCHG : ILOpCode<278, "gds_read_cmp_xchg">; +def IL_OP_APPEND_BUF_ALLOC : ILOpCode<279, "append_buf_alloc">; +def IL_OP_APPEND_BUF_CONSUME : ILOpCode<280, "append_buf_consume">; +def IL_OP_I64_ADD : ILOpCode<281, "i64add">; +def IL_OP_I64_MAX : ILOpCode<282, "i64max">; +def IL_OP_U64_MAX : ILOpCode<283, "u64max">; +def IL_OP_I64_MIN : ILOpCode<284, "i64min">; +def IL_OP_U64_MIN : ILOpCode<285, "u64min">; +def IL_OP_I64_NEGATE : ILOpCode<286, "i64negate">; +def IL_OP_I64_SHL : ILOpCode<287, "i64shl">; +def IL_OP_I64_SHR : ILOpCode<288, "i64shr">; +def IL_OP_U64_SHR : ILOpCode<289, "u64shr">; +def IL_OP_I64_EQ : ILOpCode<290, "i64eq">; +def IL_OP_I64_GE : ILOpCode<291, "i64ge">; +def IL_OP_U64_GE : ILOpCode<292, "u64ge">; +def IL_OP_I64_LT : ILOpCode<293, "i64lt">; +def IL_OP_U64_LT : ILOpCode<294, "u64lt">; +def IL_OP_I64_NE : ILOpCode<295, "i64ne">; +def IL_OP_U_MULHI24 : ILOpCode<296, "umul24_high">; +def IL_OP_I_MULHI24 : ILOpCode<297, "imul24_high">; +def IL_OP_GDS_LOAD : ILOpCode<298, "gds_load">; +def IL_OP_GDS_STORE : ILOpCode<299, "gds_store">; +def IL_OP_LDS_LOAD : ILOpCode<300, "lds_load">; +def IL_OP_LDS_LOAD_VEC : ILOpCode<301, "lds_load_vec">; +def IL_OP_LDS_LOAD_BYTE : ILOpCode<302, "lds_load_byte">; +def IL_OP_LDS_LOAD_UBYTE : ILOpCode<303, "lds_load_ubyte">; +def IL_OP_LDS_LOAD_SHORT : ILOpCode<304, "lds_load_short">; +def IL_OP_LDS_LOAD_USHORT : ILOpCode<305, "lds_load_ushort">; +def IL_OP_LDS_STORE : ILOpCode<306, "lds_store">; +def IL_OP_LDS_STORE_VEC : ILOpCode<307, "lds_store_vec">; +def IL_OP_LDS_STORE_BYTE : ILOpCode<308, "lds_store_byte">; +def IL_OP_LDS_STORE_SHORT : ILOpCode<309, "lds_store_short">; +def IL_OP_RAW_UAV_LOAD : ILOpCode<310, "uav_raw_load">; +def IL_OP_RAW_UAV_STORE : ILOpCode<311, "uav_raw_store">; +def IL_OP_ARENA_UAV_LOAD : ILOpCode<312, "uav_arena_load">; +def IL_OP_ARENA_UAV_STORE : ILOpCode<313, "uav_arena_store">; +def IL_OP_LDS_MSKOR : ILOpCode<314, "lds_mskor">; +def IL_OP_LDS_READ_MSKOR : ILOpCode<315, "lds_read_mskor">; +def IL_OP_UAV_BYTE_LOAD : ILOpCode<316, "uav_byte_load">; +def IL_OP_UAV_UBYTE_LOAD : ILOpCode<317, "uav_ubyte_load">; +def IL_OP_UAV_SHORT_LOAD : ILOpCode<318, "uav_short_load">; +def IL_OP_UAV_USHORT_LOAD : ILOpCode<319, "uav_ushort_load">; +def IL_OP_UAV_BYTE_STORE : ILOpCode<320, "uav_byte_store">; +def IL_OP_UAV_SHORT_STORE : ILOpCode<320, "uav_short_store">; +def IL_OP_UAV_STORE : ILOpCode<321, "uav_store">; +def IL_OP_UAV_LOAD : ILOpCode<322, "uav_load">; +def IL_OP_MUL : ILOpCode<323, "mul">; +def IL_OP_DIV_INF : ILOpCode<324, "div_zeroop(infinity)">; +def IL_OP_DIV_FLTMAX : ILOpCode<325, "div_zeroop(fltmax)">; +def IL_OP_DIV_ZERO : ILOpCode<326, "div_zeroop(zero)">; +def IL_OP_DIV_INFELSEMAX : ILOpCode<327, "div_zeroop(inf_else_max)">; +def IL_OP_FTOI_FLR : ILOpCode<328, "ftoi_flr">; +def IL_OP_FTOI_RPI : ILOpCode<329, "ftoi_rpi">; +def IL_OP_F32_TO_F16_NEAR : ILOpCode<330, "f2f16_near">; +def IL_OP_F32_TO_F16_NEG_INF : ILOpCode<331, "f2f16_neg_inf">; +def IL_OP_F32_TO_F16_PLUS_INF : ILOpCode<332, "f2f16_plus_inf">; +def IL_OP_I64_MUL : ILOpCode<333, "i64mul">; +def IL_OP_U64_MUL : ILOpCode<334, "u64mul">; +def IL_OP_CU_ID : ILOpCode<355, "cu_id">; +def IL_OP_WAVE_ID : ILOpCode<356, "wave_id">; +def IL_OP_I64_SUB : ILOpCode<357, "i64sub">; +def IL_OP_I64_DIV : ILOpCode<358, "i64div">; +def IL_OP_U64_DIV : ILOpCode<359, "u64div">; +def IL_OP_I64_MOD : ILOpCode<360, "i64mod">; +def IL_OP_U64_MOD : ILOpCode<361, "u64mod">; +def IL_DCL_GWS_THREAD_COUNT : ILOpCode<362, "dcl_gws_thread_count">; +def IL_DCL_SEMAPHORE : ILOpCode<363, "dcl_semaphore">; +def IL_OP_SEMAPHORE_INIT : ILOpCode<364, "init_semaphore">; +def IL_OP_SEMAPHORE_WAIT : ILOpCode<365, "semaphore_wait">; +def IL_OP_SEMAPHORE_SIGNAL : ILOpCode<366, "semaphore_signal">; +def IL_OP_BARRIER_REGION : ILOpCode<377, "fence_threads_gds">; +def IL_OP_BFI : ILOpCode<394, "bfi">; +def IL_OP_BFM : ILOpCode<395, "bfm">; +def IL_DBG_STRING : ILOpCode<396, "dbg_string">; +def IL_DBG_LINE : ILOpCode<397, "dbg_line">; +def IL_DBG_TEMPLOC : ILOpCode<398, "dbg_temploc">; diff --git a/lib/Target/AMDIL/AMDILFormats.td b/lib/Target/AMDIL/AMDILFormats.td new file mode 100644 index 00000000000..99489e7e92c --- /dev/null +++ b/lib/Target/AMDIL/AMDILFormats.td @@ -0,0 +1,450 @@ +//==- AMDILFormats.td - AMDIL Instruction Formats ----*- tablegen -*-==// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//==-----------------------------------------------------------------------===// +// +//===--------------------------------------------------------------------===// +include "AMDILTokenDesc.td" + +//===--------------------------------------------------------------------===// +// The parent IL instruction class that inherits the Instruction class. This +// class sets the corresponding namespace, the out and input dag lists the +// pattern to match to and the string to print out for the assembly printer. +//===--------------------------------------------------------------------===// +class ILFormat pattern> +: Instruction { + + let Namespace = "AMDIL"; + dag OutOperandList = outs; + dag InOperandList = ins; + ILOpCode operation = op; + let Pattern = pattern; + let AsmString = !strconcat(asmstr, "\n"); + let isPseudo = 1; + bit hasIEEEFlag = 0; + bit hasZeroOpFlag = 0; +} + +//===--------------------------------------------------------------------===// +// The base class for vector insert instructions. It is a single dest, quad +// source instruction where the last two source operands must be 32bit +// immediate values that are encoding the swizzle of the source register +// The src2 and src3 instructions must also be inversion of each other such +// that if src2 is 0x1000300(x0z0), src3 must be 0x20004(0y0w). The values +// are encoded as 32bit integer with each 8 char representing a swizzle value. +// The encoding is as follows for 32bit register types: +// 0x00 -> '_' +// 0x01 -> 'x' +// 0x02 -> 'y' +// 0x03 -> 'z' +// 0x04 -> 'w' +// 0x05 -> 'x' +// 0x06 -> 'y' +// 0x07 -> 'z' +// 0x08 -> 'w' +// 0x09 -> '0' +// The encoding is as follows for 64bit register types: +// 0x00 -> "__" +// 0x01 -> "xy" +// 0x02 -> "zw" +// 0x03 -> "xy" +// 0x04 -> "zw" +// 0x05 -> "00" +//===--------------------------------------------------------------------===// +class InsertVectorClass : + ILFormat; + +//===--------------------------------------------------------------------===// +// Class that has one input parameters and one output parameter. +// The basic pattern for this class is "Opcode Dst, Src0" and +// handles the unary math operators. +// It sets the binary token ILSrc, ILSrcMod, ILRelAddr and ILSrc and ILSrcMod +// if the addressing is register relative for input and output register 0. +//===--------------------------------------------------------------------===// +class OneInOneOut pattern> + : ILFormat +{ + ILDst dst_reg; + ILDstMod dst_mod; + ILRelAddr dst_rel; + ILSrc dst_reg_rel; + ILSrcMod dst_reg_rel_mod; + ILSrc src0_reg; + ILSrcMod src0_mod; + ILRelAddr src0_rel; + ILSrc src0_reg_rel; + ILSrcMod src0_reg_rel_mod; +} + +//===--------------------------------------------------------------------===// +// A simplified version of OneInOneOut class where the pattern is standard +// and does not need special cases. This requires that the pattern has +// a SDNode and takes a source and destination register that is of type +// RegisterClass. This is the standard unary op class. +//===--------------------------------------------------------------------===// +class UnaryOp + : OneInOneOut; + +//===--------------------------------------------------------------------===// +// This class is similiar to the UnaryOp class, however, there is no +// result value to assign. +//===--------------------------------------------------------------------===// +class UnaryOpNoRet pattern> + : ILFormat +{ + ILSrc src0_reg; + ILSrcMod src0_mod; + ILRelAddr src0_rel; + ILSrc src0_reg_rel; + ILSrcMod src0_reg_rel_mod; +} + +//===--------------------------------------------------------------------===// +// Set of classes that have two input parameters and one output parameter. +// The basic pattern for this class is "Opcode Dst, Src0, Src1" and +// handles the binary math operators and comparison operations. +// It sets the binary token ILSrc, ILSrcMod, ILRelAddr and ILSrc and ILSrcMod +// if the addressing is register relative for input register 1. +//===--------------------------------------------------------------------===// +class TwoInOneOut pattern> + : OneInOneOut +{ + ILSrc src1_reg; + ILSrcMod src1_mod; + ILRelAddr src1_rel; + ILSrc src1_reg_rel; + ILSrcMod src1_reg_rel_mod; +} +//===--------------------------------------------------------------------===// +// A simplification of the TwoInOneOut pattern for Binary Operations. +// This class is a helper class that assumes the simple pattern of +// $dst = op $src0 $src1. +// Other type of matching patterns need to use the TwoInOneOut class. +//===--------------------------------------------------------------------===// +class BinaryOp + : TwoInOneOut; + +//===--------------------------------------------------------------------===// +// The base class for vector extract instructions. The vector extract +// instructions take as an input value a source register and a 32bit integer +// with the same encoding as specified in InsertVectorClass and produces +// a result with only the swizzled component in the destination register. +//===--------------------------------------------------------------------===// +class ExtractVectorClass +: TwoInOneOut; + +//===--------------------------------------------------------------------===// +// The base class for vector concatenation. This class creates either a vec2 +// or a vec4 of 32bit data types or a vec2 of 64bit data types. This is done +// by swizzling either the 'x' or 'xy' components of the source operands +// into the destination register. +//===--------------------------------------------------------------------===// +class VectorConcatClass + : TwoInOneOut; + +//===--------------------------------------------------------------------===// +// Similiar to the UnaryOpNoRet class, but takes as arguments two input +// operands. Used mainly for barrier instructions on PC platform. +//===--------------------------------------------------------------------===// +class BinaryOpNoRet pattern> + : UnaryOpNoRet +{ + ILSrc src1_reg; + ILSrcMod src1_mod; + ILRelAddr src1_rel; + ILSrc src1_reg_rel; + ILSrcMod src1_reg_rel_mod; +} + +//===--------------------------------------------------------------------===// +// Set of classes that have three input parameters and one output parameter. +// The basic pattern for this class is "Opcode Dst, Src0, Src1, Src2" and +// handles the mad and conditional mov instruction. +// It sets the binary token ILSrc, ILSrcMod, ILRelAddr and ILSrc and ILSrcMod +// if the addressing is register relative. +// This class is the parent class of TernaryOp +//===--------------------------------------------------------------------===// +class ThreeInOneOut pattern> + : TwoInOneOut { + ILSrc src2_reg; + ILSrcMod src2_mod; + ILRelAddr src2_rel; + ILSrc src2_reg_rel; + ILSrcMod src2_reg_rel_mod; + } + +//===--------------------------------------------------------------------===// +// The g version of the Three Input pattern uses a standard pattern but +// but allows specification of the register to further generalize the class +// This class is mainly used in the generic multiclasses in AMDILMultiClass.td +//===--------------------------------------------------------------------===// +class TernaryOp + : ThreeInOneOut; + +//===--------------------------------------------------------------------===// +// Set of classes that have three input parameters and one output parameter. +// The basic pattern for this class is "Opcode Dst, Src0, Src1, Src2" and +// handles the mad and conditional mov instruction. +// It sets the binary token ILSrc, ILSrcMod, ILRelAddr and ILSrc and ILSrcMod +// if the addressing is register relative. +// This class is the parent class of TernaryOp +//===--------------------------------------------------------------------===// +class FourInOneOut pattern> + : ThreeInOneOut { + ILSrc src3_reg; + ILSrcMod src3_mod; + ILRelAddr src3_rel; + ILSrc src3_reg_rel; + ILSrcMod src3_reg_rel_mod; + } + + +//===--------------------------------------------------------------------===// +// The macro class that is an extension of OneInOneOut but is tailored for +// macros only where all the register types are the same +//===--------------------------------------------------------------------===// +class UnaryMacro +: OneInOneOut; + +//===--------------------------------------------------------------------===// +// The macro class is an extension of TwoInOneOut but is tailored for +// macros only where all the register types are the same +//===--------------------------------------------------------------------===// +class BinaryMacro + : TwoInOneOut; + +//===--------------------------------------------------------------------===// +// Classes for dealing with atomic instructions w/ 32bit pointers +//===--------------------------------------------------------------------===// +class Append + : ILFormat; + + +// TODO: Need to get this working without dst... +class AppendNoRet + : ILFormat; + +class UniAtom + : ILFormat; + + +// TODO: Need to get this working without dst... +class UniAtomNoRet + : ILFormat; + +class BinAtom + : ILFormat; + + +// TODO: Need to get this working without dst... +class BinAtomNoRet + : ILFormat; + +class TriAtom + : ILFormat; + +class CmpXChg + : ILFormat; + +// TODO: Need to get this working without dst... +class TriAtomNoRet + : ILFormat; + +// TODO: Need to get this working without dst... +class CmpXChgNoRet + : ILFormat; + + +//===--------------------------------------------------------------------===// +// Classes for dealing with atomic instructions w/ 64bit pointers +//===--------------------------------------------------------------------===// +class Append64 + : ILFormat; + + +// TODO: Need to get this working without dst... +class AppendNoRet64 + : ILFormat; + +class UniAtom64 + : ILFormat; + + +// TODO: Need to get this working without dst... +class UniAtomNoRet64 + : ILFormat; + +class BinAtom64 + : ILFormat; + + +// TODO: Need to get this working without dst... +class BinAtomNoRet64 + : ILFormat; + +class TriAtom64 + : ILFormat; + +class CmpXChg64 + : ILFormat; + +// TODO: Need to get this working without dst... +class TriAtomNoRet64 + : ILFormat; + +// TODO: Need to get this working without dst... +class CmpXChgNoRet64 + : ILFormat; + +//===--------------------------------------------------------------------===// +// Intrinsic classes +// Generic versions of the above classes but for Target specific intrinsics +// instead of SDNode patterns. +//===--------------------------------------------------------------------===// +let TargetPrefix = "AMDIL", isTarget = 1 in { + class VoidIntLong : + Intrinsic<[llvm_i64_ty], [], []>; + class VoidIntInt : + Intrinsic<[llvm_i32_ty], [], []>; + class VoidIntBool : + Intrinsic<[llvm_i32_ty], [], []>; + class UnaryIntInt : + Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>], []>; + class UnaryIntFloat : + Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>], []>; + class ConvertIntFTOI : + Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty], []>; + class ConvertIntITOF : + Intrinsic<[llvm_anyfloat_ty], [llvm_anyint_ty], []>; + class UnaryIntNoRetInt : + Intrinsic<[], [llvm_anyint_ty], []>; + class UnaryIntNoRetFloat : + Intrinsic<[], [llvm_anyfloat_ty], []>; + class BinaryIntInt : + Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, LLVMMatchType<0>], []>; + class BinaryIntFloat : + Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>, LLVMMatchType<0>], []>; + class BinaryIntNoRetInt : + Intrinsic<[], [llvm_anyint_ty, LLVMMatchType<0>], []>; + class BinaryIntNoRetFloat : + Intrinsic<[], [llvm_anyfloat_ty, LLVMMatchType<0>], []>; + class TernaryIntInt : + Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, + LLVMMatchType<0>, LLVMMatchType<0>], []>; + class TernaryIntFloat : + Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>, + LLVMMatchType<0>, LLVMMatchType<0>], []>; + class QuaternaryIntInt : + Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>, + LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>], []>; + class UnaryAtomicInt : + Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i32_ty], [IntrReadWriteArgMem]>; + class BinaryAtomicInt : + Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty], [IntrReadWriteArgMem]>; + class TernaryAtomicInt : + Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty]>; + class UnaryAtomicIntNoRet : + Intrinsic<[], [llvm_ptr_ty, llvm_i32_ty], [IntrReadWriteArgMem]>; + class BinaryAtomicIntNoRet : + Intrinsic<[], [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty], [IntrReadWriteArgMem]>; + class TernaryAtomicIntNoRet : + Intrinsic<[], [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrReadWriteArgMem]>; +} diff --git a/lib/Target/AMDIL/AMDILInstrInfo.td b/lib/Target/AMDIL/AMDILInstrInfo.td new file mode 100644 index 00000000000..7086e53a0c0 --- /dev/null +++ b/lib/Target/AMDIL/AMDILInstrInfo.td @@ -0,0 +1,115 @@ +//===------------ AMDILInstrInfo.td - AMDIL Target ------*-tablegen-*------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//==-----------------------------------------------------------------------===// +// +// This file describes the AMDIL instructions in TableGen format. +// +//===----------------------------------------------------------------------===// +// AMDIL Instruction Predicate Definitions +// Predicate that is set to true if the hardware supports double precision +// divide +def HasHWDDiv : Predicate<"Subtarget.device()" + "->getGeneration() > AMDILDeviceInfo::HD4XXX && " + "Subtarget.device()->usesHardware(AMDILDeviceInfo::DoubleOps)">; + +// Predicate that is set to true if the hardware supports double, but not double +// precision divide in hardware +def HasSWDDiv : Predicate<"Subtarget.device()" + "->getGeneration() == AMDILDeviceInfo::HD4XXX &&" + "Subtarget.device()->usesHardware(AMDILDeviceInfo::DoubleOps)">; + +// Predicate that is set to true if the hardware support 24bit signed +// math ops. Otherwise a software expansion to 32bit math ops is used instead. +def HasHWSign24Bit : Predicate<"Subtarget.device()" + "->getGeneration() > AMDILDeviceInfo::HD5XXX">; + +// Predicate that is set to true if 64bit operations are supported or not +def HasHW64Bit : Predicate<"Subtarget.device()" + "->usesHardware(AMDILDeviceInfo::LongOps)">; +def HasSW64Bit : Predicate<"Subtarget.device()" + "->usesSoftware(AMDILDeviceInfo::LongOps)">; + +// Predicate that is set to true if the timer register is supported +def HasTmrRegister : Predicate<"Subtarget.device()" + "->isSupported(AMDILDeviceInfo::TmrReg)">; +// Predicate that is true if we are at least evergreen series +def HasDeviceIDInst : Predicate<"Subtarget.device()" + "->getGeneration() >= AMDILDeviceInfo::HD5XXX">; + +// Predicate that is true if we have region address space. +def hasRegionAS : Predicate<"Subtarget.device()" + "->usesHardware(AMDILDeviceInfo::RegionMem)">; + +// Predicate that is false if we don't have region address space. +def noRegionAS : Predicate<"!Subtarget.device()" + "->isSupported(AMDILDeviceInfo::RegionMem)">; + + +// Predicate that is set to true if 64bit Mul is supported in the IL or not +def HasHW64Mul : Predicate<"Subtarget.calVersion()" + ">= CAL_VERSION_SC_139" + "&& Subtarget.device()" + "->getGeneration() >=" + "AMDILDeviceInfo::HD5XXX">; +def HasSW64Mul : Predicate<"Subtarget.calVersion()" + "< CAL_VERSION_SC_139">; +// Predicate that is set to true if 64bit Div/Mod is supported in the IL or not +def HasHW64DivMod : Predicate<"Subtarget.device()" + "->usesHardware(AMDILDeviceInfo::HW64BitDivMod)">; +def HasSW64DivMod : Predicate<"Subtarget.device()" + "->usesSoftware(AMDILDeviceInfo::HW64BitDivMod)">; + +// Predicate that is set to true if 64bit pointer are used. +def Has64BitPtr : Predicate<"Subtarget.is64bit()">; +def Has32BitPtr : Predicate<"!Subtarget.is64bit()">; +//===--------------------------------------------------------------------===// +// Custom Operands +//===--------------------------------------------------------------------===// +include "AMDILOperands.td" + +//===--------------------------------------------------------------------===// +// Custom Selection DAG Type Profiles +//===--------------------------------------------------------------------===// +include "AMDILProfiles.td" + +//===--------------------------------------------------------------------===// +// Custom Selection DAG Nodes +//===--------------------------------------------------------------------===// +include "AMDILNodes.td" + +//===--------------------------------------------------------------------===// +// Custom Pattern DAG Nodes +//===--------------------------------------------------------------------===// +include "AMDILPatterns.td" + +//===----------------------------------------------------------------------===// +// Instruction format classes +//===----------------------------------------------------------------------===// +include "AMDILFormats.td" + +//===--------------------------------------------------------------------===// +// Multiclass Instruction formats +//===--------------------------------------------------------------------===// +include "AMDILMultiClass.td" + +//===--------------------------------------------------------------------===// +// Intrinsics support +//===--------------------------------------------------------------------===// +include "AMDILIntrinsics.td" + +//===--------------------------------------------------------------------===// +// Instructions support +//===--------------------------------------------------------------------===// +include "AMDILInstructions.td" + +//===--------------------------------------------------------------------===// +// Instruction Pattern support - This Must be the last include in the file +// as it requires items defined in other files +//===--------------------------------------------------------------------===// +include "AMDILInstrPatterns.td" + diff --git a/lib/Target/AMDIL/AMDILInstrPatterns.td b/lib/Target/AMDIL/AMDILInstrPatterns.td new file mode 100644 index 00000000000..51181b2a5dc --- /dev/null +++ b/lib/Target/AMDIL/AMDILInstrPatterns.td @@ -0,0 +1,66 @@ +//===- AMDILInstrPatterns.td - AMDIL Target ------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//==-----------------------------------------------------------------------===// +//===--------------------------------------------------------------------===// +// This file holds all the custom patterns that are used by the amdil backend +// +//===--------------------------------------------------------------------===// +//===--------------------------------------------------------------------===// +// Custom patterns for conversion operations +//===--------------------------------------------------------------------===//// +// Pattern to remap integer or to IL_or +def : Pat<(i32 (or GPRI32:$src0, GPRI32:$src1)), + (i32 (BINARY_OR_i32 GPRI32:$src0, GPRI32:$src1))>; +// float ==> long patterns +// unsigned: f32 -> i64 +def FTOUL : Pat<(i64 (fp_to_uint GPRF32:$src)), + (LCREATE (FTOU GPRF32:$src), (LOADCONST_i32 0))>; +// signed: f32 -> i64 +def FTOL : Pat<(i64 (fp_to_sint GPRF32:$src)), + (LCREATE (FTOI GPRF32:$src), (LOADCONST_i32 0))>; +// unsigned: i64 -> f32 +def ULTOF : Pat<(f32 (uint_to_fp GPRI64:$src)), + (UTOF (LLO GPRI64:$src))>; +// signed: i64 -> f32 +def LTOF : Pat<(f32 (sint_to_fp GPRI64:$src)), + (ITOF (LLO GPRI64:$src))>; + +// integer subtraction +// a - b ==> a + (-b) +def SUB_i8 : Pat<(sub GPRI8:$src0, GPRI8:$src1), + (ADD_i8 GPRI8:$src0, (NEGATE_i8 GPRI8:$src1))>; +def SUB_v2i8 : Pat<(sub GPRV2I8:$src0, GPRV2I8:$src1), + (ADD_v2i8 GPRV2I8:$src0, (NEGATE_v2i8 GPRV2I8:$src1))>; +def SUB_v4i8 : Pat<(sub GPRV4I8:$src0, GPRV4I8:$src1), + (ADD_v4i8 GPRV4I8:$src0, (NEGATE_v4i8 GPRV4I8:$src1))>; +def SUB_i16 : Pat<(sub GPRI16:$src0, GPRI16:$src1), + (ADD_i16 GPRI16:$src0, (NEGATE_i16 GPRI16:$src1))>; +def SUB_v2i16 : Pat<(sub GPRV2I16:$src0, GPRV2I16:$src1), + (ADD_v2i16 GPRV2I16:$src0, (NEGATE_v2i16 GPRV2I16:$src1))>; +def SUB_v4i16 : Pat<(sub GPRV4I16:$src0, GPRV4I16:$src1), + (ADD_v4i16 GPRV4I16:$src0, (NEGATE_v4i16 GPRV4I16:$src1))>; +def SUB_i32 : Pat<(sub GPRI32:$src0, GPRI32:$src1), + (ADD_i32 GPRI32:$src0, (NEGATE_i32 GPRI32:$src1))>; +def SUB_v2i32 : Pat<(sub GPRV2I32:$src0, GPRV2I32:$src1), + (ADD_v2i32 GPRV2I32:$src0, (NEGATE_v2i32 GPRV2I32:$src1))>; +def SUB_v4i32 : Pat<(sub GPRV4I32:$src0, GPRV4I32:$src1), + (ADD_v4i32 GPRV4I32:$src0, (NEGATE_v4i32 GPRV4I32:$src1))>; +// LLVM isn't lowering this correctly, so writing a pattern that +// matches it isntead. +def : Pat<(build_vector (i32 imm:$src)), + (VCREATE_v4i32 (LOADCONST_i32 imm:$src))>; + +// Calls: +def : Pat<(IL_call tglobaladdr:$dst), + (CALL tglobaladdr:$dst)>; +def : Pat<(IL_call texternalsym:$dst), + (CALL texternalsym:$dst)>; +def : Pat<(IL_call tconstpool:$dst), + (CALL tconstpool:$dst)>; + +include "AMDILConversions.td" diff --git a/lib/Target/AMDIL/AMDILInstructions.td b/lib/Target/AMDIL/AMDILInstructions.td new file mode 100644 index 00000000000..db56e2121b3 --- /dev/null +++ b/lib/Target/AMDIL/AMDILInstructions.td @@ -0,0 +1,2436 @@ +//===-- AMDILInstructions.td - AMDIL Instruction definitions --------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//==-----------------------------------------------------------------------===// + +// Operations in this file are generic to all data types +// This opcode has custom swizzle pattern encoded in Swizzle Encoder +let isReMaterializable = 1, isAsCheapAsAMove = 1 in { + defm LOADCONST : ILConstant<"mov $dst, $val">; + defm MOVE : UnaryOpMC; + defm PHIMOVE : UnaryOpMC; +} +defm BINARY_NOT : UnaryOpMC; +defm BINARY_OR : BinaryOpMC; +defm BINARY_AND : BinaryOpMC; +defm BINARY_XOR : BinaryOpMC; +defm AND : BinaryOpMCInt; +defm CMOV : BinaryOpMC; +defm DIV_INF : BinaryOpMC; +defm SMAX : BinaryOpMCInt; +// This opcode has custom swizzle pattern encoded in Swizzle Encoder for 64bit +// instructions +defm CMOVLOG : TernaryOpMC; +// This opcode has a custom swizzle pattern in the Swizzle Encoder and +// should never be selected in ISel. It should only be generated in the +// I/O expansion code. These are different from the CMOVLOG instruction +// in that the src0 argument uses a custom swizzle for the Y/Z/W +// vector channel respectively instead of the default channel. +def CMOVLOG_Y_i32 : ThreeInOneOut; +def CMOVLOG_Z_i32 : ThreeInOneOut; +def CMOVLOG_W_i32 : ThreeInOneOut; +defm SELECTBIN : TernaryOpMCScalar; +//===---------------------------------------------------------------------===// +// Signed 8bit integer math instructions start here +//===---------------------------------------------------------------------===// +def INTTOANY_i8 : OneInOneOut; +//===---------------------------------------------------------------------===// +// Signed 16bit integer math instructions start here +//===---------------------------------------------------------------------===// +def INTTOANY_i16: OneInOneOut; +//===---------------------------------------------------------------------===// +// Signed 32bit integer math instructions start here +//===---------------------------------------------------------------------===// +defm NEGATE : UnaryOpMCi32; +defm SMUL : BinaryOpMCi32; +defm SMULHI : BinaryOpMCi32; +defm SHL : BinaryOpMCi32Const; +defm SHR : BinaryOpMCi32Const; +defm SHLVEC : BinaryOpMCi32; +defm SHRVEC : BinaryOpMCi32; +defm ADD : BinaryOpMCi32; +defm CUSTOM_XOR : BinaryOpMCInt; +// get rid of the addri via the tablegen instead of custom lowered instruction +defm CUSTOM_ADD : BinaryOpMCi32; +defm EADD : BinaryOpMCi32; +def INTTOANY_i32: OneInOneOut; +// Integer offsets for addressing +// This opcode has custom swizzle pattern encoded in Swizzle Encoder +def ADDir : TwoInOneOut; +// This opcode has custom swizzle pattern encoded in Swizzle Encoder +def ADDri : TwoInOneOut; + +defm IFFB_HI : UnaryOpMCi32; +defm IFFB_LO : UnaryOpMCi32; +let mayLoad = 0, mayStore = 0 in { +defm ABS : UnaryIntrinsicInt; +defm BITCOUNT : UnaryIntrinsicInt; +defm FFB_LO : UnaryIntrinsicInt; +defm FFB_HI : UnaryIntrinsicInt; +defm FFB_SGN : UnaryIntrinsicInt; +defm IMULHI : BinaryIntrinsicInt; +let Predicates = [HasHWSign24Bit] in { +defm IMUL24 : BinaryIntrinsicInt; +defm IMULHI24 : BinaryIntrinsicInt; +defm IMAD24 : TernaryIntrinsicInt; +} +defm CARRY : BinaryIntrinsicInt; +defm BORROW : BinaryIntrinsicInt; +defm IMIN : BinaryIntrinsicInt; +defm IMAX : BinaryIntrinsicInt; +defm CMOV_LOG : TernaryIntrinsicInt; +defm IBIT_EXTRACT : TernaryIntrinsicInt; +defm IMAD : TernaryIntrinsicInt; +defm SAD : TernaryIntrinsicInt; +defm SADHI : TernaryIntrinsicInt; +} +def SAD4_i32 : ThreeInOneOut; +def FTOV4U8_i32 : OneInOneOut; +//===---------------------------------------------------------------------===// +// Unsigned 32bit integer math instructions start here +//===---------------------------------------------------------------------===// +defm UMUL : BinaryOpMCi32; +defm UMULHI : BinaryOpMCi32; +defm USHR : BinaryOpMCi32Const; +defm USHRVEC : BinaryOpMCi32; +defm UDIV : BinaryOpMCi32; +defm NATIVE_UDIV : BinaryIntrinsicInt; +let mayLoad=0, mayStore=0 in { +defm UBIT_REVERSE : UnaryIntrinsicInt; +defm UMULHI_INT : BinaryIntrinsicInt; +defm UMULHI24 : BinaryIntrinsicInt; +defm UMUL24 : BinaryIntrinsicInt; +defm UMIN : BinaryIntrinsicInt; +defm UMAX : BinaryIntrinsicInt; +defm UBIT_EXTRACT : TernaryIntrinsicInt; +defm UBIT_INSERT : QuaternaryIntrinsicInt; +defm BFI : TernaryIntrinsicInt; +defm BFM : BinaryIntrinsicInt; +defm UMAD : TernaryIntrinsicInt; +defm UMAD24 : TernaryIntrinsicInt; +defm U4LERP : TernaryIntrinsicInt; +defm BITALIGN : TernaryIntrinsicInt; +defm BYTEALIGN : TernaryIntrinsicInt; +} +//===---------------------------------------------------------------------===// +// Signed 64bit integer math instructions start here +//===---------------------------------------------------------------------===// +// This opcode has custom swizzle pattern encoded in Swizzle Encoder +def LNEGATE : OneInOneOut; +// This opcode has custom swizzle pattern encoded in Swizzle Encoder +def LNEGATE_v2i64: OneInOneOut; +let Predicates = [HasHW64Bit] in { +def LADD : TwoInOneOut; +defm IMIN64 : BinaryIntrinsicLong; +defm UMIN64 : BinaryIntrinsicLong; +defm IMAX64 : BinaryIntrinsicLong; +defm UMAX64 : BinaryIntrinsicLong; +} +let Predicates = [HasHW64Bit] in { +def LSHR : TwoInOneOut; +def LSHL : TwoInOneOut; +} + + +//===---------------------------------------------------------------------===// +// Unsigned 64bit integer math instructions start here +//===---------------------------------------------------------------------===// +let Predicates = [HasTmrRegister] in { + def Tmr : ILFormat; +} +let Predicates = [HasDeviceIDInst] in { +def CU_ID : ILFormat; +def WAVE_ID : ILFormat; +} +let Predicates = [HasHW64Bit] in { +def LUSHR : TwoInOneOut; +} + + +//===---------------------------------------------------------------------===// +// Generic Float Instructions +//===---------------------------------------------------------------------===// +let hasIEEEFlag = 1 in { +defm MUL_IEEE : BinaryOpMCFloat; +} +defm ADD : BinaryOpMCFloat; +//===---------------------------------------------------------------------===// +// float math instructions start here +//===---------------------------------------------------------------------===// +let mayLoad=0, mayStore=0 in { +defm ABS : UnaryIntrinsicFloat; +defm FRAC : UnaryIntrinsicFloat; +defm PIREDUCE : UnaryIntrinsicFloat; +defm ROUND_NEAREST : UnaryIntrinsicFloat; +defm ROUND_NEGINF : UnaryIntrinsicFloat; +defm ROUND_POSINF : UnaryIntrinsicFloat; +defm ROUND_ZERO : UnaryIntrinsicFloat; +defm ACOS : UnaryIntrinsicFloatScalar; +defm ATAN : UnaryIntrinsicFloatScalar; +defm ASIN : UnaryIntrinsicFloatScalar; +defm TAN : UnaryIntrinsicFloatScalar; +defm SIN : UnaryIntrinsicFloatScalar; +defm COS : UnaryIntrinsicFloatScalar; +defm SQRT : UnaryIntrinsicFloatScalar; +defm EXP : UnaryIntrinsicFloatScalar; +defm EXPVEC : UnaryIntrinsicFloat; +defm SQRTVEC : UnaryIntrinsicFloat; +defm COSVEC : UnaryIntrinsicFloat; +defm SINVEC : UnaryIntrinsicFloat; +defm LOGVEC : UnaryIntrinsicFloat; +defm RSQVEC : UnaryIntrinsicFloat; +defm EXN : UnaryIntrinsicFloatScalar; +defm SIGN : UnaryIntrinsicFloat; +defm LENGTH : UnaryIntrinsicFloat; +defm POW : BinaryIntrinsicFloat; +} + +let hasIEEEFlag = 1 in { + let mayLoad = 0, mayStore=0 in { +defm MIN : BinaryIntrinsicFloat; +defm MAX : BinaryIntrinsicFloat; +defm MAD : TernaryIntrinsicFloat; + } +defm MOD : BinaryOpMCf32; +} +let hasZeroOpFlag = 1 in { + let mayLoad = 0, mayStore=0 in { +defm LN : UnaryIntrinsicFloatScalar; +defm LOG : UnaryIntrinsicFloatScalar; +defm RSQ : UnaryIntrinsicFloatScalar; +defm DIV : BinaryIntrinsicFloat; + } +} + let mayLoad = 0, mayStore=0 in { +defm CLAMP : TernaryIntrinsicFloat; +defm FMA : TernaryIntrinsicFloat; +defm LERP : TernaryIntrinsicFloat; + } +defm SUB : BinaryOpMCf32; +defm FABS : UnaryOpMCf32; +defm FMAD : TernaryOpMCf32; +defm NEAR : UnaryOpMCf32; +defm RND_Z : UnaryOpMCf32; + +// This opcode has custom swizzle pattern encoded in Swizzle Encoder +def NEG_f32 : OneInOneOut; +def INTTOANY_f32 : OneInOneOut; +let hasIEEEFlag = 1 in { +def DP2ADD_f32 : ThreeInOneOut; +def DP2_f32 : TwoInOneOut; +def DP3_f32 : TwoInOneOut; +def DP4_f32 : TwoInOneOut; +} +defm UNPACK_B0 : IntrConvertI32TOF32; +defm UNPACK_B1 : IntrConvertI32TOF32; +defm UNPACK_B2 : IntrConvertI32TOF32; +defm UNPACK_B3 : IntrConvertI32TOF32; +defm FTOI_FLR : IntrConvertF32TOI32; +defm FTOI_RPI : IntrConvertF32TOI32; +defm HTOF : IntrConvertF16TOF32; +defm FTOH : IntrConvertF32TOF16; +defm FTOH_NEAR : IntrConvertF32TOF16; +defm FTOH_NEG_INF : IntrConvertF32TOF16; +defm FTOH_PLUS_INF : IntrConvertF32TOF16; +//===---------------------------------------------------------------------===// +// float math instructions end here +//===---------------------------------------------------------------------===// + +//===---------------------------------------------------------------------===// +// float2 math instructions start here +//===---------------------------------------------------------------------===// +// This opcode has custom swizzle pattern encoded in Swizzle Encoder +def NEG_v2f32 : OneInOneOut; +//===---------------------------------------------------------------------===// +// float2 math instructions end here +//===---------------------------------------------------------------------===// + +//===---------------------------------------------------------------------===// +// float4 math instructions start here +//===---------------------------------------------------------------------===// +// This opcode has custom swizzle pattern encoded in Swizzle Encoder +def NEG_v4f32 : OneInOneOut; +//===---------------------------------------------------------------------===// +// float4 math instructions end here +//===---------------------------------------------------------------------===// + +//===---------------------------------------------------------------------===// +// double math instructions start here +//===---------------------------------------------------------------------===// +// This opcode has custom swizzle pattern encoded in Swizzle Encoder +def SUB_f64 : TwoInOneOut; +// This opcode has custom swizzle pattern encoded in Swizzle Encoder +def SUB_v2f64 : TwoInOneOut; +// This opcode has custom swizzle pattern encoded in Swizzle Encoder +def NEG_f64 : OneInOneOut; +// This opcode has custom swizzle pattern encoded in Swizzle Encoder +def NEG_v2f64 : OneInOneOut; + let mayLoad = 0, mayStore=0 in { +defm MIN : BinaryIntrinsicDouble; +defm MAX : BinaryIntrinsicDouble; +defm DIV : BinaryIntrinsicDouble; +defm MAD : TernaryIntrinsicDouble; +defm DFMA : TernaryIntrinsicDouble; +defm FRAC : UnaryIntrinsicDouble; +defm SQRT : UnaryIntrinsicDouble; +defm RSQ : UnaryIntrinsicDoubleScalar; +defm RCP : UnaryIntrinsicDoubleScalar; +defm DMAD : TernaryOpMCf64; + } +def FREXP_f64 : OneInOneOut; +def LDEXP_f64 : TwoInOneOut; +def LDEXP_v2f64 : TwoInOneOut; +//===---------------------------------------------------------------------===// +// double math instructions end here +//===---------------------------------------------------------------------===// + +//===---------------------------------------------------------------------===// +// Various Macros +//===---------------------------------------------------------------------===// +def MACRO__sdiv_i8 : BinaryMacro< GPRI8, GPRI8, GPRI8, sdiv>; +def MACRO__sdiv_i16 : BinaryMacro; +def MACRO__sdiv_i32 : BinaryMacro; +def MACRO__udiv_i8 : BinaryMacro< GPRI8, GPRI8, GPRI8, udiv>; +def MACRO__udiv_i16 : BinaryMacro; +def MACRO__udiv_i32 : BinaryMacro; +def MACRO__smod_i8 : BinaryMacro< GPRI8, GPRI8, GPRI8, srem>; +def MACRO__smod_i16 : BinaryMacro; +def MACRO__smod_i32 : BinaryMacro; +def MACRO__umod_i8 : BinaryMacro< GPRI8, GPRI8, GPRI8, urem>; +def MACRO__umod_i16 : BinaryMacro; +def MACRO__umod_i32 : BinaryMacro; +let Predicates = [HasSWDDiv] in { + def MACRO__ddiv_f64: BinaryMacro; +} +let Predicates = [HasHWDDiv] in { + def MACRO__ddiv_f64_fma: BinaryMacro; +} +def MACRO__ftol_i64 : UnaryMacro; +def MACRO__ftoul_i64 : UnaryMacro; +def MACRO__ultof_f32 : UnaryMacro; +def MACRO__ltof_f32 : UnaryMacro; +let Predicates = [HasSW64Mul] in { +def MACRO__mul_i64 : BinaryMacro; +def MACRO__mul_v2i64 : BinaryMacro; +} +let Predicates = [HasSW64DivMod] in { +def MACRO__sdiv_i64 : BinaryMacro; +def MACRO__udiv_i64 : BinaryMacro; +def MACRO__smod_i64 : BinaryMacro; +def MACRO__umod_i64 : BinaryMacro; +} +let Predicates = [HasHW64DivMod] in { + defm SDIV : BinaryOpMCi64; + defm UDIV : BinaryOpMCi64; + defm SMOD : BinaryOpMCi64; + defm UMOD : BinaryOpMCi64; +} +let Predicates = [HasHW64Mul] in { + defm SMUL : BinaryOpMCi64; + defm UMUL : BinaryOpMCi64; +} +def MACRO__shr_v2i64 : BinaryMacro; +def MACRO__shl_v2i64 : BinaryMacro; +def MACRO__sra_v2i64 : BinaryMacro; + +let Predicates = [HasSW64Bit] in { +def MACRO__shr_i64 : BinaryMacro; +def MACRO__shl_i64 : BinaryMacro; +def MACRO__sra_i64 : BinaryMacro; +} +//===---------------------------------------------------------------------===// +// Comparison Instructions +//===---------------------------------------------------------------------===// +let usesCustomInserter = 1 in { + defm CMP : Compare<"Pseudo comparison instr">; +} +//===---------------------------------------------------------------------===// +// 32-bit floating point operations +//===---------------------------------------------------------------------===// +def FEQ : TwoInOneOut; +def FGE : TwoInOneOut; +def FLT : TwoInOneOut; +def FLT_v2f32 : TwoInOneOut; +def FLT_v4f32 : TwoInOneOut; +def FNE : TwoInOneOut; + +//===---------------------------------------------------------------------===// +//TODO: need to correctly define comparison instructions +//===---------------------------------------------------------------------===// +def DEQ : TwoInOneOut; +def DEQ_v2f64 : TwoInOneOut; +def DGE : TwoInOneOut; +def DLT : TwoInOneOut; +def DNE : TwoInOneOut; + +//===---------------------------------------------------------------------===// +//TODO: need to correctly define comparison instructions +//===---------------------------------------------------------------------===// +def IEQ : TwoInOneOut; +def IEQ_v2i32 : TwoInOneOut; +def IEQ_v4i32 : TwoInOneOut; +def IGE : TwoInOneOut; +def IGE_v2i32 : TwoInOneOut; +def IGE_v4i32 : TwoInOneOut; +def ILT : TwoInOneOut; +def ILT_v2i32 : TwoInOneOut; +def ILT_v4i32 : TwoInOneOut; +def INE : TwoInOneOut; +def INE_v2i32 : TwoInOneOut; +def INE_v4i32 : TwoInOneOut; +let Predicates = [HasHW64Bit] in { +def LEQ : TwoInOneOut; +def LGE : TwoInOneOut; +def LLE : TwoInOneOut; +def LGT : TwoInOneOut; +def LLT : TwoInOneOut; +def LNE : TwoInOneOut; +} + +//===---------------------------------------------------------------------===// +// Unsigned Integer Operations +//===---------------------------------------------------------------------===// + +//===---------------------------------------------------------------------===// +//TODO: need to correctly define comparison instructions +//===---------------------------------------------------------------------===// +def UEQ : TwoInOneOut; +def UEQ_v2i32 : TwoInOneOut; +def UEQ_v4i32 : TwoInOneOut; +def ULE : TwoInOneOut; +def ULE_v2i32 : TwoInOneOut; +def ULE_v4i32 : TwoInOneOut; +def UGT : TwoInOneOut; +def UGT_v2i32 : TwoInOneOut; +def UGT_v4i32 : TwoInOneOut; +def UGE : TwoInOneOut; +def UGE_v2i32 : TwoInOneOut; +def UGE_v4i32 : TwoInOneOut; +def ULT : TwoInOneOut; +def ULT_v2i32 : TwoInOneOut; +def ULT_v4i32 : TwoInOneOut; +def UNE : TwoInOneOut; +def UNE_v2i32 : TwoInOneOut; +def UNE_v4i32 : TwoInOneOut; +let Predicates = [HasHW64Bit] in { +def ULLE : TwoInOneOut; +def ULGT : TwoInOneOut; +def ULGE : TwoInOneOut; +def ULLT : TwoInOneOut; +} +//===---------------------------------------------------------------------===// +// Scalar ==> Scalar conversion functions +//===---------------------------------------------------------------------===// +// f32 ==> f64 +def FTOD : UnaryOp; +// f64 ==> f32 +def DTOF : UnaryOp; +// f32 ==> i32 signed +def FTOI : UnaryOp; +def FTOI_v2i32 : UnaryOp; +def FTOI_v4i32 : UnaryOp; +// i32 ==> f32 signed +def ITOF : UnaryOp; +def ITOF_v2f32 : UnaryOp; +def ITOF_v4f32 : UnaryOp; +// f32 ==> i32 unsigned +def FTOU : UnaryOp; +def FTOU_v2i32 : UnaryOp; +def FTOU_v4i32 : UnaryOp; +// i32 ==> f32 unsigned +def UTOF : UnaryOp; +def UTOF_v2f32 : UnaryOp; +def UTOF_v4f32 : UnaryOp; +// Get upper 32 bits of f64 +// This opcode has custom swizzle pattern encoded in Swizzle Encoder +def DHI : OneInOneOut; +// This opcode has custom swizzle pattern encoded in Swizzle Encoder +def DHI_v2f64 : OneInOneOut; +// Get lower 32 bits of f64 +// This opcode has custom swizzle pattern encoded in Swizzle Encoder +def DLO : OneInOneOut; +// This opcode has custom swizzle pattern encoded in Swizzle Encoder +def DLO_v2f64 : OneInOneOut; +// Convert two 32 bit integers into a f64 +// This opcode has custom swizzle pattern encoded in Swizzle Encoder +def DCREATE : TwoInOneOut; +// This opcode has custom swizzle pattern encoded in Swizzle Encoder +def DCREATE_v2f64 : TwoInOneOut; +// Get upper 32 bits of i64 +// This opcode has custom swizzle pattern encoded in Swizzle Encoder +def LHI : OneInOneOut; +// This opcode has custom swizzle pattern encoded in Swizzle Encoder +def LHI_v2i64 : OneInOneOut; +// Get lower 32 bits of i64 +// This opcode has custom swizzle pattern encoded in Swizzle Encoder +def LLO : OneInOneOut; +// This opcode has custom swizzle pattern encoded in Swizzle Encoder +def LLO_v2i64 : OneInOneOut; +// This opcode has custom swizzle pattern encoded in Swizzle Encoder +def HILO_BITOR_v4i16 : TwoInOneOut; +// This opcode has custom swizzle pattern encoded in Swizzle Encoder +def HILO_BITOR_v2i32 : TwoInOneOut; +// This opcode has custom swizzle pattern encoded in Swizzle Encoder +def HILO_BITOR_v2i64 : TwoInOneOut; +// Convert two 32 bit integers into a i64 +// This opcode has custom swizzle pattern encoded in Swizzle Encoder +def LCREATE : TwoInOneOut; +// This opcode has custom swizzle pattern encoded in Swizzle Encoder +def LCREATE_v2i64 : TwoInOneOut; +//===---------------------------------------------------------------------===// +// Scalar ==> Vector conversion functions +//===---------------------------------------------------------------------===// +// This opcode has custom swizzle pattern encoded in Swizzle Encoder +defm VCREATE : UnaryOpMCVec; + +//===---------------------------------------------------------------------===// +// Vector ==> Scalar conversion functions +//===---------------------------------------------------------------------===// + +// This opcode has custom swizzle pattern encoded in Swizzle Encoder +defm VEXTRACT : VectorExtract; + +//===---------------------------------------------------------------------===// +// Vector ==> Vector conversion functions +//===---------------------------------------------------------------------===// +// This opcode has custom swizzle pattern encoded in Swizzle Encoder +defm VINSERT : VectorInsert; +// This opcode has custom swizzle pattern encoded in Swizzle Encoder +defm VCONCAT : VectorConcat; + +//===---------------------------------------------------------------------===// +// Bit conversion functions +//===---------------------------------------------------------------------===// +defm IL_ASCHAR : BitConversion; +defm IL_ASSHORT : BitConversion; +defm IL_ASINT : BitConversion; +defm IL_ASFLOAT : BitConversion; +defm IL_ASDOUBLE : BitConversion; +defm IL_ASLONG : BitConversion; +defm IL_ASV2CHAR : BitConversion; +defm IL_ASV2SHORT : BitConversion; +defm IL_ASV2INT : BitConversion; +defm IL_ASV2FLOAT : BitConversion; +defm IL_ASV2DOUBLE : BitConversion; +defm IL_ASV2LONG : BitConversion; +defm IL_ASV4CHAR : BitConversion; +defm IL_ASV4SHORT : BitConversion; +defm IL_ASV4INT : BitConversion; +defm IL_ASV4FLOAT : BitConversion; + +let Predicates = [Has32BitPtr] in { + let isCodeGenOnly=1 in { + //===----------------------------------------------------------------------===// + // Store Memory Operations + //===----------------------------------------------------------------------===// + defm GLOBALTRUNCSTORE : GTRUNCSTORE<"!global trunc store">; + defm GLOBALSTORE : STORE<"!global store" , global_store>; + defm LOCALTRUNCSTORE : LTRUNCSTORE<"!local trunc store">; + defm LOCALSTORE : STORE<"!local store" , local_store>; + defm PRIVATETRUNCSTORE : PTRUNCSTORE<"!private trunc store">; + defm PRIVATESTORE : STORE<"!private store" , private_store>; + defm REGIONTRUNCSTORE : RTRUNCSTORE<"!region trunc store">; + defm REGIONSTORE : STORE<"!region hw store" , region_store>; + + + //===---------------------------------------------------------------------===// + // Load Memory Operations + //===---------------------------------------------------------------------===// + defm GLOBALLOAD : LOAD<"!global load" , global_load>; + defm GLOBALZEXTLOAD : LOAD<"!global zext load" , global_zext_load>; + defm GLOBALSEXTLOAD : LOAD<"!global sext load" , global_sext_load>; + defm GLOBALAEXTLOAD : LOAD<"!global aext load" , global_aext_load>; + defm PRIVATELOAD : LOAD<"!private load" , private_load>; + defm PRIVATEZEXTLOAD : LOAD<"!private zext load" , private_zext_load>; + defm PRIVATESEXTLOAD : LOAD<"!private sext load" , private_sext_load>; + defm PRIVATEAEXTLOAD : LOAD<"!private aext load" , private_aext_load>; + defm CPOOLLOAD : LOAD<"!constant pool load" , cp_load>; + defm CPOOLZEXTLOAD : LOAD<"!constant pool zext load", cp_zext_load>; + defm CPOOLSEXTLOAD : LOAD<"!constant pool sext load", cp_sext_load>; + defm CPOOLAEXTLOAD : LOAD<"!constant aext pool load", cp_aext_load>; + defm CONSTANTLOAD : LOAD<"!constant load" , constant_load>; + defm CONSTANTZEXTLOAD : LOAD<"!constant zext load" , constant_zext_load>; + defm CONSTANTSEXTLOAD : LOAD<"!constant sext load" , constant_sext_load>; + defm CONSTANTAEXTLOAD : LOAD<"!constant aext load" , constant_aext_load>; + defm LOCALLOAD : LOAD<"!local load" , local_load>; + defm LOCALZEXTLOAD : LOAD<"!local zext load" , local_zext_load>; + defm LOCALSEXTLOAD : LOAD<"!local sext load" , local_sext_load>; + defm LOCALAEXTLOAD : LOAD<"!local aext load" , local_aext_load>; + defm REGIONLOAD : LOAD<"!region load" , region_load>; + defm REGIONZEXTLOAD : LOAD<"!region zext load" , region_zext_load>; + defm REGIONSEXTLOAD : LOAD<"!region sext load" , region_sext_load>; + defm REGIONAEXTLOAD : LOAD<"!region aext load" , region_aext_load>; + } + + + //===---------------------------------------------------------------------===// + // IO Expansion Load/Store Instructions + //===---------------------------------------------------------------------===// + let mayLoad = 1 in { + // This opcode has custom swizzle patterns for some of the arguments. + def SCRATCHLOAD : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def CBLOAD : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def GDSLOAD : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def GDSLOAD_Y : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def GDSLOAD_Z : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def GDSLOAD_W : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def LDSLOADVEC : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def LDSLOADVEC_v2i32 : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def LDSLOADVEC_v4i32 : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def LDSLOAD : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def LDSLOAD_i8 : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def LDSLOAD_u8 : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def LDSLOAD_i16 : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def LDSLOAD_u16 : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def LDSLOAD_Y : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def LDSLOAD_Z : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def LDSLOAD_W : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def UAVARENALOAD_i8 : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def UAVARENALOAD_i16 : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def UAVARENALOAD_i32 : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def UAVARENALOAD_Y_i32 : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def UAVARENALOAD_Z_i32 : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def UAVARENALOAD_W_i32 : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def UAVRAWLOAD_i32 : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def UAVRAWLOAD_v2i32 : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def UAVRAWLOAD_v4i32 : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def UAVRAWLOADCACHED_i32 : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def UAVRAWLOADCACHED_v2i32 : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def UAVRAWLOADCACHED_v4i32 : TwoInOneOut; + } + let mayStore = 1 in { + // This opcode has custom swizzle patterns for some of the arguments. + def SCRATCHSTORE : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def SCRATCHSTORE_X : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def SCRATCHSTORE_Y : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def SCRATCHSTORE_Z : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def SCRATCHSTORE_W : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def SCRATCHSTORE_XY : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def SCRATCHSTORE_ZW : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def GDSSTORE : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def GDSSTORE_Y : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def GDSSTORE_Z : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def GDSSTORE_W : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def LDSSTOREVEC : ThreeInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def LDSSTOREVEC_v2i32 : ThreeInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def LDSSTOREVEC_v4i32 : ThreeInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def LDSSTORE : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def LDSSTORE_i8 : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def LDSSTORE_i16 : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def LDSSTORE_Y : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def LDSSTORE_Z : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def LDSSTORE_W : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def UAVARENASTORE_i8 : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def UAVARENASTORE_i16 : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def UAVARENASTORE_i32 : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def UAVARENASTORE_Y_i32 : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def UAVARENASTORE_Z_i32 : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def UAVARENASTORE_W_i32 : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def UAVRAWSTORE_i32 : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def UAVRAWSTORE_v2i32 : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def UAVRAWSTORE_v4i32 : TwoInOneOut; + } +} +let Predicates = [Has64BitPtr] in { + let isCodeGenOnly=1 in { + //===----------------------------------------------------------------------===// + // Store Memory Operations + //===----------------------------------------------------------------------===// + defm GLOBALTRUNCSTORE64 : GTRUNCSTORE64<"!global trunc store">; + defm GLOBALSTORE64 : STORE64<"!global store" , global_store>; + defm LOCALTRUNCSTORE64 : LTRUNCSTORE64<"!local trunc store">; + defm LOCALSTORE64 : STORE64<"!local store" , local_store>; + defm PRIVATETRUNCSTORE64 : PTRUNCSTORE64<"!private trunc store">; + defm PRIVATESTORE64 : STORE64<"!private store" , private_store>; + defm REGIONTRUNCSTORE64 : RTRUNCSTORE64<"!region trunc store">; + defm REGIONSTORE64 : STORE64<"!region hw store" , region_store>; + + + //===---------------------------------------------------------------------===// + // Load Memory Operations + //===---------------------------------------------------------------------===// + defm GLOBALLOAD64 : LOAD64<"!global load" , global_load>; + defm GLOBALZEXTLOAD64 : LOAD64<"!global zext load" , global_zext_load>; + defm GLOBALSEXTLOAD64 : LOAD64<"!global sext load" , global_sext_load>; + defm GLOBALAEXTLOAD64 : LOAD64<"!global aext load" , global_aext_load>; + defm PRIVATELOAD64 : LOAD64<"!private load" , private_load>; + defm PRIVATEZEXTLOAD64 : LOAD64<"!private zext load" , private_zext_load>; + defm PRIVATESEXTLOAD64 : LOAD64<"!private sext load" , private_sext_load>; + defm PRIVATEAEXTLOAD64 : LOAD64<"!private aext load" , private_aext_load>; + defm CPOOLLOAD64 : LOAD64<"!constant pool load" , cp_load>; + defm CPOOLZEXTLOAD64 : LOAD64<"!constant pool zext load", cp_zext_load>; + defm CPOOLSEXTLOAD64 : LOAD64<"!constant pool sext load", cp_sext_load>; + defm CPOOLAEXTLOAD64 : LOAD64<"!constant aext pool load", cp_aext_load>; + defm CONSTANTLOAD64 : LOAD64<"!constant load" , constant_load>; + defm CONSTANTZEXTLOAD64 : LOAD64<"!constant zext load" , constant_zext_load>; + defm CONSTANTSEXTLOAD64 : LOAD64<"!constant sext load" , constant_sext_load>; + defm CONSTANTAEXTLOAD64 : LOAD64<"!constant aext load" , constant_aext_load>; + defm LOCALLOAD64 : LOAD64<"!local load" , local_load>; + defm LOCALZEXTLOAD64 : LOAD64<"!local zext load" , local_zext_load>; + defm LOCALSEXTLOAD64 : LOAD64<"!local sext load" , local_sext_load>; + defm LOCALAEXTLOAD64 : LOAD64<"!local aext load" , local_aext_load>; + defm REGIONLOAD64 : LOAD64<"!region load" , region_load>; + defm REGIONZEXTLOAD64 : LOAD64<"!region zext load" , region_zext_load>; + defm REGIONSEXTLOAD64 : LOAD64<"!region sext load" , region_sext_load>; + defm REGIONAEXTLOAD64 : LOAD64<"!region aext load" , region_aext_load>; + } + + + //===---------------------------------------------------------------------===// + // IO Expansion Load/Store Instructions + //===---------------------------------------------------------------------===// + let mayLoad = 1 in { + // This opcode has custom swizzle patterns for some of the arguments. + def SCRATCHLOAD64 : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def CBLOAD64 : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def GDSLOAD64 : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def GDSLOAD64_Y : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def GDSLOAD64_Z : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def GDSLOAD64_W : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def LDSLOADVEC64 : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def LDSLOADVEC64_v2i32 : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def LDSLOADVEC64_v4i32 : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def LDSLOAD64 : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def LDSLOAD64_i8 : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def LDSLOAD64_u8 : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def LDSLOAD64_i16 : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def LDSLOAD64_u16 : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def LDSLOAD64_Y : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def LDSLOAD64_Z : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def LDSLOAD64_W : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def UAVARENALOAD64_i8 : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def UAVARENALOAD64_i16 : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def UAVARENALOAD64_i32 : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def UAVARENALOAD64_Y_i32 : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def UAVARENALOAD64_Z_i32 : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def UAVARENALOAD64_W_i32 : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def UAVRAWLOAD64_i32 : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def UAVRAWLOAD64_v2i32 : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def UAVRAWLOAD64_v4i32 : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def UAVRAWLOADCACHED64_i32 : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def UAVRAWLOADCACHED64_v2i32 : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def UAVRAWLOADCACHED64_v4i32 : TwoInOneOut; + } + let mayStore = 1 in { + // This opcode has custom swizzle patterns for some of the arguments. + def SCRATCHSTORE64 : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def SCRATCHSTORE64_X : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def SCRATCHSTORE64_Y : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def SCRATCHSTORE64_Z : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def SCRATCHSTORE64_W : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def SCRATCHSTORE64_XY : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def SCRATCHSTORE64_ZW : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def GDSSTORE64 : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def GDSSTORE64_Y : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def GDSSTORE64_Z : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def GDSSTORE64_W : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def LDSSTOREVEC64 : ThreeInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def LDSSTOREVEC64_v2i32 : ThreeInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def LDSSTOREVEC64_v4i32 : ThreeInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def LDSSTORE64 : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def LDSSTORE64_i8 : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def LDSSTORE64_i16 : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def LDSSTORE64_Y : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def LDSSTORE64_Z : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def LDSSTORE64_W : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def UAVARENASTORE64_i8 : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def UAVARENASTORE64_i16 : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def UAVARENASTORE64_i32 : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def UAVARENASTORE64_Y_i32 : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def UAVARENASTORE64_Z_i32 : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def UAVARENASTORE64_W_i32 : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def UAVRAWSTORE64_i32 : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def UAVRAWSTORE64_v2i32 : TwoInOneOut; + // This opcode has custom swizzle patterns for some of the arguments. + def UAVRAWSTORE64_v4i32 : TwoInOneOut; + } +} +//===---------------------------------------------------------------------===// +// Custom Inserter for Branches and returns, this eventually will be a +// seperate pass +//===---------------------------------------------------------------------===// +let isTerminator = 1 in { + def BRANCH : ILFormat; + defm BRANCH_COND : BranchConditional; +} +//===---------------------------------------------------------------------===// +// return instructions +//===---------------------------------------------------------------------===// +let isTerminator = 1, isReturn = 1, isBarrier = 1, hasCtrlDep = 1 in { + def RETURN : ILFormat; +} +//===---------------------------------------------------------------------===// +// Lower and raise the stack x amount +//===---------------------------------------------------------------------===// +def ADJCALLSTACKDOWN : ILFormat; +def ADJCALLSTACKUP : ILFormat; + +//===---------------------------------------------------------------------===// +// Handle a function call +//===---------------------------------------------------------------------===// +let isCall = 1, + Defs = [ + R110, R111, + R112, R113, R114, R115, R116, R117, R118, R119, R120, R121, R122, R123, R124, + R125, R126, R127, + R128, R129, R130, R131, R132, R133, R134, R135, R136, R137, R138, R139, R140, + R141, R142, R143, + R144, R145, R146, R147, R148, R149, R150, R151, R152, R153, R154, R155, R156, + R157, R158, R159, + R160, R161, R162, R163, R164, R165, R166, R167, R168, R169, R170, R171, R172, + R173, R174, R175, + R176, R177, R178, R179, R180, R181, R182, R183, R184, R185, R186, R187, R188, + R189, R190, R191, + R192, R193, R194, R195, R196, R197, R198, R199, R200, R201, R202, R203, R204, + R205, R206, R207, + R208, R209, R210, R211, R212, R213, R214, R215, R216, R217, R218, R219, R220, + R221, R222, R223, + R224, R225, R226, R227, R228, R229, R230, R231, R232, R233, R234, R235, R236, + R237, R238, R239, + R240, R241, R242, R243, R244, R245, R246, R247, R248, R249, R250, R251, R252, + R253, R254, R255 + ] + , + Uses = [ + R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, + R16, R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, + R32, R33, R34, R35, R36, R37, R38, R39, R40, R41, R42, R43, R44, R45, R46, R47, + R48, R49, R50, R51, R52, R53, R54, R55, R56, R57, R58, R59, R60, R61, R62, R63, + R64, R65, R66, R67, R68, R69, R70, R71, R72, R73, R74, R75, R76, R77, R78, R79, + R80, R81, R82, R83, R84, R85, R86, R87, R88, R89, R90, R91, R92, R93, R94, R95, + R96, R97, R98, R99, R100, R101, R102, R103, R104, R105, R106, R107, R108, R109 + ] + in { + def CALL : UnaryOpNoRet; + } + + +//===---------------------------------------------------------------------===// +// Flow and Program control Instructions +//===---------------------------------------------------------------------===// +let isTerminator=1 in { + def SWITCH : ILFormat; + def CASE : ILFormat; + def BREAK : ILFormat; + def CONTINUE : ILFormat; + def DEFAULT : ILFormat; + def ELSE : ILFormat; + def ENDSWITCH : ILFormat; + def ENDMAIN : ILFormat; + def END : ILFormat; + def ENDFUNC : ILFormat; + def ENDIF : ILFormat; + def WHILELOOP : ILFormat; + def ENDLOOP : ILFormat; + def FUNC : ILFormat; + def RETDYN : ILFormat; + // This opcode has custom swizzle pattern encoded in Swizzle Encoder + defm IF_LOGICALNZ : BranchInstr; + // This opcode has custom swizzle pattern encoded in Swizzle Encoder + defm IF_LOGICALZ : BranchInstr; + // This opcode has custom swizzle pattern encoded in Swizzle Encoder + defm BREAK_LOGICALNZ : BranchInstr; + // This opcode has custom swizzle pattern encoded in Swizzle Encoder + defm BREAK_LOGICALZ : BranchInstr; + // This opcode has custom swizzle pattern encoded in Swizzle Encoder + defm CONTINUE_LOGICALNZ : BranchInstr; + // This opcode has custom swizzle pattern encoded in Swizzle Encoder + defm CONTINUE_LOGICALZ : BranchInstr; + defm IFC : BranchInstr2; + defm BREAKC : BranchInstr2; + defm CONTINUEC : BranchInstr2; +} +let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in { + def TRAP : ILFormat; +} + +//===---------------------------------------------------------------------===// +//----------------- Work Item Functions - OpenCL 6.11.1 ---------------------// +//===---------------------------------------------------------------------===// +let isCall = 1, isAsCheapAsAMove = 1 in { + def GET_WORK_DIM : ILFormat; + + def GET_GLOBAL_ID : ILFormat; + + def GET_LOCAL_ID : ILFormat; + + def GET_GROUP_ID : ILFormat; + + def GET_GLOBAL_SIZE : ILFormat; + + def GET_LOCAL_SIZE : ILFormat; + + def GET_NUM_GROUPS : ILFormat; + + def GET_GLOBAL_OFFSET : ILFormat; + + let Predicates = [Has64BitPtr] in { + def GET_PRINTF_OFFSET_i64: ILFormat; + def GET_PRINTF_SIZE_i64 : ILFormat; + } + let Predicates = [Has32BitPtr] in { + def GET_PRINTF_OFFSET_i32 : ILFormat; + def GET_PRINTF_SIZE_i32 : ILFormat; + } +} +//===---------------------------------------------------------------------===// +//------------- Synchronization Functions - OpenCL 6.11.9 -------------------// +//===---------------------------------------------------------------------===// +let isCall=1 in { + + def FENCE : BinaryOpNoRet; + + def FENCE_LOCAL : BinaryOpNoRet; + + def FENCE_GLOBAL : BinaryOpNoRet; + + def FENCE_REGION : BinaryOpNoRet; + + def FENCE_READ_ONLY : BinaryOpNoRet; + + def FENCE_READ_ONLY_LOCAL : BinaryOpNoRet; + + def FENCE_READ_ONLY_GLOBAL : BinaryOpNoRet; + + def FENCE_READ_ONLY_REGION : BinaryOpNoRet; + + def FENCE_WRITE_ONLY : BinaryOpNoRet; + + def FENCE_WRITE_ONLY_LOCAL : BinaryOpNoRet; + + def FENCE_WRITE_ONLY_GLOBAL : BinaryOpNoRet; + + def FENCE_WRITE_ONLY_REGION : BinaryOpNoRet; +} +let isReturn = 1 in { + def EARLY_EXIT : UnaryOpNoRet; +} +def MEDIA_UNPACK_0 : OneInOneOut; +def MEDIA_UNPACK_1 : OneInOneOut; +def MEDIA_UNPACK_2 : OneInOneOut; +def MEDIA_UNPACK_3 : OneInOneOut; +let Predicates = [Has32BitPtr] in { +// All of the image functions +def IMAGE1D_READ : ILFormat; +def IMAGE1DA_READ : ILFormat; +def IMAGE2D_READ : ILFormat; +def IMAGE2DA_READ : ILFormat; +def IMAGE3D_READ : ILFormat; +def IMAGE1D_READ_UNNORM : ILFormat; +def IMAGE1DA_READ_UNNORM : ILFormat; +def IMAGE2D_READ_UNNORM : ILFormat; +def IMAGE2DA_READ_UNNORM : ILFormat; +def IMAGE3D_READ_UNNORM : ILFormat; +def IMAGE1D_INFO0 : ILFormat; +def IMAGE1D_INFO1 : ILFormat; +def IMAGE1DA_INFO0 : ILFormat; +def IMAGE1DA_INFO1 : ILFormat; +def IMAGE2D_INFO0 : ILFormat; +def IMAGE2D_INFO1 : ILFormat; +def IMAGE2DA_INFO0 : ILFormat; +def IMAGE2DA_INFO1 : ILFormat; +def IMAGE3D_INFO0 : ILFormat; +def IMAGE3D_INFO1 : ILFormat; +def IMAGE1D_WRITE : ILFormat; +def IMAGE1DA_WRITE : ILFormat; +def IMAGE2D_WRITE : ILFormat; +def IMAGE2DA_WRITE : ILFormat; +def IMAGE3D_WRITE : ILFormat; +let hasSideEffects = 1, isNotDuplicable = 1 in { + // All of the noret atomic functions + def ATOM_G_ADD_NORET : BinAtomNoRet; + def ATOM_G_AND_NORET : BinAtomNoRet; + def ATOM_G_MAX_NORET : BinAtomNoRet; + def ATOM_G_MIN_NORET : BinAtomNoRet; + def ATOM_G_UMAX_NORET : BinAtomNoRet; + def ATOM_G_UMIN_NORET : BinAtomNoRet; + def ATOM_G_OR_NORET : BinAtomNoRet; + def ATOM_G_RSUB_NORET : BinAtomNoRet; + def ATOM_G_SUB_NORET : BinAtomNoRet; + def ATOM_G_XOR_NORET : BinAtomNoRet; + def ATOM_G_INC_NORET : BinAtomNoRet; + def ATOM_G_DEC_NORET : BinAtomNoRet; + def ATOM_G_CMPXCHG_NORET : CmpXChgNoRet; + def ATOM_A_ADD_NORET : BinAtomNoRet; + def ATOM_A_AND_NORET : BinAtomNoRet; + def ATOM_A_MAX_NORET : BinAtomNoRet; + def ATOM_A_MIN_NORET : BinAtomNoRet; + def ATOM_A_UMAX_NORET : BinAtomNoRet; + def ATOM_A_UMIN_NORET : BinAtomNoRet; + def ATOM_A_OR_NORET : BinAtomNoRet; + def ATOM_A_RSUB_NORET : BinAtomNoRet; + def ATOM_A_SUB_NORET : BinAtomNoRet; + def ATOM_A_XOR_NORET : BinAtomNoRet; + def ATOM_A_INC_NORET : BinAtomNoRet; + def ATOM_A_DEC_NORET : BinAtomNoRet; + def ATOM_A_CMPXCHG_NORET : CmpXChgNoRet; + def ATOM_L_ADD_NORET : BinAtomNoRet; + def ATOM_L_AND_NORET : BinAtomNoRet; + def ATOM_L_MAX_NORET : BinAtomNoRet; + def ATOM_L_MIN_NORET : BinAtomNoRet; + def ATOM_L_UMAX_NORET : BinAtomNoRet; + def ATOM_L_UMIN_NORET : BinAtomNoRet; + def ATOM_L_MSKOR_NORET : TriAtomNoRet; + def ATOM_L_OR_NORET : BinAtomNoRet; + def ATOM_L_RSUB_NORET : BinAtomNoRet; + def ATOM_L_SUB_NORET : BinAtomNoRet; + def ATOM_L_XOR_NORET : BinAtomNoRet; + def ATOM_L_INC_NORET : BinAtomNoRet; + def ATOM_L_DEC_NORET : BinAtomNoRet; + def ATOM_L_CMPXCHG_NORET : TriAtomNoRet; + def ATOM_R_ADD_NORET : BinAtomNoRet; + def ATOM_R_AND_NORET : BinAtomNoRet; + def ATOM_R_MAX_NORET : BinAtomNoRet; + def ATOM_R_MIN_NORET : BinAtomNoRet; + def ATOM_R_UMAX_NORET : BinAtomNoRet; + def ATOM_R_UMIN_NORET : BinAtomNoRet; + def ATOM_R_MSKOR_NORET : TriAtomNoRet; + def ATOM_R_OR_NORET : BinAtomNoRet; + def ATOM_R_RSUB_NORET : BinAtomNoRet; + def ATOM_R_SUB_NORET : BinAtomNoRet; + def ATOM_R_XOR_NORET : BinAtomNoRet; + def ATOM_R_INC_NORET : BinAtomNoRet; + def ATOM_R_DEC_NORET : BinAtomNoRet; + def ATOM_R_CMPXCHG_NORET : CmpXChgNoRet; + def APPEND_ALLOC_NORET : AppendNoRet; + def APPEND_CONSUME_NORET : AppendNoRet; + // All of the atomic functions that return + def ATOM_G_ADD : BinAtom; + def ATOM_G_AND : BinAtom; + def ATOM_G_MAX : BinAtom; + def ATOM_G_MIN : BinAtom; + def ATOM_G_UMAX : BinAtom; + def ATOM_G_UMIN : BinAtom; + def ATOM_G_OR : BinAtom; + def ATOM_G_RSUB : BinAtom; + def ATOM_G_SUB : BinAtom; + def ATOM_G_XOR : BinAtom; + def ATOM_G_INC : BinAtom; + def ATOM_G_DEC : BinAtom; + def ATOM_G_XCHG : BinAtom; + def ATOM_G_CMPXCHG : CmpXChg; + // Arena atomic accesses + def ATOM_A_ADD : BinAtom; + def ATOM_A_AND : BinAtom; + def ATOM_A_MAX : BinAtom; + def ATOM_A_MIN : BinAtom; + def ATOM_A_UMAX : BinAtom; + def ATOM_A_UMIN : BinAtom; + def ATOM_A_OR : BinAtom; + def ATOM_A_RSUB : BinAtom; + def ATOM_A_SUB : BinAtom; + def ATOM_A_XOR : BinAtom; + def ATOM_A_INC : BinAtom; + def ATOM_A_DEC : BinAtom; + def ATOM_A_XCHG : BinAtom; + def ATOM_A_CMPXCHG : CmpXChg; + def ATOM_L_ADD : BinAtom; + def ATOM_L_AND : BinAtom; + def ATOM_L_MAX : BinAtom; + def ATOM_L_MIN : BinAtom; + def ATOM_L_UMAX : BinAtom; + def ATOM_L_UMIN : BinAtom; + def ATOM_L_OR : BinAtom; + def ATOM_L_MSKOR : TriAtom; + def ATOM_L_RSUB : BinAtom; + def ATOM_L_SUB : BinAtom; + def ATOM_L_XOR : BinAtom; + def ATOM_L_INC : BinAtom; + def ATOM_L_DEC : BinAtom; + def ATOM_L_XCHG : BinAtom; + def ATOM_L_CMPXCHG : TriAtom; + def ATOM_R_ADD : BinAtom; + def ATOM_R_AND : BinAtom; + def ATOM_R_MAX : BinAtom; + def ATOM_R_MIN : BinAtom; + def ATOM_R_UMAX : BinAtom; + def ATOM_R_UMIN : BinAtom; + def ATOM_R_OR : BinAtom; + def ATOM_R_MSKOR : TriAtom; + def ATOM_R_RSUB : BinAtom; + def ATOM_R_SUB : BinAtom; + def ATOM_R_XOR : BinAtom; + def ATOM_R_INC : BinAtom; + def ATOM_R_DEC : BinAtom; + def ATOM_R_XCHG : BinAtom; + def ATOM_R_CMPXCHG : CmpXChg; + def APPEND_ALLOC : Append; + def APPEND_CONSUME : Append; +} +} +let Predicates = [Has64BitPtr] in { +// All of the image functions +def IMAGE1D64_READ : ILFormat; +def IMAGE1DA64_READ : ILFormat; +def IMAGE2D64_READ : ILFormat; +def IMAGE2DA64_READ : ILFormat; +def IMAGE3D64_READ : ILFormat; +def IMAGE1D64_READ_UNNORM : ILFormat; +def IMAGE1DA64_READ_UNNORM : ILFormat; +def IMAGE2D64_READ_UNNORM : ILFormat; +def IMAGE2DA64_READ_UNNORM : ILFormat; +def IMAGE3D64_READ_UNNORM : ILFormat; +def IMAGE1D64_INFO0 : ILFormat; +def IMAGE1D64_INFO1 : ILFormat; +def IMAGE1DA64_INFO0 : ILFormat; +def IMAGE1DA64_INFO1 : ILFormat; +def IMAGE2DA64_INFO0 : ILFormat; +def IMAGE2DA64_INFO1 : ILFormat; +def IMAGE2D64_INFO0 : ILFormat; +def IMAGE2D64_INFO1 : ILFormat; +def IMAGE3D64_INFO0 : ILFormat; +def IMAGE3D64_INFO1 : ILFormat; +def IMAGE1D64_WRITE : ILFormat; +def IMAGE1DA64_WRITE : ILFormat; +def IMAGE2D64_WRITE : ILFormat; +def IMAGE2DA64_WRITE : ILFormat; +def IMAGE3D64_WRITE : ILFormat; +let hasSideEffects= 1 in { + // All of the noret atomic functions + def ATOM_G64_ADD_NORET : BinAtomNoRet64; + def ATOM_G64_AND_NORET : BinAtomNoRet64; + def ATOM_G64_MAX_NORET : BinAtomNoRet64; + def ATOM_G64_MIN_NORET : BinAtomNoRet64; + def ATOM_G64_UMAX_NORET : BinAtomNoRet64; + def ATOM_G64_UMIN_NORET : BinAtomNoRet64; + def ATOM_G64_OR_NORET : BinAtomNoRet64; + def ATOM_G64_RSUB_NORET : BinAtomNoRet64; + def ATOM_G64_SUB_NORET : BinAtomNoRet64; + def ATOM_G64_XOR_NORET : BinAtomNoRet64; + def ATOM_G64_INC_NORET : BinAtomNoRet64; + def ATOM_G64_DEC_NORET : BinAtomNoRet64; + def ATOM_G64_CMPXCHG_NORET : CmpXChgNoRet64; + def ATOM_A64_ADD_NORET : BinAtomNoRet64; + def ATOM_A64_AND_NORET : BinAtomNoRet64; + def ATOM_A64_MAX_NORET : BinAtomNoRet64; + def ATOM_A64_MIN_NORET : BinAtomNoRet64; + def ATOM_A64_UMAX_NORET : BinAtomNoRet64; + def ATOM_A64_UMIN_NORET : BinAtomNoRet64; + def ATOM_A64_OR_NORET : BinAtomNoRet64; + def ATOM_A64_RSUB_NORET : BinAtomNoRet64; + def ATOM_A64_SUB_NORET : BinAtomNoRet64; + def ATOM_A64_XOR_NORET : BinAtomNoRet64; + def ATOM_A64_INC_NORET : BinAtomNoRet64; + def ATOM_A64_DEC_NORET : BinAtomNoRet64; + def ATOM_A64_CMPXCHG_NORET : CmpXChgNoRet64; + def ATOM_L64_ADD_NORET : BinAtomNoRet64; + def ATOM_L64_AND_NORET : BinAtomNoRet64; + def ATOM_L64_MAX_NORET : BinAtomNoRet64; + def ATOM_L64_MIN_NORET : BinAtomNoRet64; + def ATOM_L64_UMAX_NORET : BinAtomNoRet64; + def ATOM_L64_UMIN_NORET : BinAtomNoRet64; + def ATOM_L64_MSKOR_NORET : TriAtomNoRet64; + def ATOM_L64_OR_NORET : BinAtomNoRet64; + def ATOM_L64_RSUB_NORET : BinAtomNoRet64; + def ATOM_L64_SUB_NORET : BinAtomNoRet64; + def ATOM_L64_XOR_NORET : BinAtomNoRet64; + def ATOM_L64_INC_NORET : BinAtomNoRet64; + def ATOM_L64_DEC_NORET : BinAtomNoRet64; + def ATOM_L64_CMPXCHG_NORET : TriAtomNoRet64; + def ATOM_R64_ADD_NORET : BinAtomNoRet64; + def ATOM_R64_AND_NORET : BinAtomNoRet64; + def ATOM_R64_MAX_NORET : BinAtomNoRet64; + def ATOM_R64_MIN_NORET : BinAtomNoRet64; + def ATOM_R64_UMAX_NORET : BinAtomNoRet64; + def ATOM_R64_UMIN_NORET : BinAtomNoRet64; + def ATOM_R64_MSKOR_NORET : TriAtomNoRet64; + def ATOM_R64_OR_NORET : BinAtomNoRet64; + def ATOM_R64_RSUB_NORET : BinAtomNoRet64; + def ATOM_R64_SUB_NORET : BinAtomNoRet64; + def ATOM_R64_XOR_NORET : BinAtomNoRet64; + def ATOM_R64_INC_NORET : BinAtomNoRet64; + def ATOM_R64_DEC_NORET : BinAtomNoRet64; + def ATOM_R64_CMPXCHG_NORET : CmpXChgNoRet64; + def APPEND_ALLOC64_NORET : AppendNoRet64; + def APPEND_CONSUME64_NORET : AppendNoRet64; + // All of the atomic functions that return + def ATOM_G64_ADD : BinAtom64; + def ATOM_G64_AND : BinAtom64; + def ATOM_G64_MAX : BinAtom64; + def ATOM_G64_MIN : BinAtom64; + def ATOM_G64_UMAX : BinAtom64; + def ATOM_G64_UMIN : BinAtom64; + def ATOM_G64_OR : BinAtom64; + def ATOM_G64_RSUB : BinAtom64; + def ATOM_G64_SUB : BinAtom64; + def ATOM_G64_XOR : BinAtom64; + def ATOM_G64_INC : BinAtom64; + def ATOM_G64_DEC : BinAtom64; + def ATOM_G64_XCHG : BinAtom64; + def ATOM_G64_CMPXCHG : CmpXChg64; + // Arena atomic accesses + def ATOM_A64_ADD : BinAtom64; + def ATOM_A64_AND : BinAtom64; + def ATOM_A64_MAX : BinAtom64; + def ATOM_A64_MIN : BinAtom64; + def ATOM_A64_UMAX : BinAtom64; + def ATOM_A64_UMIN : BinAtom64; + def ATOM_A64_OR : BinAtom64; + def ATOM_A64_RSUB : BinAtom64; + def ATOM_A64_SUB : BinAtom64; + def ATOM_A64_XOR : BinAtom64; + def ATOM_A64_INC : BinAtom64; + def ATOM_A64_DEC : BinAtom64; + def ATOM_A64_XCHG : BinAtom64; + def ATOM_A64_CMPXCHG : CmpXChg64; + def ATOM_L64_ADD : BinAtom64; + def ATOM_L64_AND : BinAtom64; + def ATOM_L64_MAX : BinAtom64; + def ATOM_L64_MIN : BinAtom64; + def ATOM_L64_UMAX : BinAtom64; + def ATOM_L64_UMIN : BinAtom64; + def ATOM_L64_OR : BinAtom64; + def ATOM_L64_MSKOR : TriAtom64; + def ATOM_L64_RSUB : BinAtom64; + def ATOM_L64_SUB : BinAtom64; + def ATOM_L64_XOR : BinAtom64; + def ATOM_L64_INC : BinAtom64; + def ATOM_L64_DEC : BinAtom64; + def ATOM_L64_XCHG : BinAtom64; + def ATOM_L64_CMPXCHG : TriAtom64; + def ATOM_R64_ADD : BinAtom64; + def ATOM_R64_AND : BinAtom64; + def ATOM_R64_MAX : BinAtom64; + def ATOM_R64_MIN : BinAtom64; + def ATOM_R64_UMAX : BinAtom64; + def ATOM_R64_UMIN : BinAtom64; + def ATOM_R64_OR : BinAtom64; + def ATOM_R64_MSKOR : TriAtom64; + def ATOM_R64_RSUB : BinAtom64; + def ATOM_R64_SUB : BinAtom64; + def ATOM_R64_XOR : BinAtom64; + def ATOM_R64_INC : BinAtom64; + def ATOM_R64_DEC : BinAtom64; + def ATOM_R64_XCHG : BinAtom64; + def ATOM_R64_CMPXCHG : CmpXChg64; + def APPEND_ALLOC64 : Append64; + def APPEND_CONSUME64 : Append64; +} +} +/* +def SEMAPHORE_INIT : BinaryOpNoRet; + +def SEMAPHORE_WAIT : UnaryOpNoRet; + +def SEMAPHORE_SIGNAL : UnaryOpNoRet; +*/ diff --git a/lib/Target/AMDIL/AMDILIntrinsics.td b/lib/Target/AMDIL/AMDILIntrinsics.td new file mode 100644 index 00000000000..ef361f4e6af --- /dev/null +++ b/lib/Target/AMDIL/AMDILIntrinsics.td @@ -0,0 +1,705 @@ +//===- AMDILIntrinsics.td - Defines AMDIL Intrinscs -*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//==-----------------------------------------------------------------------===// +// +// This file defines all of the amdil-specific intrinsics +// +//===---------------------------------------------------------------===// + +let TargetPrefix = "AMDIL", isTarget = 1 in { +//------------- Synchronization Functions - OpenCL 6.11.9 --------------------// + def int_AMDIL_fence : GCCBuiltin<"mem_fence">, + UnaryIntNoRetInt; + def int_AMDIL_fence_global : GCCBuiltin<"mem_fence_global">, + UnaryIntNoRetInt; + def int_AMDIL_fence_local : GCCBuiltin<"mem_fence_local">, + UnaryIntNoRetInt; + def int_AMDIL_fence_region : GCCBuiltin<"mem_fence_region">, + UnaryIntNoRetInt; + def int_AMDIL_fence_read_only : GCCBuiltin<"read_mem_fence">, + UnaryIntNoRetInt; + def int_AMDIL_fence_read_only_global : GCCBuiltin<"read_mem_fence_global">, + UnaryIntNoRetInt; + def int_AMDIL_fence_read_only_local : GCCBuiltin<"read_mem_fence_local">, + UnaryIntNoRetInt; + def int_AMDIL_fence_read_only_region : GCCBuiltin<"read_mem_fence_region">, + UnaryIntNoRetInt; + def int_AMDIL_fence_write_only : GCCBuiltin<"write_mem_fence">, + UnaryIntNoRetInt; + def int_AMDIL_fence_write_only_global : GCCBuiltin<"write_mem_fence_global">, + UnaryIntNoRetInt; + def int_AMDIL_fence_write_only_local : GCCBuiltin<"write_mem_fence_local">, + UnaryIntNoRetInt; + def int_AMDIL_fence_write_only_region : GCCBuiltin<"write_mem_fence_region">, + UnaryIntNoRetInt; + + def int_AMDIL_early_exit : GCCBuiltin<"__amdil_early_exit">, + UnaryIntNoRetInt; + + def int_AMDIL_cmov_logical : GCCBuiltin<"__amdil_cmov_logical">, + TernaryIntInt; + def int_AMDIL_fabs : GCCBuiltin<"__amdil_fabs">, UnaryIntFloat; + def int_AMDIL_abs : GCCBuiltin<"__amdil_abs">, UnaryIntInt; + + def int_AMDIL_bit_extract_i32 : GCCBuiltin<"__amdil_ibit_extract">, + TernaryIntInt; + def int_AMDIL_bit_extract_u32 : GCCBuiltin<"__amdil_ubit_extract">, + TernaryIntInt; + def int_AMDIL_bit_reverse_u32 : GCCBuiltin<"__amdil_ubit_reverse">, + UnaryIntInt; + def int_AMDIL_bit_count_i32 : GCCBuiltin<"__amdil_count_bits">, + UnaryIntInt; + def int_AMDIL_bit_find_first_lo : GCCBuiltin<"__amdil_ffb_lo">, + UnaryIntInt; + def int_AMDIL_bit_find_first_hi : GCCBuiltin<"__amdil_ffb_hi">, + UnaryIntInt; + def int_AMDIL_bit_find_first_sgn : GCCBuiltin<"__amdil_ffb_signed">, + UnaryIntInt; + def int_AMDIL_media_bitalign : GCCBuiltin<"__amdil_bitalign">, + TernaryIntInt; + def int_AMDIL_media_bytealign : GCCBuiltin<"__amdil_bytealign">, + TernaryIntInt; + def int_AMDIL_bit_insert_u32 : GCCBuiltin<"__amdil_ubit_insert">, + QuaternaryIntInt; + def int_AMDIL_bfi : GCCBuiltin<"__amdil_bfi">, + TernaryIntInt; + def int_AMDIL_bfm : GCCBuiltin<"__amdil_bfm">, + BinaryIntInt; + def int_AMDIL_mad_i32 : GCCBuiltin<"__amdil_imad">, + TernaryIntInt; + def int_AMDIL_mad_u32 : GCCBuiltin<"__amdil_umad">, + TernaryIntInt; + def int_AMDIL_mad : GCCBuiltin<"__amdil_mad">, + TernaryIntFloat; + def int_AMDIL_mulhi_i32 : GCCBuiltin<"__amdil_imul_high">, + BinaryIntInt; + def int_AMDIL_mulhi_u32 : GCCBuiltin<"__amdil_umul_high">, + BinaryIntInt; + def int_AMDIL_mul24_i32 : GCCBuiltin<"__amdil_imul24">, + BinaryIntInt; + def int_AMDIL_mul24_u32 : GCCBuiltin<"__amdil_umul24">, + BinaryIntInt; + def int_AMDIL_mulhi24_i32 : GCCBuiltin<"__amdil_imul24_high">, + BinaryIntInt; + def int_AMDIL_mulhi24_u32 : GCCBuiltin<"__amdil_umul24_high">, + BinaryIntInt; + def int_AMDIL_mad24_i32 : GCCBuiltin<"__amdil_imad24">, + TernaryIntInt; + def int_AMDIL_mad24_u32 : GCCBuiltin<"__amdil_umad24">, + TernaryIntInt; + def int_AMDIL_carry_i32 : GCCBuiltin<"__amdil_carry">, + BinaryIntInt; + def int_AMDIL_borrow_i32 : GCCBuiltin<"__amdil_borrow">, + BinaryIntInt; + def int_AMDIL_min_i32 : GCCBuiltin<"__amdil_imin">, + BinaryIntInt; + def int_AMDIL_min_u32 : GCCBuiltin<"__amdil_umin">, + BinaryIntInt; + def int_AMDIL_min : GCCBuiltin<"__amdil_min">, + BinaryIntFloat; + def int_AMDIL_max_i32 : GCCBuiltin<"__amdil_imax">, + BinaryIntInt; + def int_AMDIL_max_u32 : GCCBuiltin<"__amdil_umax">, + BinaryIntInt; + def int_AMDIL_max : GCCBuiltin<"__amdil_max">, + BinaryIntFloat; + def int_AMDIL_media_lerp_u4 : GCCBuiltin<"__amdil_u4lerp">, + TernaryIntInt; + def int_AMDIL_media_sad : GCCBuiltin<"__amdil_sad">, + TernaryIntInt; + def int_AMDIL_media_sad_hi : GCCBuiltin<"__amdil_sadhi">, + TernaryIntInt; + def int_AMDIL_fraction : GCCBuiltin<"__amdil_fraction">, + UnaryIntFloat; + def int_AMDIL_clamp : GCCBuiltin<"__amdil_clamp">, + TernaryIntFloat; + def int_AMDIL_pireduce : GCCBuiltin<"__amdil_pireduce">, + UnaryIntFloat; + def int_AMDIL_round_nearest : GCCBuiltin<"__amdil_round_nearest">, + UnaryIntFloat; + def int_AMDIL_round_neginf : GCCBuiltin<"__amdil_round_neginf">, + UnaryIntFloat; + def int_AMDIL_round_posinf : GCCBuiltin<"__amdil_round_posinf">, + UnaryIntFloat; + def int_AMDIL_round_zero : GCCBuiltin<"__amdil_round_zero">, + UnaryIntFloat; + def int_AMDIL_acos : GCCBuiltin<"__amdil_acos">, + UnaryIntFloat; + def int_AMDIL_atan : GCCBuiltin<"__amdil_atan">, + UnaryIntFloat; + def int_AMDIL_asin : GCCBuiltin<"__amdil_asin">, + UnaryIntFloat; + def int_AMDIL_cos : GCCBuiltin<"__amdil_cos">, + UnaryIntFloat; + def int_AMDIL_cos_vec : GCCBuiltin<"__amdil_cos_vec">, + UnaryIntFloat; + def int_AMDIL_tan : GCCBuiltin<"__amdil_tan">, + UnaryIntFloat; + def int_AMDIL_sin : GCCBuiltin<"__amdil_sin">, + UnaryIntFloat; + def int_AMDIL_sin_vec : GCCBuiltin<"__amdil_sin_vec">, + UnaryIntFloat; + def int_AMDIL_pow : GCCBuiltin<"__amdil_pow">, BinaryIntFloat; + def int_AMDIL_div : GCCBuiltin<"__amdil_div">, BinaryIntFloat; + def int_AMDIL_udiv : GCCBuiltin<"__amdil_udiv">, BinaryIntInt; + def int_AMDIL_sqrt: GCCBuiltin<"__amdil_sqrt">, + UnaryIntFloat; + def int_AMDIL_sqrt_vec: GCCBuiltin<"__amdil_sqrt_vec">, + UnaryIntFloat; + def int_AMDIL_exp : GCCBuiltin<"__amdil_exp">, + UnaryIntFloat; + def int_AMDIL_exp_vec : GCCBuiltin<"__amdil_exp_vec">, + UnaryIntFloat; + def int_AMDIL_exn : GCCBuiltin<"__amdil_exn">, + UnaryIntFloat; + def int_AMDIL_log : GCCBuiltin<"__amdil_log">, + UnaryIntFloat; + def int_AMDIL_log_vec : GCCBuiltin<"__amdil_log_vec">, + UnaryIntFloat; + def int_AMDIL_ln : GCCBuiltin<"__amdil_ln">, + UnaryIntFloat; + def int_AMDIL_sign: GCCBuiltin<"__amdil_sign">, + UnaryIntFloat; + def int_AMDIL_fma: GCCBuiltin<"__amdil_fma">, + TernaryIntFloat; + def int_AMDIL_rsq : GCCBuiltin<"__amdil_rsq">, + UnaryIntFloat; + def int_AMDIL_rsq_vec : GCCBuiltin<"__amdil_rsq_vec">, + UnaryIntFloat; + def int_AMDIL_length : GCCBuiltin<"__amdil_length">, + UnaryIntFloat; + def int_AMDIL_lerp : GCCBuiltin<"__amdil_lerp">, + TernaryIntFloat; + def int_AMDIL_media_sad4 : GCCBuiltin<"__amdil_sad4">, + Intrinsic<[llvm_i32_ty], [llvm_v4i32_ty, + llvm_v4i32_ty, llvm_i32_ty], []>; + + def int_AMDIL_frexp_f64 : GCCBuiltin<"__amdil_frexp">, + Intrinsic<[llvm_v2i64_ty], [llvm_double_ty], []>; + def int_AMDIL_ldexp : GCCBuiltin<"__amdil_ldexp">, + Intrinsic<[llvm_anyfloat_ty], [llvm_anyfloat_ty, llvm_anyint_ty], []>; + def int_AMDIL_drcp : GCCBuiltin<"__amdil_rcp">, + Intrinsic<[llvm_double_ty], [llvm_double_ty], []>; + def int_AMDIL_convert_f16_f32 : GCCBuiltin<"__amdil_half_to_float">, + ConvertIntITOF; + def int_AMDIL_convert_f32_f16 : GCCBuiltin<"__amdil_float_to_half">, + ConvertIntFTOI; + def int_AMDIL_convert_f32_i32_rpi : GCCBuiltin<"__amdil_float_to_int_rpi">, + ConvertIntFTOI; + def int_AMDIL_convert_f32_i32_flr : GCCBuiltin<"__amdil_float_to_int_flr">, + ConvertIntFTOI; + def int_AMDIL_convert_f32_f16_near : GCCBuiltin<"__amdil_float_to_half_near">, + ConvertIntFTOI; + def int_AMDIL_convert_f32_f16_neg_inf : GCCBuiltin<"__amdil_float_to_half_neg_inf">, + ConvertIntFTOI; + def int_AMDIL_convert_f32_f16_plus_inf : GCCBuiltin<"__amdil_float_to_half_plus_inf">, + ConvertIntFTOI; + def int_AMDIL_media_convert_f2v4u8 : GCCBuiltin<"__amdil_f_2_u4">, + Intrinsic<[llvm_i32_ty], [llvm_v4f32_ty], []>; + def int_AMDIL_media_unpack_byte_0 : GCCBuiltin<"__amdil_unpack_0">, + ConvertIntITOF; + def int_AMDIL_media_unpack_byte_1 : GCCBuiltin<"__amdil_unpack_1">, + ConvertIntITOF; + def int_AMDIL_media_unpack_byte_2 : GCCBuiltin<"__amdil_unpack_2">, + ConvertIntITOF; + def int_AMDIL_media_unpack_byte_3 : GCCBuiltin<"__amdil_unpack_3">, + ConvertIntITOF; + def int_AMDIL_dp2_add : GCCBuiltin<"__amdil_dp2_add">, + Intrinsic<[llvm_float_ty], [llvm_v2f32_ty, + llvm_v2f32_ty, llvm_float_ty], []>; + def int_AMDIL_dp2 : GCCBuiltin<"__amdil_dp2">, + Intrinsic<[llvm_float_ty], [llvm_v2f32_ty, + llvm_v2f32_ty], []>; + def int_AMDIL_dp3 : GCCBuiltin<"__amdil_dp3">, + Intrinsic<[llvm_float_ty], [llvm_v4f32_ty, + llvm_v4f32_ty], []>; + def int_AMDIL_dp4 : GCCBuiltin<"__amdil_dp4">, + Intrinsic<[llvm_float_ty], [llvm_v4f32_ty, + llvm_v4f32_ty], []>; +//===---------------------- Image functions begin ------------------------===// + def int_AMDIL_image1d_write : GCCBuiltin<"__amdil_image1d_write">, + Intrinsic<[], [llvm_ptr_ty, llvm_v2i32_ty, llvm_v4i32_ty], [IntrReadWriteArgMem]>; + + def int_AMDIL_image1d_read_norm : GCCBuiltin<"__amdil_image1d_read_norm">, + Intrinsic<[llvm_v4i32_ty], [llvm_ptr_ty, llvm_i32_ty, llvm_v4f32_ty], [IntrReadWriteArgMem]>; + + def int_AMDIL_image1d_read_unnorm : GCCBuiltin<"__amdil_image1d_read_unnorm">, + Intrinsic<[llvm_v4i32_ty], [llvm_ptr_ty, llvm_i32_ty, llvm_v4f32_ty], [IntrReadWriteArgMem]>; + + def int_AMDIL_image1d_info0 : GCCBuiltin<"__amdil_image1d_info0">, + Intrinsic<[llvm_v4i32_ty], [llvm_ptr_ty], []>; + + def int_AMDIL_image1d_info1 : GCCBuiltin<"__amdil_image1d_info1">, + Intrinsic<[llvm_v4i32_ty], [llvm_ptr_ty], []>; + + def int_AMDIL_image1d_array_write : GCCBuiltin<"__amdil_image1d_array_write">, + Intrinsic<[], [llvm_ptr_ty, llvm_v2i32_ty, llvm_v4i32_ty], [IntrReadWriteArgMem]>; + + def int_AMDIL_image1d_array_read_norm : GCCBuiltin<"__amdil_image1d_array_read_norm">, + Intrinsic<[llvm_v4i32_ty], [llvm_ptr_ty, llvm_i32_ty, llvm_v4f32_ty], [IntrReadWriteArgMem]>; + + def int_AMDIL_image1d_array_read_unnorm : GCCBuiltin<"__amdil_image1d_array_read_unnorm">, + Intrinsic<[llvm_v4i32_ty], [llvm_ptr_ty, llvm_i32_ty, llvm_v4f32_ty], [IntrReadWriteArgMem]>; + + def int_AMDIL_image1d_array_info0 : GCCBuiltin<"__amdil_image1d_array_info0">, + Intrinsic<[llvm_v4i32_ty], [llvm_ptr_ty], []>; + + def int_AMDIL_image1d_array_info1 : GCCBuiltin<"__amdil_image1d_array_info1">, + Intrinsic<[llvm_v4i32_ty], [llvm_ptr_ty], []>; + + def int_AMDIL_image2d_write : GCCBuiltin<"__amdil_image2d_write">, + Intrinsic<[], [llvm_ptr_ty, llvm_v2i32_ty, llvm_v4i32_ty], [IntrReadWriteArgMem]>; + + def int_AMDIL_image2d_read_norm : GCCBuiltin<"__amdil_image2d_read_norm">, + Intrinsic<[llvm_v4i32_ty], [llvm_ptr_ty, llvm_i32_ty, llvm_v4f32_ty], [IntrReadWriteArgMem]>; + + def int_AMDIL_image2d_read_unnorm : GCCBuiltin<"__amdil_image2d_read_unnorm">, + Intrinsic<[llvm_v4i32_ty], [llvm_ptr_ty, llvm_i32_ty, llvm_v4f32_ty], [IntrReadWriteArgMem]>; + + def int_AMDIL_image2d_info0 : GCCBuiltin<"__amdil_image2d_info0">, + Intrinsic<[llvm_v4i32_ty], [llvm_ptr_ty], []>; + + def int_AMDIL_image2d_info1 : GCCBuiltin<"__amdil_image2d_info1">, + Intrinsic<[llvm_v4i32_ty], [llvm_ptr_ty], []>; + + def int_AMDIL_image2d_array_write : GCCBuiltin<"__amdil_image2d_array_write">, + Intrinsic<[], [llvm_ptr_ty, llvm_v2i32_ty, llvm_v4i32_ty], [IntrReadWriteArgMem]>; + + def int_AMDIL_image2d_array_read_norm : GCCBuiltin<"__amdil_image2d_array_read_norm">, + Intrinsic<[llvm_v4i32_ty], [llvm_ptr_ty, llvm_i32_ty, llvm_v4f32_ty], [IntrReadWriteArgMem]>; + + def int_AMDIL_image2d_array_read_unnorm : GCCBuiltin<"__amdil_image2d_array_read_unnorm">, + Intrinsic<[llvm_v4i32_ty], [llvm_ptr_ty, llvm_i32_ty, llvm_v4f32_ty], [IntrReadWriteArgMem]>; + + def int_AMDIL_image2d_array_info0 : GCCBuiltin<"__amdil_image2d_array_info0">, + Intrinsic<[llvm_v4i32_ty], [llvm_ptr_ty], []>; + + def int_AMDIL_image2d_array_info1 : GCCBuiltin<"__amdil_image2d_array_info1">, + Intrinsic<[llvm_v4i32_ty], [llvm_ptr_ty], []>; + + def int_AMDIL_image3d_write : GCCBuiltin<"__amdil_image3d_write">, + Intrinsic<[], [llvm_ptr_ty, llvm_v4i32_ty, llvm_v4i32_ty], [IntrReadWriteArgMem]>; + + def int_AMDIL_image3d_read_norm : GCCBuiltin<"__amdil_image3d_read_norm">, + Intrinsic<[llvm_v4i32_ty], [llvm_ptr_ty, llvm_i32_ty, llvm_v4f32_ty], [IntrReadWriteArgMem]>; + + def int_AMDIL_image3d_read_unnorm : GCCBuiltin<"__amdil_image3d_read_unnorm">, + Intrinsic<[llvm_v4i32_ty], [llvm_ptr_ty, llvm_i32_ty, llvm_v4f32_ty], [IntrReadWriteArgMem]>; + + def int_AMDIL_image3d_info0 : GCCBuiltin<"__amdil_image3d_info0">, + Intrinsic<[llvm_v4i32_ty], [llvm_ptr_ty], []>; + + def int_AMDIL_image3d_info1 : GCCBuiltin<"__amdil_image3d_info1">, + Intrinsic<[llvm_v4i32_ty], [llvm_ptr_ty], []>; + +//===---------------------- Image functions end --------------------------===// + + def int_AMDIL_append_alloc_i32 : GCCBuiltin<"__amdil_append_alloc">, + Intrinsic<[llvm_i32_ty], [llvm_ptr_ty], [IntrReadWriteArgMem]>; + def int_AMDIL_append_consume_i32 : GCCBuiltin<"__amdil_append_consume">, + Intrinsic<[llvm_i32_ty], [llvm_ptr_ty], [IntrReadWriteArgMem]>; + def int_AMDIL_append_alloc_i32_noret : GCCBuiltin<"__amdil_append_alloc_noret">, + Intrinsic<[llvm_i32_ty], [llvm_ptr_ty], [IntrReadWriteArgMem]>; + def int_AMDIL_append_consume_i32_noret : GCCBuiltin<"__amdil_append_consume_noret">, + Intrinsic<[llvm_i32_ty], [llvm_ptr_ty], [IntrReadWriteArgMem]>; + + def int_AMDIL_get_global_id : GCCBuiltin<"__amdil_get_global_id_int">, + Intrinsic<[llvm_v4i32_ty], [], []>; + def int_AMDIL_get_local_id : GCCBuiltin<"__amdil_get_local_id_int">, + Intrinsic<[llvm_v4i32_ty], [], []>; + def int_AMDIL_get_group_id : GCCBuiltin<"__amdil_get_group_id_int">, + Intrinsic<[llvm_v4i32_ty], [], []>; + def int_AMDIL_get_num_groups : GCCBuiltin<"__amdil_get_num_groups_int">, + Intrinsic<[llvm_v4i32_ty], [], []>; + def int_AMDIL_get_local_size : GCCBuiltin<"__amdil_get_local_size_int">, + Intrinsic<[llvm_v4i32_ty], [], []>; + def int_AMDIL_get_global_size : GCCBuiltin<"__amdil_get_global_size_int">, + Intrinsic<[llvm_v4i32_ty], [], []>; + def int_AMDIL_get_global_offset : GCCBuiltin<"__amdil_get_global_offset_int">, + Intrinsic<[llvm_v4i32_ty], [], []>; + def int_AMDIL_get_work_dim : GCCBuiltin<"get_work_dim">, + Intrinsic<[llvm_i32_ty], [], []>; + def int_AMDIL_get_printf_offset : GCCBuiltin<"__amdil_get_printf_offset">, + Intrinsic<[llvm_i32_ty], []>; + def int_AMDIL_get_printf_size : GCCBuiltin<"__amdil_get_printf_size">, + Intrinsic<[llvm_i32_ty], []>; + +/// Intrinsics for atomic instructions with no return value +/// Signed 32 bit integer atomics for global address space +def int_AMDIL_atomic_add_gi32_noret : GCCBuiltin<"__atomic_add_gi32_noret">, + BinaryAtomicIntNoRet; +def int_AMDIL_atomic_sub_gi32_noret : GCCBuiltin<"__atomic_sub_gi32_noret">, + BinaryAtomicIntNoRet; +def int_AMDIL_atomic_rsub_gi32_noret : GCCBuiltin<"__atomic_rsub_gi32_noret">, + BinaryAtomicIntNoRet; +def int_AMDIL_atomic_xchg_gi32_noret : GCCBuiltin<"__atomic_xchg_gi32_noret">, + BinaryAtomicIntNoRet; +def int_AMDIL_atomic_inc_gi32_noret : GCCBuiltin<"__atomic_inc_gi32_noret">, + BinaryAtomicIntNoRet; +def int_AMDIL_atomic_dec_gi32_noret : GCCBuiltin<"__atomic_dec_gi32_noret">, + BinaryAtomicIntNoRet; +def int_AMDIL_atomic_cmpxchg_gi32_noret : GCCBuiltin<"__atomic_cmpxchg_gi32_noret">, + TernaryAtomicIntNoRet; +def int_AMDIL_atomic_min_gi32_noret : GCCBuiltin<"__atomic_min_gi32_noret">, + BinaryAtomicIntNoRet; +def int_AMDIL_atomic_max_gi32_noret : GCCBuiltin<"__atomic_max_gi32_noret">, + BinaryAtomicIntNoRet; +def int_AMDIL_atomic_and_gi32_noret : GCCBuiltin<"__atomic_and_gi32_noret">, + BinaryAtomicIntNoRet; +def int_AMDIL_atomic_or_gi32_noret : GCCBuiltin<"__atomic_or_gi32_noret">, + BinaryAtomicIntNoRet; +def int_AMDIL_atomic_xor_gi32_noret : GCCBuiltin<"__atomic_xor_gi32_noret">, + BinaryAtomicIntNoRet; + + + +/// Unsigned 32 bit integer atomics for global address space +def int_AMDIL_atomic_add_gu32_noret : GCCBuiltin<"__atomic_add_gu32_noret">, + BinaryAtomicIntNoRet; +def int_AMDIL_atomic_sub_gu32_noret : GCCBuiltin<"__atomic_sub_gu32_noret">, + BinaryAtomicIntNoRet; +def int_AMDIL_atomic_rsub_gu32_noret : GCCBuiltin<"__atomic_rsub_gu32_noret">, + BinaryAtomicIntNoRet; +def int_AMDIL_atomic_xchg_gu32_noret : GCCBuiltin<"__atomic_xchg_gu32_noret">, + BinaryAtomicIntNoRet; +def int_AMDIL_atomic_inc_gu32_noret : GCCBuiltin<"__atomic_inc_gu32_noret">, + BinaryAtomicIntNoRet; +def int_AMDIL_atomic_dec_gu32_noret : GCCBuiltin<"__atomic_dec_gu32_noret">, + BinaryAtomicIntNoRet; +def int_AMDIL_atomic_cmpxchg_gu32_noret : GCCBuiltin<"__atomic_cmpxchg_gu32_noret">, + TernaryAtomicIntNoRet; +def int_AMDIL_atomic_min_gu32_noret : GCCBuiltin<"__atomic_min_gu32_noret">, + BinaryAtomicIntNoRet; +def int_AMDIL_atomic_max_gu32_noret : GCCBuiltin<"__atomic_max_gu32_noret">, + BinaryAtomicIntNoRet; +def int_AMDIL_atomic_and_gu32_noret : GCCBuiltin<"__atomic_and_gu32_noret">, + BinaryAtomicIntNoRet; +def int_AMDIL_atomic_or_gu32_noret : GCCBuiltin<"__atomic_or_gu32_noret">, + BinaryAtomicIntNoRet; +def int_AMDIL_atomic_xor_gu32_noret : GCCBuiltin<"__atomic_xor_gu32_noret">, + BinaryAtomicIntNoRet; + + +/// Intrinsics for atomic instructions with a return value +/// Signed 32 bit integer atomics for global address space +def int_AMDIL_atomic_add_gi32 : GCCBuiltin<"__atomic_add_gi32">, + BinaryAtomicInt; +def int_AMDIL_atomic_sub_gi32 : GCCBuiltin<"__atomic_sub_gi32">, + BinaryAtomicInt; +def int_AMDIL_atomic_rsub_gi32 : GCCBuiltin<"__atomic_rsub_gi32">, + BinaryAtomicInt; +def int_AMDIL_atomic_xchg_gi32 : GCCBuiltin<"__atomic_xchg_gi32">, + BinaryAtomicInt; +def int_AMDIL_atomic_inc_gi32 : GCCBuiltin<"__atomic_inc_gi32">, + BinaryAtomicInt; +def int_AMDIL_atomic_dec_gi32 : GCCBuiltin<"__atomic_dec_gi32">, + BinaryAtomicInt; +def int_AMDIL_atomic_cmpxchg_gi32 : GCCBuiltin<"__atomic_cmpxchg_gi32">, + TernaryAtomicInt; +def int_AMDIL_atomic_min_gi32 : GCCBuiltin<"__atomic_min_gi32">, + BinaryAtomicInt; +def int_AMDIL_atomic_max_gi32 : GCCBuiltin<"__atomic_max_gi32">, + BinaryAtomicInt; +def int_AMDIL_atomic_and_gi32 : GCCBuiltin<"__atomic_and_gi32">, + BinaryAtomicInt; +def int_AMDIL_atomic_or_gi32 : GCCBuiltin<"__atomic_or_gi32">, + BinaryAtomicInt; +def int_AMDIL_atomic_xor_gi32 : GCCBuiltin<"__atomic_xor_gi32">, + BinaryAtomicInt; + +/// 32 bit float atomics required by OpenCL +def int_AMDIL_atomic_xchg_gf32 : GCCBuiltin<"__atomic_xchg_gf32">, + BinaryAtomicInt; +def int_AMDIL_atomic_xchg_gf32_noret : GCCBuiltin<"__atomic_xchg_gf32_noret">, + BinaryAtomicIntNoRet; + +/// Unsigned 32 bit integer atomics for global address space +def int_AMDIL_atomic_add_gu32 : GCCBuiltin<"__atomic_add_gu32">, + BinaryAtomicInt; +def int_AMDIL_atomic_sub_gu32 : GCCBuiltin<"__atomic_sub_gu32">, + BinaryAtomicInt; +def int_AMDIL_atomic_rsub_gu32 : GCCBuiltin<"__atomic_rsub_gu32">, + BinaryAtomicInt; +def int_AMDIL_atomic_xchg_gu32 : GCCBuiltin<"__atomic_xchg_gu32">, + BinaryAtomicInt; +def int_AMDIL_atomic_inc_gu32 : GCCBuiltin<"__atomic_inc_gu32">, + BinaryAtomicInt; +def int_AMDIL_atomic_dec_gu32 : GCCBuiltin<"__atomic_dec_gu32">, + BinaryAtomicInt; +def int_AMDIL_atomic_cmpxchg_gu32 : GCCBuiltin<"__atomic_cmpxchg_gu32">, + TernaryAtomicInt; +def int_AMDIL_atomic_min_gu32 : GCCBuiltin<"__atomic_min_gu32">, + BinaryAtomicInt; +def int_AMDIL_atomic_max_gu32 : GCCBuiltin<"__atomic_max_gu32">, + BinaryAtomicInt; +def int_AMDIL_atomic_and_gu32 : GCCBuiltin<"__atomic_and_gu32">, + BinaryAtomicInt; +def int_AMDIL_atomic_or_gu32 : GCCBuiltin<"__atomic_or_gu32">, + BinaryAtomicInt; +def int_AMDIL_atomic_xor_gu32 : GCCBuiltin<"__atomic_xor_gu32">, + BinaryAtomicInt; + + +/// Intrinsics for atomic instructions with no return value +/// Signed 32 bit integer atomics for local address space +def int_AMDIL_atomic_add_li32_noret : GCCBuiltin<"__atomic_add_li32_noret">, + BinaryAtomicIntNoRet; +def int_AMDIL_atomic_sub_li32_noret : GCCBuiltin<"__atomic_sub_li32_noret">, + BinaryAtomicIntNoRet; +def int_AMDIL_atomic_rsub_li32_noret : GCCBuiltin<"__atomic_rsub_li32_noret">, + BinaryAtomicIntNoRet; +def int_AMDIL_atomic_xchg_li32_noret : GCCBuiltin<"__atomic_xchg_li32_noret">, + BinaryAtomicIntNoRet; +def int_AMDIL_atomic_inc_li32_noret : GCCBuiltin<"__atomic_inc_li32_noret">, + BinaryAtomicIntNoRet; +def int_AMDIL_atomic_dec_li32_noret : GCCBuiltin<"__atomic_dec_li32_noret">, + BinaryAtomicIntNoRet; +def int_AMDIL_atomic_cmpxchg_li32_noret : GCCBuiltin<"__atomic_cmpxchg_li32_noret">, + TernaryAtomicIntNoRet; +def int_AMDIL_atomic_min_li32_noret : GCCBuiltin<"__atomic_min_li32_noret">, + BinaryAtomicIntNoRet; +def int_AMDIL_atomic_max_li32_noret : GCCBuiltin<"__atomic_max_li32_noret">, + BinaryAtomicIntNoRet; +def int_AMDIL_atomic_and_li32_noret : GCCBuiltin<"__atomic_and_li32_noret">, + BinaryAtomicIntNoRet; +def int_AMDIL_atomic_or_li32_noret : GCCBuiltin<"__atomic_or_li32_noret">, + BinaryAtomicIntNoRet; +def int_AMDIL_atomic_mskor_li32_noret : GCCBuiltin<"__atomic_mskor_li32_noret">, + TernaryAtomicIntNoRet; +def int_AMDIL_atomic_xor_li32_noret : GCCBuiltin<"__atomic_xor_li32_noret">, + BinaryAtomicIntNoRet; + +/// Signed 32 bit integer atomics for region address space +def int_AMDIL_atomic_add_ri32_noret : GCCBuiltin<"__atomic_add_ri32_noret">, + BinaryAtomicIntNoRet; +def int_AMDIL_atomic_sub_ri32_noret : GCCBuiltin<"__atomic_sub_ri32_noret">, + BinaryAtomicIntNoRet; +def int_AMDIL_atomic_rsub_ri32_noret : GCCBuiltin<"__atomic_rsub_ri32_noret">, + BinaryAtomicIntNoRet; +def int_AMDIL_atomic_xchg_ri32_noret : GCCBuiltin<"__atomic_xchg_ri32_noret">, + BinaryAtomicIntNoRet; +def int_AMDIL_atomic_inc_ri32_noret : GCCBuiltin<"__atomic_inc_ri32_noret">, + BinaryAtomicIntNoRet; +def int_AMDIL_atomic_dec_ri32_noret : GCCBuiltin<"__atomic_dec_ri32_noret">, + BinaryAtomicIntNoRet; +def int_AMDIL_atomic_cmpxchg_ri32_noret : GCCBuiltin<"__atomic_cmpxchg_ri32_noret">, + TernaryAtomicIntNoRet; +def int_AMDIL_atomic_min_ri32_noret : GCCBuiltin<"__atomic_min_ri32_noret">, + BinaryAtomicIntNoRet; +def int_AMDIL_atomic_max_ri32_noret : GCCBuiltin<"__atomic_max_ri32_noret">, + BinaryAtomicIntNoRet; +def int_AMDIL_atomic_and_ri32_noret : GCCBuiltin<"__atomic_and_ri32_noret">, + BinaryAtomicIntNoRet; +def int_AMDIL_atomic_or_ri32_noret : GCCBuiltin<"__atomic_or_ri32_noret">, + BinaryAtomicIntNoRet; +def int_AMDIL_atomic_mskor_ri32_noret : GCCBuiltin<"__atomic_mskor_ri32_noret">, + TernaryAtomicIntNoRet; +def int_AMDIL_atomic_xor_ri32_noret : GCCBuiltin<"__atomic_xor_ri32_noret">, + BinaryAtomicIntNoRet; + + + +/// Unsigned 32 bit integer atomics for local address space +def int_AMDIL_atomic_add_lu32_noret : GCCBuiltin<"__atomic_add_lu32_noret">, + BinaryAtomicIntNoRet; +def int_AMDIL_atomic_sub_lu32_noret : GCCBuiltin<"__atomic_sub_lu32_noret">, + BinaryAtomicIntNoRet; +def int_AMDIL_atomic_rsub_lu32_noret : GCCBuiltin<"__atomic_rsub_lu32_noret">, + BinaryAtomicIntNoRet; +def int_AMDIL_atomic_xchg_lu32_noret : GCCBuiltin<"__atomic_xchg_lu32_noret">, + BinaryAtomicIntNoRet; +def int_AMDIL_atomic_inc_lu32_noret : GCCBuiltin<"__atomic_inc_lu32_noret">, + BinaryAtomicIntNoRet; +def int_AMDIL_atomic_dec_lu32_noret : GCCBuiltin<"__atomic_dec_lu32_noret">, + BinaryAtomicIntNoRet; +def int_AMDIL_atomic_cmpxchg_lu32_noret : GCCBuiltin<"__atomic_cmpxchg_lu32_noret">, + TernaryAtomicIntNoRet; +def int_AMDIL_atomic_min_lu32_noret : GCCBuiltin<"__atomic_min_lu32_noret">, + BinaryAtomicIntNoRet; +def int_AMDIL_atomic_max_lu32_noret : GCCBuiltin<"__atomic_max_lu32_noret">, + BinaryAtomicIntNoRet; +def int_AMDIL_atomic_and_lu32_noret : GCCBuiltin<"__atomic_and_lu32_noret">, + BinaryAtomicIntNoRet; +def int_AMDIL_atomic_or_lu32_noret : GCCBuiltin<"__atomic_or_lu32_noret">, + BinaryAtomicIntNoRet; +def int_AMDIL_atomic_mskor_lu32_noret : GCCBuiltin<"__atomic_mskor_lu32_noret">, + TernaryAtomicIntNoRet; +def int_AMDIL_atomic_xor_lu32_noret : GCCBuiltin<"__atomic_xor_lu32_noret">, + BinaryAtomicIntNoRet; + +/// Unsigned 32 bit integer atomics for region address space +def int_AMDIL_atomic_add_ru32_noret : GCCBuiltin<"__atomic_add_ru32_noret">, + BinaryAtomicIntNoRet; +def int_AMDIL_atomic_sub_ru32_noret : GCCBuiltin<"__atomic_sub_ru32_noret">, + BinaryAtomicIntNoRet; +def int_AMDIL_atomic_rsub_ru32_noret : GCCBuiltin<"__atomic_rsub_ru32_noret">, + BinaryAtomicIntNoRet; +def int_AMDIL_atomic_xchg_ru32_noret : GCCBuiltin<"__atomic_xchg_ru32_noret">, + BinaryAtomicIntNoRet; +def int_AMDIL_atomic_inc_ru32_noret : GCCBuiltin<"__atomic_inc_ru32_noret">, + BinaryAtomicIntNoRet; +def int_AMDIL_atomic_dec_ru32_noret : GCCBuiltin<"__atomic_dec_ru32_noret">, + BinaryAtomicIntNoRet; +def int_AMDIL_atomic_cmpxchg_ru32_noret : GCCBuiltin<"__atomic_cmpxchg_ru32_noret">, + TernaryAtomicIntNoRet; +def int_AMDIL_atomic_min_ru32_noret : GCCBuiltin<"__atomic_min_ru32_noret">, + BinaryAtomicIntNoRet; +def int_AMDIL_atomic_max_ru32_noret : GCCBuiltin<"__atomic_max_ru32_noret">, + BinaryAtomicIntNoRet; +def int_AMDIL_atomic_and_ru32_noret : GCCBuiltin<"__atomic_and_ru32_noret">, + BinaryAtomicIntNoRet; +def int_AMDIL_atomic_or_ru32_noret : GCCBuiltin<"__atomic_or_ru32_noret">, + BinaryAtomicIntNoRet; +def int_AMDIL_atomic_mskor_ru32_noret : GCCBuiltin<"__atomic_mskor_ru32_noret">, + TernaryAtomicIntNoRet; +def int_AMDIL_atomic_xor_ru32_noret : GCCBuiltin<"__atomic_xor_ru32_noret">, + BinaryAtomicIntNoRet; + +def int_AMDIL_get_cycle_count : GCCBuiltin<"__amdil_get_cycle_count">, + VoidIntLong; + +def int_AMDIL_compute_unit_id : GCCBuiltin<"__amdil_compute_unit_id">, + VoidIntInt; + +def int_AMDIL_wavefront_id : GCCBuiltin<"__amdil_wavefront_id">, + VoidIntInt; + + +/// Intrinsics for atomic instructions with a return value +/// Signed 32 bit integer atomics for local address space +def int_AMDIL_atomic_add_li32 : GCCBuiltin<"__atomic_add_li32">, + BinaryAtomicInt; +def int_AMDIL_atomic_sub_li32 : GCCBuiltin<"__atomic_sub_li32">, + BinaryAtomicInt; +def int_AMDIL_atomic_rsub_li32 : GCCBuiltin<"__atomic_rsub_li32">, + BinaryAtomicInt; +def int_AMDIL_atomic_xchg_li32 : GCCBuiltin<"__atomic_xchg_li32">, + BinaryAtomicInt; +def int_AMDIL_atomic_inc_li32 : GCCBuiltin<"__atomic_inc_li32">, + BinaryAtomicInt; +def int_AMDIL_atomic_dec_li32 : GCCBuiltin<"__atomic_dec_li32">, + BinaryAtomicInt; +def int_AMDIL_atomic_cmpxchg_li32 : GCCBuiltin<"__atomic_cmpxchg_li32">, + TernaryAtomicInt; +def int_AMDIL_atomic_min_li32 : GCCBuiltin<"__atomic_min_li32">, + BinaryAtomicInt; +def int_AMDIL_atomic_max_li32 : GCCBuiltin<"__atomic_max_li32">, + BinaryAtomicInt; +def int_AMDIL_atomic_and_li32 : GCCBuiltin<"__atomic_and_li32">, + BinaryAtomicInt; +def int_AMDIL_atomic_or_li32 : GCCBuiltin<"__atomic_or_li32">, + BinaryAtomicInt; +def int_AMDIL_atomic_mskor_li32 : GCCBuiltin<"__atomic_mskor_li32">, + TernaryAtomicInt; +def int_AMDIL_atomic_xor_li32 : GCCBuiltin<"__atomic_xor_li32">, + BinaryAtomicInt; + +/// Signed 32 bit integer atomics for region address space +def int_AMDIL_atomic_add_ri32 : GCCBuiltin<"__atomic_add_ri32">, + BinaryAtomicInt; +def int_AMDIL_atomic_sub_ri32 : GCCBuiltin<"__atomic_sub_ri32">, + BinaryAtomicInt; +def int_AMDIL_atomic_rsub_ri32 : GCCBuiltin<"__atomic_rsub_ri32">, + BinaryAtomicInt; +def int_AMDIL_atomic_xchg_ri32 : GCCBuiltin<"__atomic_xchg_ri32">, + BinaryAtomicInt; +def int_AMDIL_atomic_inc_ri32 : GCCBuiltin<"__atomic_inc_ri32">, + BinaryAtomicInt; +def int_AMDIL_atomic_dec_ri32 : GCCBuiltin<"__atomic_dec_ri32">, + BinaryAtomicInt; +def int_AMDIL_atomic_cmpxchg_ri32 : GCCBuiltin<"__atomic_cmpxchg_ri32">, + TernaryAtomicInt; +def int_AMDIL_atomic_min_ri32 : GCCBuiltin<"__atomic_min_ri32">, + BinaryAtomicInt; +def int_AMDIL_atomic_max_ri32 : GCCBuiltin<"__atomic_max_ri32">, + BinaryAtomicInt; +def int_AMDIL_atomic_and_ri32 : GCCBuiltin<"__atomic_and_ri32">, + BinaryAtomicInt; +def int_AMDIL_atomic_or_ri32 : GCCBuiltin<"__atomic_or_ri32">, + BinaryAtomicInt; +def int_AMDIL_atomic_mskor_ri32 : GCCBuiltin<"__atomic_mskor_ri32">, + TernaryAtomicInt; +def int_AMDIL_atomic_xor_ri32 : GCCBuiltin<"__atomic_xor_ri32">, + BinaryAtomicInt; + +/// 32 bit float atomics required by OpenCL +def int_AMDIL_atomic_xchg_lf32 : GCCBuiltin<"__atomic_xchg_lf32">, + BinaryAtomicInt; +def int_AMDIL_atomic_xchg_lf32_noret : GCCBuiltin<"__atomic_xchg_lf32_noret">, + BinaryAtomicIntNoRet; +def int_AMDIL_atomic_xchg_rf32 : GCCBuiltin<"__atomic_xchg_rf32">, + BinaryAtomicInt; +def int_AMDIL_atomic_xchg_rf32_noret : GCCBuiltin<"__atomic_xchg_rf32_noret">, + BinaryAtomicIntNoRet; + +/// Unsigned 32 bit integer atomics for local address space +def int_AMDIL_atomic_add_lu32 : GCCBuiltin<"__atomic_add_lu32">, + BinaryAtomicInt; +def int_AMDIL_atomic_sub_lu32 : GCCBuiltin<"__atomic_sub_lu32">, + BinaryAtomicInt; +def int_AMDIL_atomic_rsub_lu32 : GCCBuiltin<"__atomic_rsub_lu32">, + BinaryAtomicInt; +def int_AMDIL_atomic_xchg_lu32 : GCCBuiltin<"__atomic_xchg_lu32">, + BinaryAtomicInt; +def int_AMDIL_atomic_inc_lu32 : GCCBuiltin<"__atomic_inc_lu32">, + BinaryAtomicInt; +def int_AMDIL_atomic_dec_lu32 : GCCBuiltin<"__atomic_dec_lu32">, + BinaryAtomicInt; +def int_AMDIL_atomic_cmpxchg_lu32 : GCCBuiltin<"__atomic_cmpxchg_lu32">, + TernaryAtomicInt; +def int_AMDIL_atomic_min_lu32 : GCCBuiltin<"__atomic_min_lu32">, + BinaryAtomicInt; +def int_AMDIL_atomic_max_lu32 : GCCBuiltin<"__atomic_max_lu32">, + BinaryAtomicInt; +def int_AMDIL_atomic_and_lu32 : GCCBuiltin<"__atomic_and_lu32">, + BinaryAtomicInt; +def int_AMDIL_atomic_or_lu32 : GCCBuiltin<"__atomic_or_lu32">, + BinaryAtomicInt; +def int_AMDIL_atomic_mskor_lu32 : GCCBuiltin<"__atomic_mskor_lu32">, + TernaryAtomicInt; +def int_AMDIL_atomic_xor_lu32 : GCCBuiltin<"__atomic_xor_lu32">, + BinaryAtomicInt; + +/// Unsigned 32 bit integer atomics for region address space +def int_AMDIL_atomic_add_ru32 : GCCBuiltin<"__atomic_add_ru32">, + BinaryAtomicInt; +def int_AMDIL_atomic_sub_ru32 : GCCBuiltin<"__atomic_sub_ru32">, + BinaryAtomicInt; +def int_AMDIL_atomic_rsub_ru32 : GCCBuiltin<"__atomic_rsub_ru32">, + BinaryAtomicInt; +def int_AMDIL_atomic_xchg_ru32 : GCCBuiltin<"__atomic_xchg_ru32">, + BinaryAtomicInt; +def int_AMDIL_atomic_inc_ru32 : GCCBuiltin<"__atomic_inc_ru32">, + BinaryAtomicInt; +def int_AMDIL_atomic_dec_ru32 : GCCBuiltin<"__atomic_dec_ru32">, + BinaryAtomicInt; +def int_AMDIL_atomic_cmpxchg_ru32 : GCCBuiltin<"__atomic_cmpxchg_ru32">, + TernaryAtomicInt; +def int_AMDIL_atomic_min_ru32 : GCCBuiltin<"__atomic_min_ru32">, + BinaryAtomicInt; +def int_AMDIL_atomic_max_ru32 : GCCBuiltin<"__atomic_max_ru32">, + BinaryAtomicInt; +def int_AMDIL_atomic_and_ru32 : GCCBuiltin<"__atomic_and_ru32">, + BinaryAtomicInt; +def int_AMDIL_atomic_or_ru32 : GCCBuiltin<"__atomic_or_ru32">, + BinaryAtomicInt; +def int_AMDIL_atomic_mskor_ru32 : GCCBuiltin<"__atomic_mskor_ru32">, + TernaryAtomicInt; +def int_AMDIL_atomic_xor_ru32 : GCCBuiltin<"__atomic_xor_ru32">, + BinaryAtomicInt; + +/// Semaphore signal/wait/init +def int_AMDIL_semaphore_init : GCCBuiltin<"__amdil_semaphore_init">, + Intrinsic<[], [llvm_ptr_ty, llvm_i32_ty]>; +def int_AMDIL_semaphore_wait : GCCBuiltin<"__amdil_semaphore_wait">, + Intrinsic<[], [llvm_ptr_ty]>; +def int_AMDIL_semaphore_signal : GCCBuiltin<"__amdil_semaphore_signal">, + Intrinsic<[], [llvm_ptr_ty]>; +def int_AMDIL_semaphore_size : GCCBuiltin<"__amdil_max_semaphore_size">, + Intrinsic<[llvm_i32_ty], []>; +} diff --git a/lib/Target/AMDIL/AMDILMultiClass.td b/lib/Target/AMDIL/AMDILMultiClass.td new file mode 100644 index 00000000000..d6828178ba7 --- /dev/null +++ b/lib/Target/AMDIL/AMDILMultiClass.td @@ -0,0 +1,1440 @@ +//===-- AMDILMultiClass.td - AMDIL Multiclass defs ---*- tablegen -*-------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//==-----------------------------------------------------------------------===// +// Multiclass that handles branch instructions +multiclass BranchConditional { + def _i8 : ILFormat; + def _i16 : ILFormat; + def _i32 : ILFormat; + def _f32 : ILFormat; + def _i64 : ILFormat; + def _f64 : ILFormat; +} +// Multiclass that handles compare instructions +// When a definition is added here, a corrosponding defition +// needs to be added at: +// AMDILISelLowering.cpp@EmitInstrWithCustomInserter +multiclass Compare { + def _i8 : ILFormat; + def _i16 : ILFormat; + def _i32 : ILFormat; + def _i64 : ILFormat; + def _f32 : ILFormat; + def _f64 : ILFormat; + def _v2i8 : ILFormat; + def _v2i16 : ILFormat; + def _v2i32 : ILFormat; + def _v2i64 : ILFormat; + def _v2f32 : ILFormat; + def _v2f64 : ILFormat; + def _v4i8 : ILFormat; + def _v4i16 : ILFormat; + def _v4i32 : ILFormat; + def _v4f32 : ILFormat; +} + +// Multiclass that handles constant values +multiclass ILConstant { + def _i8 : ILFormat; + + // def _v2i8 : ILFormat; + + //def _v4i8 : ILFormat; + + def _i16 : ILFormat; + + // def _v2i16 : ILFormat; + + // def _v4i16 : ILFormat; + + def _i32 : ILFormat; + + // def _v2i32 : ILFormat; + + // def _v4i32 : ILFormat; + + def _i64 : ILFormat; + + // def _v2i64 : ILFormat; + + def _f32 : ILFormat; + + // def _v2f32 : ILFormat; + + // def _v4f32 : ILFormat; + + def _f64 : ILFormat; + + // def _v2f64 : ILFormat; + +} + +// Multiclass that handles memory store operations +multiclass GTRUNCSTORE { + def _i16i8 : OneInOneOut; + def _i32i8 : OneInOneOut; + def _i64i8 : OneInOneOut; + def _i32i16 : OneInOneOut; + def _i64i16 : OneInOneOut; + def _i64i32 : OneInOneOut; + def _f64f32 : OneInOneOut; + def _v2i32i8 : OneInOneOut; + def _v4i32i8 : OneInOneOut; + def _v2i16i8 : OneInOneOut; + def _v4i16i8 : OneInOneOut; + def _v2i32i16 : OneInOneOut; + def _v4i32i16 : OneInOneOut; + def _v2f64f32 : OneInOneOut; + def _v2i64i8 : OneInOneOut; + def _v2i64i16 : OneInOneOut; + def _v2i64i32 : OneInOneOut; +} + +// Multiclass that handles memory store operations +multiclass LTRUNCSTORE { + def _i16i8 : OneInOneOut; + def _i32i8 : OneInOneOut; + def _i64i8 : OneInOneOut; + def _i32i16 : OneInOneOut; + def _i64i16 : OneInOneOut; + def _i64i32 : OneInOneOut; + def _f64f32 : OneInOneOut; + def _v2i32i8 : OneInOneOut; + def _v4i32i8 : OneInOneOut; + def _v2i16i8 : OneInOneOut; + def _v4i16i8 : OneInOneOut; + def _v2i32i16 : OneInOneOut; + def _v4i32i16 : OneInOneOut; + def _v2f64f32 : OneInOneOut; + def _v2i64i8 : OneInOneOut; + def _v2i64i16 : OneInOneOut; + def _v2i64i32 : OneInOneOut; +} + +// Multiclass that handles memory store operations +multiclass PTRUNCSTORE { + def _i16i8 : OneInOneOut; + def _i32i8 : OneInOneOut; + def _i64i8 : OneInOneOut; + def _i32i16 : OneInOneOut; + def _i64i16 : OneInOneOut; + def _i64i32 : OneInOneOut; + def _f64f32 : OneInOneOut; + def _v2i32i8 : OneInOneOut; + def _v4i32i8 : OneInOneOut; + def _v2i16i8 : OneInOneOut; + def _v4i16i8 : OneInOneOut; + def _v2i32i16 : OneInOneOut; + def _v4i32i16 : OneInOneOut; + def _v2f64f32 : OneInOneOut; + def _v2i64i8 : OneInOneOut; + def _v2i64i16 : OneInOneOut; + def _v2i64i32 : OneInOneOut; +} + +// Multiclass that handles memory store operations +multiclass RTRUNCSTORE { + def _i16i8 : OneInOneOut; + def _i32i8 : OneInOneOut; + def _i64i8 : OneInOneOut; + def _i32i16 : OneInOneOut; + def _i64i16 : OneInOneOut; + def _i64i32 : OneInOneOut; + def _f64f32 : OneInOneOut; + def _v2i32i8 : OneInOneOut; + def _v4i32i8 : OneInOneOut; + def _v2i16i8 : OneInOneOut; + def _v4i16i8 : OneInOneOut; + def _v2i32i16 : OneInOneOut; + def _v4i32i16 : OneInOneOut; + def _v2f64f32 : OneInOneOut; + def _v2i64i8 : OneInOneOut; + def _v2i64i16 : OneInOneOut; + def _v2i64i32 : OneInOneOut; +} + + +// Multiclass that handles memory store operations +multiclass STORE { + def _i8 : OneInOneOut; + def _i16 : OneInOneOut; + def _i32 : OneInOneOut; + def _f32 : OneInOneOut; + def _i64 : OneInOneOut; + def _f64 : OneInOneOut; + def _v4f32 : OneInOneOut; + def _v2f32 : OneInOneOut; + def _v4i32 : OneInOneOut; + def _v2i8 : OneInOneOut; + def _v2i16 : OneInOneOut; + def _v4i8 : OneInOneOut; + def _v4i16 : OneInOneOut; + def _v2i32 : OneInOneOut; + def _v2f64 : OneInOneOut; + def _v2i64 : OneInOneOut; +} + +// Multiclass that handles load operations +multiclass LOAD { + def _i8 : OneInOneOut; + def _i16 : OneInOneOut; + def _i32 : OneInOneOut; + def _f32 : OneInOneOut; + def _i64 : OneInOneOut; + def _f64 : OneInOneOut; + def _v4f32 : OneInOneOut; + def _v2f32 : OneInOneOut; + def _v2f64 : OneInOneOut; + def _v4i32 : OneInOneOut; + def _v2i8 : OneInOneOut; + def _v2i16 : OneInOneOut; + def _v4i8 : OneInOneOut; + def _v4i16 : OneInOneOut; + def _v2i32 : OneInOneOut; + def _v2i64 : OneInOneOut; +} + +// Multiclass that handles memory store operations +multiclass GTRUNCSTORE64 { + def _i16i8 : OneInOneOut; + def _i32i8 : OneInOneOut; + def _i64i8 : OneInOneOut; + def _i32i16 : OneInOneOut; + def _i64i16 : OneInOneOut; + def _i64i32 : OneInOneOut; + def _f64f32 : OneInOneOut; + def _v2i32i8 : OneInOneOut; + def _v4i32i8 : OneInOneOut; + def _v2i16i8 : OneInOneOut; + def _v4i16i8 : OneInOneOut; + def _v2i32i16 : OneInOneOut; + def _v4i32i16 : OneInOneOut; + def _v2f64f32 : OneInOneOut; + def _v2i64i8 : OneInOneOut; + def _v2i64i16 : OneInOneOut; + def _v2i64i32 : OneInOneOut; +} + +// Multiclass that handles memory store operations +multiclass LTRUNCSTORE64 { + def _i16i8 : OneInOneOut; + def _i32i8 : OneInOneOut; + def _i64i8 : OneInOneOut; + def _i32i16 : OneInOneOut; + def _i64i16 : OneInOneOut; + def _i64i32 : OneInOneOut; + def _f64f32 : OneInOneOut; + def _v2i32i8 : OneInOneOut; + def _v4i32i8 : OneInOneOut; + def _v2i16i8 : OneInOneOut; + def _v4i16i8 : OneInOneOut; + def _v2i32i16 : OneInOneOut; + def _v4i32i16 : OneInOneOut; + def _v2f64f32 : OneInOneOut; + def _v2i64i8 : OneInOneOut; + def _v2i64i16 : OneInOneOut; + def _v2i64i32 : OneInOneOut; +} + +// Multiclass that handles memory store operations +multiclass PTRUNCSTORE64 { + def _i16i8 : OneInOneOut; + def _i32i8 : OneInOneOut; + def _i64i8 : OneInOneOut; + def _i32i16 : OneInOneOut; + def _i64i16 : OneInOneOut; + def _i64i32 : OneInOneOut; + def _f64f32 : OneInOneOut; + def _v2i32i8 : OneInOneOut; + def _v4i32i8 : OneInOneOut; + def _v2i16i8 : OneInOneOut; + def _v4i16i8 : OneInOneOut; + def _v2i32i16 : OneInOneOut; + def _v4i32i16 : OneInOneOut; + def _v2f64f32 : OneInOneOut; + def _v2i64i8 : OneInOneOut; + def _v2i64i16 : OneInOneOut; + def _v2i64i32 : OneInOneOut; +} + +// Multiclass that handles memory store operations +multiclass RTRUNCSTORE64 { + def _i16i8 : OneInOneOut; + def _i32i8 : OneInOneOut; + def _i64i8 : OneInOneOut; + def _i32i16 : OneInOneOut; + def _i64i16 : OneInOneOut; + def _i64i32 : OneInOneOut; + def _f64f32 : OneInOneOut; + def _v2i32i8 : OneInOneOut; + def _v4i32i8 : OneInOneOut; + def _v2i16i8 : OneInOneOut; + def _v4i16i8 : OneInOneOut; + def _v2i32i16 : OneInOneOut; + def _v4i32i16 : OneInOneOut; + def _v2f64f32 : OneInOneOut; + def _v2i64i8 : OneInOneOut; + def _v2i64i16 : OneInOneOut; + def _v2i64i32 : OneInOneOut; +} + + +// Multiclass that handles memory store operations +multiclass STORE64 { + def _i8 : OneInOneOut; + def _i16 : OneInOneOut; + def _i32 : OneInOneOut; + def _f32 : OneInOneOut; + def _i64 : OneInOneOut; + def _f64 : OneInOneOut; + def _v4f32 : OneInOneOut; + def _v2f32 : OneInOneOut; + def _v4i32 : OneInOneOut; + def _v2i8 : OneInOneOut; + def _v2i16 : OneInOneOut; + def _v4i8 : OneInOneOut; + def _v4i16 : OneInOneOut; + def _v2i32 : OneInOneOut; + def _v2f64 : OneInOneOut; + def _v2i64 : OneInOneOut; +} + +// Multiclass that handles load operations +multiclass LOAD64 { + def _i8 : OneInOneOut; + def _i16 : OneInOneOut; + def _i32 : OneInOneOut; + def _f32 : OneInOneOut; + def _i64 : OneInOneOut; + def _f64 : OneInOneOut; + def _v4f32 : OneInOneOut; + def _v2f32 : OneInOneOut; + def _v2f64 : OneInOneOut; + def _v4i32 : OneInOneOut; + def _v2i8 : OneInOneOut; + def _v2i16 : OneInOneOut; + def _v4i8 : OneInOneOut; + def _v4i16 : OneInOneOut; + def _v2i32 : OneInOneOut; + def _v2i64 : OneInOneOut; +} + +// Only scalar types should generate flow control +multiclass BranchInstr { + def _i8 : UnaryOpNoRet; + def _i16 : UnaryOpNoRet; + def _i32 : UnaryOpNoRet; + def _i64 : UnaryOpNoRet; + def _f32 : UnaryOpNoRet; + def _f64 : UnaryOpNoRet; +} +// Only scalar types should generate flow control +multiclass BranchInstr2 { + def _i8 : BinaryOpNoRet; + def _i16 : BinaryOpNoRet; + def _i32 : BinaryOpNoRet; + def _i64 : BinaryOpNoRet; + def _f32 : BinaryOpNoRet; + def _f64 : BinaryOpNoRet; +} + +// Class that handles the various vector extract patterns +multiclass VectorExtract { + def _v2f64 : ExtractVectorClass; + def _v4f32: ExtractVectorClass; + def _v2f32 : ExtractVectorClass; + def _v2i64 : ExtractVectorClass; + def _v4i8 : ExtractVectorClass; + def _v4i16 : ExtractVectorClass; + def _v4i32 : ExtractVectorClass; + def _v2i8 : ExtractVectorClass; + def _v2i16 : ExtractVectorClass; + def _v2i32 : ExtractVectorClass; +} + +multiclass VectorConcat { + def _v2f64 : VectorConcatClass; + def _v2i64 : VectorConcatClass; + def _v4f32 : VectorConcatClass; + def _v4i32 : VectorConcatClass; + def _v4i16 : VectorConcatClass; + def _v4i8 : VectorConcatClass; + def _v2f32 : VectorConcatClass; + def _v2i32 : VectorConcatClass; + def _v2i16 : VectorConcatClass; + def _v2i8 : VectorConcatClass; +} + +// Class that handles the various vector insert patterns +multiclass VectorInsert { + def _v2f64 : InsertVectorClass; + def _v4f32: InsertVectorClass; + def _v2f32 : InsertVectorClass; + def _v2i64 : InsertVectorClass; + def _v4i8 : InsertVectorClass; + def _v4i16 : InsertVectorClass; + def _v4i32 : InsertVectorClass; + def _v2i8 : InsertVectorClass; + def _v2i16 : InsertVectorClass; + def _v2i32 : InsertVectorClass; +} + +// generic class that handles math instruction for OneInOneOut instruction +// patterns +multiclass UnaryOpMC { + def _i8 : UnaryOp; + def _i16 : UnaryOp; + def _i32 : UnaryOp; + def _f32 : UnaryOp; + def _f64 : UnaryOp; + def _i64 : UnaryOp; + def _v4f32: UnaryOp; + def _v4i16 : UnaryOp; + def _v4i8 : UnaryOp; + def _v4i32 : UnaryOp; + def _v2f32 : UnaryOp; + def _v2i16 : UnaryOp; + def _v2i8 : UnaryOp; + def _v2i32 : UnaryOp; + def _v2f64 : UnaryOp; + def _v2i64 : UnaryOp; +} +multiclass UnaryOpMCVec { + def _v4f32: UnaryOp; + def _v4i16 : UnaryOp; + def _v4i8 : UnaryOp; + def _v4i32 : UnaryOp; + def _v2f32 : UnaryOp; + def _v2i16 : UnaryOp; + def _v2i8 : UnaryOp; + def _v2i32 : UnaryOp; + def _v2f64 : UnaryOp; + def _v2i64 : UnaryOp; +} + +multiclass UnaryOpMCf32< +ILOpCode f32OpCode, + SDNode OpNode> { + def _f32 : UnaryOp; + def _v4f32: UnaryOp; + def _v2f32 : UnaryOp; + } + +multiclass UnaryOpMCi32< +ILOpCode i32OpCode, + SDNode OpNode> { + def _i8 : UnaryOp; + def _i16 : UnaryOp; + def _i32 : UnaryOp; + def _v4i16 : UnaryOp; + def _v4i8 : UnaryOp; + def _v4i32 : UnaryOp; + def _v2i16 : UnaryOp; + def _v2i8 : UnaryOp; + def _v2i32 : UnaryOp; + } + + +multiclass BinaryOpMC { + def _i8 : BinaryOp; + + def _i16 : BinaryOp; + def _i32 : BinaryOp; + def _f32 : BinaryOp; + def _f64 : BinaryOp; + def _i64 : BinaryOp; + def _v4f32: BinaryOp; + def _v4i16 : BinaryOp; + def _v4i8 : BinaryOp; + def _v4i32 : BinaryOp; + def _v2f32 : BinaryOp; + def _v2i16 : BinaryOp; + def _v2i8 : BinaryOp; + def _v2i32 : BinaryOp; + def _v2f64 : BinaryOp; + def _v2i64 : BinaryOp; +} + +multiclass BinaryOpMCInt { + def _i8 : BinaryOp; + + def _i16 : BinaryOp; + def _i32 : BinaryOp; + def _i64 : BinaryOp; + def _v4i16 : BinaryOp; + def _v4i8 : BinaryOp; + def _v4i32 : BinaryOp; + def _v2i16 : BinaryOp; + def _v2i8 : BinaryOp; + def _v2i32 : BinaryOp; + def _v2i64 : BinaryOp; +} + +// generic class that handles math instruction for ThreeInOneOut +// instruction patterns +multiclass TernaryOpMC { + def _i8 : TernaryOp; + def _i16 : TernaryOp; + def _i32 : TernaryOp; + def _f32 : TernaryOp; + def _f64 : TernaryOp; + def _i64 : TernaryOp; + def _v4f32: TernaryOp; + def _v4i8 : TernaryOp; + def _v4i16 : TernaryOp; + def _v4i32 : TernaryOp; + def _v2f32 : TernaryOp; + def _v2i8 : TernaryOp; + def _v2i16 : TernaryOp; + def _v2i32 : TernaryOp; + def _v2f64 : TernaryOp; + def _v2i64 : TernaryOp; +} +multiclass BinaryOpMCi32 { + def _i8 : BinaryOp; + def _i16 : BinaryOp; + def _i32 : BinaryOp; + def _v4i16 : BinaryOp; + def _v4i8 : BinaryOp; + def _v4i32 : BinaryOp; + def _v2i16 : BinaryOp; + def _v2i8 : BinaryOp; + def _v2i32 : BinaryOp; +} +multiclass BinaryOpMCi64 { + def _i64 : BinaryOp; + def _v2i64 : BinaryOp; +} +multiclass BinaryOpMCi32Const { + def _i8 : BinaryOp; + def _i16 : BinaryOp; + def _i32 : BinaryOp; + def _v4i16 : BinaryOp; + def _v4i8 : BinaryOp; + def _v4i32 : BinaryOp; + def _v2i16 : BinaryOp; + def _v2i8 : BinaryOp; + def _v2i32 : BinaryOp; +} +multiclass BinaryOpMCf32 { + def _f32 : BinaryOp; + def _v4f32: BinaryOp; + def _v2f32 : BinaryOp; +} + +multiclass TernaryOpMCf64 { + def _f64 : TernaryOp; +} + +multiclass TernaryOpMCf32 { + def _f32 : TernaryOp; + def _v4f32: TernaryOp; + def _v2f32 : TernaryOp; +} +multiclass BinaryOpMCFloat { + def _f64 : BinaryOp; + def _v2f64 : BinaryOp; + def _f32 : BinaryOp; + def _v2f32 : BinaryOp; + def _v4f32: BinaryOp; + } + +multiclass TernaryOpMCScalar +{ + def _i8: TernaryOp; + def _i16: TernaryOp; + def _i32: TernaryOp; + def _i64: TernaryOp; + def _f32: TernaryOp; + def _f64: TernaryOp; +} + + +multiclass BitConversion +{ + def _i8 : UnaryOp; + def _i16 : UnaryOp; + def _i32 : UnaryOp; + def _f32 : UnaryOp; + def _i64 : UnaryOp; + def _f64 : UnaryOp; + def _v2i8 : UnaryOp; + def _v2i16 : UnaryOp; + def _v2i32 : UnaryOp; + def _v2f32 : UnaryOp; + def _v2i64 : UnaryOp; + def _v2f64 : UnaryOp; + def _v4i8 : UnaryOp; + def _v4i16 : UnaryOp; + def _v4i32 : UnaryOp; + def _v4f32 : UnaryOp; +} + + +multiclass UnaryIntrinsicInt +{ +def _i32 : OneInOneOut; +def _v2i32 : OneInOneOut; +def _v4i32 : OneInOneOut; +} + +multiclass IntrConvertF32TOF16 +{ +def _i16 : OneInOneOut; +def _v2i16 : OneInOneOut; +def _v4i16 : OneInOneOut; +} + + +multiclass IntrConvertF32TOI32 +{ +def _i32 : OneInOneOut; +def _v2i32 : OneInOneOut; +def _v4i32 : OneInOneOut; +} + +multiclass IntrConvertF64TOI32 +{ +def _i32 : OneInOneOut; +def _v2i32 : OneInOneOut; +} + +multiclass IntrConvertF16TOF32 +{ +def _f32 : OneInOneOut; +def _v2f32 : OneInOneOut; +def _v4f32 : OneInOneOut; +} + + +multiclass IntrConvertI32TOF32 +{ +def _f32 : OneInOneOut; +def _v2f32 : OneInOneOut; +def _v4f32 : OneInOneOut; +} + +multiclass BinaryIntrinsicLong +{ +def _i64 : TwoInOneOut; +} + + +multiclass BinaryIntrinsicInt +{ +def _i32 : TwoInOneOut; +def _v2i32 : TwoInOneOut; +def _v4i32 : TwoInOneOut; +} + +multiclass TernaryIntrinsicInt +{ +def _i32 : ThreeInOneOut; +def _v2i32 : ThreeInOneOut; +def _v4i32 : ThreeInOneOut; +} + +multiclass TernaryIntrinsicFloat +{ +def _f32 : ThreeInOneOut; +def _v2f32 : ThreeInOneOut; +def _v4f32 : ThreeInOneOut; +} + +multiclass BinaryIntrinsicDoubleScalar +{ +def _f64 : ThreeInOneOut; +} + +multiclass TernaryIntrinsicDoubleScalar +{ +def _f64 : ThreeInOneOut; +} + + +multiclass TernaryIntrinsicLongScalar +{ +def _i64 : ThreeInOneOut; +} + +multiclass QuaternaryIntrinsicInt +{ +def _i32 : FourInOneOut; +def _v2i32 : FourInOneOut; +def _v4i32 : FourInOneOut; +} + +multiclass UnaryIntrinsicFloatScalar +{ +def _f32 : OneInOneOut; +} + +multiclass UnaryIntrinsicFloat +{ +def _f32 : OneInOneOut; +def _v2f32 : OneInOneOut; +def _v4f32 : OneInOneOut; +} + +multiclass BinaryIntrinsicFloatScalar +{ +def _f32 : TwoInOneOut; +} +multiclass BinaryIntrinsicFloat +{ +def _f32 : TwoInOneOut; +def _v2f32 : TwoInOneOut; +def _v4f32 : TwoInOneOut; +} + +multiclass UnaryIntrinsicDoubleScalar +{ +def _f64 : OneInOneOut; +} + +multiclass UnaryIntrinsicDouble +{ +def _f64 : OneInOneOut; +def _v2f64 : OneInOneOut; +} + +multiclass BinaryIntrinsicDouble +{ +def _f64 : TwoInOneOut; +def _v2f64 : TwoInOneOut; +} + +multiclass TernaryIntrinsicDouble +{ +def _f64 : TwoInOneOut; +def _v2f64 : TwoInOneOut; +} diff --git a/lib/Target/AMDIL/AMDILNodes.td b/lib/Target/AMDIL/AMDILNodes.td new file mode 100644 index 00000000000..8cf07a5b27b --- /dev/null +++ b/lib/Target/AMDIL/AMDILNodes.td @@ -0,0 +1,325 @@ +//===- AMDILNodes.td - AMD IL nodes ------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//==-----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// Conversion DAG Nodes +//===----------------------------------------------------------------------===// +// Double to Single conversion +def IL_d2f : SDNode<"AMDILISD::DP_TO_FP" , SDTIL_DPToFPOp>; + +def IL_inttoany: SDNode<"AMDILISD::INTTOANY", SDTIL_IntToAny>; +//===----------------------------------------------------------------------===// +// Flow Control DAG Nodes +//===----------------------------------------------------------------------===// +def IL_brcond : SDNode<"AMDILISD::BRANCH_COND", SDTIL_BRCond, [SDNPHasChain]>; + +//===----------------------------------------------------------------------===// +// Comparison DAG Nodes +//===----------------------------------------------------------------------===// +def IL_cmp : SDNode<"AMDILISD::CMP", SDTIL_Cmp>; + +//===----------------------------------------------------------------------===// +// Call/Return DAG Nodes +//===----------------------------------------------------------------------===// +def IL_callseq_start : SDNode<"ISD::CALLSEQ_START", SDTIL_CallSeqStart, + [SDNPHasChain, SDNPOutGlue]>; +def IL_callseq_end : SDNode<"ISD::CALLSEQ_END", SDTIL_CallSeqEnd, + [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; +def IL_call : SDNode<"AMDILISD::CALL", SDTIL_Call, + [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; + +def IL_retflag : SDNode<"AMDILISD::RET_FLAG", SDTNone, + [SDNPHasChain, SDNPOptInGlue]>; + +//===----------------------------------------------------------------------===// +// Arithmetic DAG Nodes +//===----------------------------------------------------------------------===// +// Address modification nodes +def IL_addaddrri : SDNode<"AMDILISD::ADDADDR", SDTIL_AddAddrri, + [SDNPCommutative, SDNPAssociative]>; +def IL_addaddrir : SDNode<"AMDILISD::ADDADDR", SDTIL_AddAddrir, + [SDNPCommutative, SDNPAssociative]>; + +//===--------------------------------------------------------------------===// +// Instructions +//===--------------------------------------------------------------------===// +// Floating point math functions +def IL_cmov_logical : SDNode<"AMDILISD::CMOVLOG", SDTIL_GenTernaryOp>; +def IL_add : SDNode<"AMDILISD::ADD" , SDTIL_GenBinaryOp>; +def IL_cmov : SDNode<"AMDILISD::CMOV" , SDTIL_GenBinaryOp>; +def IL_or : SDNode<"AMDILISD::OR" ,SDTIL_GenBinaryOp>; +def IL_and : SDNode<"AMDILISD::AND" ,SDTIL_GenBinaryOp>; +def IL_xor : SDNode<"AMDILISD::XOR", SDTIL_GenBinaryOp>; +def IL_not : SDNode<"AMDILISD::NOT", SDTIL_GenUnaryOp>; +def IL_div_inf : SDNode<"AMDILISD::DIV_INF", SDTIL_GenBinaryOp>; +def IL_mad : SDNode<"AMDILISD::MAD", SDTIL_GenTernaryOp>; + +//===----------------------------------------------------------------------===// +// Integer functions +//===----------------------------------------------------------------------===// +def IL_inegate : SDNode<"AMDILISD::INEGATE" , SDTIntUnaryOp>; +def IL_umul : SDNode<"AMDILISD::UMUL" , SDTIntBinOp, + [SDNPCommutative, SDNPAssociative]>; +def IL_mov : SDNode<"AMDILISD::MOVE", SDTIL_GenUnaryOp>; +def IL_phimov : SDNode<"AMDILISD::PHIMOVE", SDTIL_GenUnaryOp>; +def IL_bitconv : SDNode<"AMDILISD::BITCONV", SDTIL_GenBitConv>; +def IL_ffb_hi : SDNode<"AMDILISD::IFFB_HI", SDTIL_GenUnaryOp>; +def IL_ffb_lo : SDNode<"AMDILISD::IFFB_LO", SDTIL_GenUnaryOp>; +def IL_smax : SDNode<"AMDILISD::SMAX", SDTIL_GenBinaryOp>; + +//===----------------------------------------------------------------------===// +// Double functions +//===----------------------------------------------------------------------===// +def IL_dcreate : SDNode<"AMDILISD::DCREATE" , SDTIL_DCreate>; +def IL_dcomphi : SDNode<"AMDILISD::DCOMPHI" , SDTIL_DComp>; +def IL_dcomplo : SDNode<"AMDILISD::DCOMPLO" , SDTIL_DComp>; +def IL_dcreate2 : SDNode<"AMDILISD::DCREATE2" , SDTIL_DCreate2>; +def IL_dcomphi2 : SDNode<"AMDILISD::DCOMPHI2" , SDTIL_DComp2>; +def IL_dcomplo2 : SDNode<"AMDILISD::DCOMPLO2" , SDTIL_DComp2>; + +//===----------------------------------------------------------------------===// +// Long functions +//===----------------------------------------------------------------------===// +def IL_lcreate : SDNode<"AMDILISD::LCREATE" , SDTIL_LCreate>; +def IL_lcreate2 : SDNode<"AMDILISD::LCREATE2" , SDTIL_LCreate2>; +def IL_lcomphi : SDNode<"AMDILISD::LCOMPHI" , SDTIL_LComp>; +def IL_lcomphi2 : SDNode<"AMDILISD::LCOMPHI2" , SDTIL_LComp2>; +def IL_lcomplo : SDNode<"AMDILISD::LCOMPLO" , SDTIL_LComp>; +def IL_lcomplo2 : SDNode<"AMDILISD::LCOMPLO2" , SDTIL_LComp2>; + +//===----------------------------------------------------------------------===// +// Vector functions +//===----------------------------------------------------------------------===// +def IL_vbuild : SDNode<"AMDILISD::VBUILD", SDTIL_GenVecBuild, + []>; +def IL_vextract : SDNode<"AMDILISD::VEXTRACT", SDTIL_GenVecExtract, + []>; +def IL_vinsert : SDNode<"AMDILISD::VINSERT", SDTIL_GenVecInsert, + []>; +def IL_vconcat : SDNode<"AMDILISD::VCONCAT", SDTIL_GenVecConcat, + []>; + +//===----------------------------------------------------------------------===// +// AMDIL Image Custom SDNodes +//===----------------------------------------------------------------------===// +def image2d_read : SDNode<"AMDILISD::IMAGE2D_READ", SDTIL_ImageRead, + [SDNPHasChain, SDNPMayLoad]>; +def image2d_write : SDNode<"AMDILISD::IMAGE2D_WRITE", SDTIL_ImageWrite, + [SDNPHasChain, SDNPMayStore]>; +def image2d_info0 : SDNode<"AMDILISD::IMAGE2D_INFO0", SDTIL_ImageInfo, []>; +def image2d_info1 : SDNode<"AMDILISD::IMAGE2D_INFO1", SDTIL_ImageInfo, []>; +def image3d_read : SDNode<"AMDILISD::IMAGE3D_READ", SDTIL_ImageRead, + [SDNPHasChain, SDNPMayLoad]>; +def image3d_write : SDNode<"AMDILISD::IMAGE3D_WRITE", SDTIL_ImageWrite3D, + [SDNPHasChain, SDNPMayStore]>; +def image3d_info0 : SDNode<"AMDILISD::IMAGE3D_INFO0", SDTIL_ImageInfo, []>; +def image3d_info1 : SDNode<"AMDILISD::IMAGE3D_INFO1", SDTIL_ImageInfo, []>; + +//===----------------------------------------------------------------------===// +// AMDIL Atomic Custom SDNodes +//===----------------------------------------------------------------------===// +//===-------------- 32 bit global atomics with return values --------------===// +def atom_g_add : SDNode<"AMDILISD::ATOM_G_ADD", SDTIL_BinAtom, + [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>; +def atom_g_and : SDNode<"AMDILISD::ATOM_G_AND", SDTIL_BinAtom, + [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>; +def atom_g_cmpxchg : SDNode<"AMDILISD::ATOM_G_CMPXCHG", SDTIL_TriAtom, + [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>; +def atom_g_dec : SDNode<"AMDILISD::ATOM_G_DEC", SDTIL_BinAtom, + [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>; +def atom_g_inc : SDNode<"AMDILISD::ATOM_G_INC", SDTIL_BinAtom, + [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>; +def atom_g_max : SDNode<"AMDILISD::ATOM_G_MAX", SDTIL_BinAtom, + [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>; +def atom_g_umax : SDNode<"AMDILISD::ATOM_G_UMAX", SDTIL_BinAtom, + [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>; +def atom_g_min : SDNode<"AMDILISD::ATOM_G_MIN", SDTIL_BinAtom, + [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>; +def atom_g_umin : SDNode<"AMDILISD::ATOM_G_UMIN", SDTIL_BinAtom, + [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>; +def atom_g_or : SDNode<"AMDILISD::ATOM_G_OR", SDTIL_BinAtom, + [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>; +def atom_g_sub : SDNode<"AMDILISD::ATOM_G_SUB", SDTIL_BinAtom, + [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>; +def atom_g_rsub : SDNode<"AMDILISD::ATOM_G_RSUB", SDTIL_BinAtom, + [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>; +def atom_g_xchg : SDNode<"AMDILISD::ATOM_G_XCHG", SDTIL_BinAtom, + [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>; +def atom_g_xor : SDNode<"AMDILISD::ATOM_G_XOR", SDTIL_BinAtom, + [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; + +//===------------- 32 bit global atomics without return values ------------===// +def atom_g_add_noret : SDNode<"AMDILISD::ATOM_G_ADD_NORET", SDTIL_BinAtom, + [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; +def atom_g_and_noret : SDNode<"AMDILISD::ATOM_G_AND_NORET", SDTIL_BinAtom, + [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; +def atom_g_cmpxchg_noret : SDNode<"AMDILISD::ATOM_G_CMPXCHG_NORET", + SDTIL_TriAtom, [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>; +def atom_g_cmp_noret : SDNode<"AMDILISD::ATOM_G_CMPXCHG_NORET", + SDTIL_TriAtom, [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; +def atom_g_dec_noret : SDNode<"AMDILISD::ATOM_G_DEC_NORET", SDTIL_BinAtom, + [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; +def atom_g_inc_noret : SDNode<"AMDILISD::ATOM_G_INC_NORET", SDTIL_BinAtom, + [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; +def atom_g_max_noret : SDNode<"AMDILISD::ATOM_G_MAX_NORET", SDTIL_BinAtom, + [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; +def atom_g_umax_noret: SDNode<"AMDILISD::ATOM_G_UMAX_NORET", + SDTIL_BinAtom, [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; +def atom_g_min_noret : SDNode<"AMDILISD::ATOM_G_MIN_NORET", SDTIL_BinAtom, + [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; +def atom_g_umin_noret: SDNode<"AMDILISD::ATOM_G_UMIN_NORET", + SDTIL_BinAtom, [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; +def atom_g_or_noret : SDNode<"AMDILISD::ATOM_G_OR_NORET", SDTIL_BinAtom, + [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; +def atom_g_sub_noret : SDNode<"AMDILISD::ATOM_G_SUB_NORET", SDTIL_BinAtom, + [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; +def atom_g_rsub_noret : SDNode<"AMDILISD::ATOM_G_RSUB_NORET", SDTIL_BinAtom, + [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; +def atom_g_xchg_noret: SDNode<"AMDILISD::ATOM_G_XCHG_NORET", + SDTIL_BinAtom, [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>; +def atom_g_xor_noret : SDNode<"AMDILISD::ATOM_G_XOR_NORET", SDTIL_BinAtom, + [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; + +//===--------------- 32 bit local atomics with return values --------------===// +def atom_l_add : SDNode<"AMDILISD::ATOM_L_ADD", SDTIL_BinAtom, + [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>; +def atom_l_and : SDNode<"AMDILISD::ATOM_L_AND", SDTIL_BinAtom, + [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>; +def atom_l_cmpxchg : SDNode<"AMDILISD::ATOM_L_CMPXCHG", SDTIL_TriAtom, + [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>; +def atom_l_dec : SDNode<"AMDILISD::ATOM_L_DEC", SDTIL_BinAtom, + [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>; +def atom_l_inc : SDNode<"AMDILISD::ATOM_L_INC", SDTIL_BinAtom, + [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>; +def atom_l_max : SDNode<"AMDILISD::ATOM_L_MAX", SDTIL_BinAtom, + [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>; +def atom_l_umax : SDNode<"AMDILISD::ATOM_L_UMAX", SDTIL_BinAtom, + [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>; +def atom_l_min : SDNode<"AMDILISD::ATOM_L_MIN", SDTIL_BinAtom, + [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>; +def atom_l_umin : SDNode<"AMDILISD::ATOM_L_UMIN", SDTIL_BinAtom, + [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>; +def atom_l_or : SDNode<"AMDILISD::ATOM_L_OR", SDTIL_BinAtom, + [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>; +def atom_l_mskor : SDNode<"AMDILISD::ATOM_L_MSKOR", SDTIL_TriAtom, + [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>; +def atom_l_sub : SDNode<"AMDILISD::ATOM_L_SUB", SDTIL_BinAtom, + [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>; +def atom_l_rsub : SDNode<"AMDILISD::ATOM_L_RSUB", SDTIL_BinAtom, + [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>; +def atom_l_xchg : SDNode<"AMDILISD::ATOM_L_XCHG", SDTIL_BinAtom, + [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>; +def atom_l_xor : SDNode<"AMDILISD::ATOM_L_XOR", SDTIL_BinAtom, + [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>; + +//===-------------- 32 bit local atomics without return values ------------===// +def atom_l_add_noret : SDNode<"AMDILISD::ATOM_L_ADD_NORET", SDTIL_BinAtom, + [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; +def atom_l_and_noret : SDNode<"AMDILISD::ATOM_L_AND_NORET", SDTIL_BinAtom, + [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; +def atom_l_cmpxchg_noret : SDNode<"AMDILISD::ATOM_L_CMPXCHG_NORET", + SDTIL_TriAtom, [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>; +def atom_l_dec_noret : SDNode<"AMDILISD::ATOM_L_DEC_NORET", SDTIL_BinAtom, + [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; +def atom_l_inc_noret : SDNode<"AMDILISD::ATOM_L_INC_NORET", SDTIL_BinAtom, + [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; +def atom_l_max_noret : SDNode<"AMDILISD::ATOM_L_MAX_NORET", SDTIL_BinAtom, + [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; +def atom_l_umax_noret: SDNode<"AMDILISD::ATOM_L_UMAX_NORET", + SDTIL_BinAtom, [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; +def atom_l_min_noret : SDNode<"AMDILISD::ATOM_L_MIN_NORET", SDTIL_BinAtom, + [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; +def atom_l_umin_noret: SDNode<"AMDILISD::ATOM_L_UMIN_NORET", + SDTIL_BinAtom, [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; +def atom_l_or_noret : SDNode<"AMDILISD::ATOM_L_OR_NORET", SDTIL_BinAtom, + [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; +def atom_l_mskor_noret : SDNode<"AMDILISD::ATOM_L_MSKOR_NORET", + SDTIL_TriAtom, [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; +def atom_l_sub_noret : SDNode<"AMDILISD::ATOM_L_SUB_NORET", SDTIL_BinAtom, + [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; +def atom_l_rsub_noret : SDNode<"AMDILISD::ATOM_L_RSUB_NORET", + SDTIL_BinAtom, [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; +def atom_l_xchg_noret: SDNode<"AMDILISD::ATOM_L_XCHG_NORET", + SDTIL_BinAtom, [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>; +def atom_l_xor_noret : SDNode<"AMDILISD::ATOM_L_XOR_NORET", SDTIL_BinAtom, + [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; + +//===--------------- 32 bit local atomics with return values --------------===// +def atom_r_add : SDNode<"AMDILISD::ATOM_R_ADD", SDTIL_BinAtom, + [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>; +def atom_r_and : SDNode<"AMDILISD::ATOM_R_AND", SDTIL_BinAtom, + [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>; +def atom_r_cmpxchg : SDNode<"AMDILISD::ATOM_R_CMPXCHG", SDTIL_TriAtom, + [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>; +def atom_r_dec : SDNode<"AMDILISD::ATOM_R_DEC", SDTIL_BinAtom, + [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>; +def atom_r_inc : SDNode<"AMDILISD::ATOM_R_INC", SDTIL_BinAtom, + [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>; +def atom_r_max : SDNode<"AMDILISD::ATOM_R_MAX", SDTIL_BinAtom, + [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>; +def atom_r_umax : SDNode<"AMDILISD::ATOM_R_UMAX", SDTIL_BinAtom, + [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>; +def atom_r_min : SDNode<"AMDILISD::ATOM_R_MIN", SDTIL_BinAtom, + [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>; +def atom_r_umin : SDNode<"AMDILISD::ATOM_R_UMIN", SDTIL_BinAtom, + [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>; +def atom_r_or : SDNode<"AMDILISD::ATOM_R_OR", SDTIL_BinAtom, + [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>; +def atom_r_mskor : SDNode<"AMDILISD::ATOM_R_MSKOR", SDTIL_TriAtom, + [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>; +def atom_r_sub : SDNode<"AMDILISD::ATOM_R_SUB", SDTIL_BinAtom, + [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>; +def atom_r_rsub : SDNode<"AMDILISD::ATOM_R_RSUB", SDTIL_BinAtom, + [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>; +def atom_r_xchg : SDNode<"AMDILISD::ATOM_R_XCHG", SDTIL_BinAtom, + [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>; +def atom_r_xor : SDNode<"AMDILISD::ATOM_R_XOR", SDTIL_BinAtom, + [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>; + +//===-------------- 32 bit local atomics without return values ------------===// +def atom_r_add_noret : SDNode<"AMDILISD::ATOM_R_ADD_NORET", SDTIL_BinAtom, + [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; +def atom_r_and_noret : SDNode<"AMDILISD::ATOM_R_AND_NORET", SDTIL_BinAtom, + [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; +def atom_r_cmpxchg_noret : SDNode<"AMDILISD::ATOM_R_CMPXCHG_NORET", + SDTIL_TriAtom, [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>; +def atom_r_dec_noret : SDNode<"AMDILISD::ATOM_R_DEC_NORET", SDTIL_BinAtom, + [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; +def atom_r_inc_noret : SDNode<"AMDILISD::ATOM_R_INC_NORET", SDTIL_BinAtom, + [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; +def atom_r_max_noret : SDNode<"AMDILISD::ATOM_R_MAX_NORET", SDTIL_BinAtom, + [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; +def atom_r_umax_noret: SDNode<"AMDILISD::ATOM_R_UMAX_NORET", + SDTIL_BinAtom, [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; +def atom_r_min_noret : SDNode<"AMDILISD::ATOM_R_MIN_NORET", SDTIL_BinAtom, + [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; +def atom_r_umin_noret: SDNode<"AMDILISD::ATOM_R_UMIN_NORET", + SDTIL_BinAtom, [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; +def atom_r_or_noret : SDNode<"AMDILISD::ATOM_R_OR_NORET", SDTIL_BinAtom, + [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; +def atom_r_mskor_noret : SDNode<"AMDILISD::ATOM_R_MSKOR_NORET", SDTIL_TriAtom, + [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; +def atom_r_sub_noret : SDNode<"AMDILISD::ATOM_R_SUB_NORET", SDTIL_BinAtom, + [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; +def atom_r_rsub_noret : SDNode<"AMDILISD::ATOM_R_RSUB_NORET", SDTIL_BinAtom, + [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; +def atom_r_xchg_noret: SDNode<"AMDILISD::ATOM_R_XCHG_NORET", + SDTIL_BinAtom, [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>; +def atom_r_xor_noret : SDNode<"AMDILISD::ATOM_R_XOR_NORET", SDTIL_BinAtom, + [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; + +//===--------------- 32 bit atomic counter instructions -------------------===// +def append_alloc : SDNode<"AMDILISD::APPEND_ALLOC", SDTIL_Append, + [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>; +def append_consume : SDNode<"AMDILISD::APPEND_CONSUME", SDTIL_Append, + [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>; +def append_alloc_noret : SDNode<"AMDILISD::APPEND_ALLOC_NORET", SDTIL_Append, + [SDNPHasChain, SDNPMayStore]>; +def append_consume_noret : SDNode<"AMDILISD::APPEND_CONSUME_NORET", + SDTIL_Append, [SDNPHasChain, SDNPMayStore]>; diff --git a/lib/Target/AMDIL/AMDILOperands.td b/lib/Target/AMDIL/AMDILOperands.td new file mode 100644 index 00000000000..b22c67bfdba --- /dev/null +++ b/lib/Target/AMDIL/AMDILOperands.td @@ -0,0 +1,37 @@ +//===- AMDILOperands.td - AMD IL Operands ------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//==-----------------------------------------------------------------------===// +//===----------------------------------------------------------------------===// +// Custom memory operand +//===----------------------------------------------------------------------===// + +def MEMI32 : Operand { + let PrintMethod = "printMemOperand"; + let MIOperandInfo = (ops GPRI32, GPRI32); +} + +def MEMI64 : Operand { + let PrintMethod = "printMemOperand"; + let MIOperandInfo = (ops GPRI64, GPRI64); +} + +// Call target types +def calltarget : Operand; +def brtarget : Operand; + +// def v2i8imm : Operand; +// def v4i8imm : Operand; +// def v2i16imm : Operand; +// def v4i16imm : Operand; +// def v2i32imm : Operand; +// def v4i32imm : Operand; +// def v2i64imm : Operand; +// def v2f32imm : Operand; +// def v4f32imm : Operand; +// def v2f64imm : Operand; + diff --git a/lib/Target/AMDIL/AMDILPatterns.td b/lib/Target/AMDIL/AMDILPatterns.td new file mode 100644 index 00000000000..aa59bcb5b4e --- /dev/null +++ b/lib/Target/AMDIL/AMDILPatterns.td @@ -0,0 +1,504 @@ +//===- AMDILPatterns.td - AMDIL Target Patterns------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//==-----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// Store pattern fragments +//===----------------------------------------------------------------------===// +def truncstorei64 : PatFrag<(ops node:$val, node:$ptr), + (truncstore node:$val, node:$ptr), [{ + return cast(N)->getMemoryVT() == MVT::i64; +}]>; +def truncstorev2i8 : PatFrag<(ops node:$val, node:$ptr), + (truncstore node:$val, node:$ptr), [{ + return cast(N)->getMemoryVT() == MVT::v2i8; +}]>; +def truncstorev2i16 : PatFrag<(ops node:$val, node:$ptr), + (truncstore node:$val, node:$ptr), [{ + return cast(N)->getMemoryVT() == MVT::v2i16; +}]>; +def truncstorev2i32 : PatFrag<(ops node:$val, node:$ptr), + (truncstore node:$val, node:$ptr), [{ + return cast(N)->getMemoryVT() == MVT::v2i32; +}]>; +def truncstorev2i64 : PatFrag<(ops node:$val, node:$ptr), + (truncstore node:$val, node:$ptr), [{ + return cast(N)->getMemoryVT() == MVT::v2i64; +}]>; +def truncstorev2f32 : PatFrag<(ops node:$val, node:$ptr), + (truncstore node:$val, node:$ptr), [{ + return cast(N)->getMemoryVT() == MVT::v2f32; +}]>; +def truncstorev2f64 : PatFrag<(ops node:$val, node:$ptr), + (truncstore node:$val, node:$ptr), [{ + return cast(N)->getMemoryVT() == MVT::v2f64; +}]>; +def truncstorev4i8 : PatFrag<(ops node:$val, node:$ptr), + (truncstore node:$val, node:$ptr), [{ + return cast(N)->getMemoryVT() == MVT::v4i8; +}]>; +def truncstorev4i16 : PatFrag<(ops node:$val, node:$ptr), + (truncstore node:$val, node:$ptr), [{ + return cast(N)->getMemoryVT() == MVT::v4i16; +}]>; +def truncstorev4i32 : PatFrag<(ops node:$val, node:$ptr), + (truncstore node:$val, node:$ptr), [{ + return cast(N)->getMemoryVT() == MVT::v4i32; +}]>; +def truncstorev4f32 : PatFrag<(ops node:$val, node:$ptr), + (truncstore node:$val, node:$ptr), [{ + return cast(N)->getMemoryVT() == MVT::v4f32; +}]>; + +def global_store : PatFrag<(ops node:$val, node:$ptr), + (store node:$val, node:$ptr), [{ + return isGlobalStore(dyn_cast(N)); +}]>; +def private_store : PatFrag<(ops node:$val, node:$ptr), + (store node:$val, node:$ptr), [{ + return isPrivateStore(dyn_cast(N)); +}]>; +def local_store : PatFrag<(ops node:$val, node:$ptr), + (store node:$val, node:$ptr), [{ + return isLocalStore(dyn_cast(N)); +}]>; +def region_store : PatFrag<(ops node:$val, node:$ptr), + (store node:$val, node:$ptr), [{ + return isRegionStore(dyn_cast(N)); +}]>; +def global_i8trunc_store : PatFrag<(ops node:$val, node:$ptr), + (truncstorei8 node:$val, node:$ptr), [{ + return isGlobalStore(dyn_cast(N)); +}]>; +def global_i16trunc_store : PatFrag<(ops node:$val, node:$ptr), + (truncstorei16 node:$val, node:$ptr), [{ + return isGlobalStore(dyn_cast(N)); +}]>; +def global_i32trunc_store : PatFrag<(ops node:$val, node:$ptr), + (truncstorei32 node:$val, node:$ptr), [{ + return isGlobalStore(dyn_cast(N)); +}]>; +def global_i64trunc_store : PatFrag<(ops node:$val, node:$ptr), + (truncstorei64 node:$val, node:$ptr), [{ + return isGlobalStore(dyn_cast(N)); +}]>; +def global_f32trunc_store : PatFrag<(ops node:$val, node:$ptr), + (truncstoref32 node:$val, node:$ptr), [{ + return isGlobalStore(dyn_cast(N)); +}]>; +def global_f64trunc_store : PatFrag<(ops node:$val, node:$ptr), + (truncstoref64 node:$val, node:$ptr), [{ + return isGlobalStore(dyn_cast(N)); +}]>; +def global_v2i8trunc_store : PatFrag<(ops node:$val, node:$ptr), + (truncstorev2i8 node:$val, node:$ptr), [{ + return isGlobalStore(dyn_cast(N)); +}]>; +def global_v2i16trunc_store : PatFrag<(ops node:$val, node:$ptr), + (truncstorev2i16 node:$val, node:$ptr), [{ + return isGlobalStore(dyn_cast(N)); +}]>; +def global_v2i32trunc_store : PatFrag<(ops node:$val, node:$ptr), + (truncstorev2i32 node:$val, node:$ptr), [{ + return isGlobalStore(dyn_cast(N)); +}]>; +def global_v2i64trunc_store : PatFrag<(ops node:$val, node:$ptr), + (truncstorev2i64 node:$val, node:$ptr), [{ + return isGlobalStore(dyn_cast(N)); +}]>; +def global_v2f32trunc_store : PatFrag<(ops node:$val, node:$ptr), + (truncstorev2f32 node:$val, node:$ptr), [{ + return isGlobalStore(dyn_cast(N)); +}]>; +def global_v2f64trunc_store : PatFrag<(ops node:$val, node:$ptr), + (truncstorev2f64 node:$val, node:$ptr), [{ + return isGlobalStore(dyn_cast(N)); +}]>; +def global_v4i8trunc_store : PatFrag<(ops node:$val, node:$ptr), + (truncstorev4i8 node:$val, node:$ptr), [{ + return isGlobalStore(dyn_cast(N)); +}]>; +def global_v4i16trunc_store : PatFrag<(ops node:$val, node:$ptr), + (truncstorev4i16 node:$val, node:$ptr), [{ + return isGlobalStore(dyn_cast(N)); +}]>; +def global_v4i32trunc_store : PatFrag<(ops node:$val, node:$ptr), + (truncstorev4i32 node:$val, node:$ptr), [{ + return isGlobalStore(dyn_cast(N)); +}]>; +def global_v4f32trunc_store : PatFrag<(ops node:$val, node:$ptr), + (truncstorev4f32 node:$val, node:$ptr), [{ + return isGlobalStore(dyn_cast(N)); +}]>; +def private_trunc_store : PatFrag<(ops node:$val, node:$ptr), + (truncstore node:$val, node:$ptr), [{ + return isPrivateStore(dyn_cast(N)); +}]>; +def private_i8trunc_store : PatFrag<(ops node:$val, node:$ptr), + (truncstorei8 node:$val, node:$ptr), [{ + return isPrivateStore(dyn_cast(N)); +}]>; +def private_i16trunc_store : PatFrag<(ops node:$val, node:$ptr), + (truncstorei16 node:$val, node:$ptr), [{ + return isPrivateStore(dyn_cast(N)); +}]>; +def private_i32trunc_store : PatFrag<(ops node:$val, node:$ptr), + (truncstorei32 node:$val, node:$ptr), [{ + return isPrivateStore(dyn_cast(N)); +}]>; +def private_i64trunc_store : PatFrag<(ops node:$val, node:$ptr), + (truncstorei64 node:$val, node:$ptr), [{ + return isPrivateStore(dyn_cast(N)); +}]>; +def private_f32trunc_store : PatFrag<(ops node:$val, node:$ptr), + (truncstoref32 node:$val, node:$ptr), [{ + return isPrivateStore(dyn_cast(N)); +}]>; +def private_f64trunc_store : PatFrag<(ops node:$val, node:$ptr), + (truncstoref64 node:$val, node:$ptr), [{ + return isPrivateStore(dyn_cast(N)); +}]>; +def private_v2i8trunc_store : PatFrag<(ops node:$val, node:$ptr), + (truncstorev2i8 node:$val, node:$ptr), [{ + return isPrivateStore(dyn_cast(N)); +}]>; +def private_v2i16trunc_store : PatFrag<(ops node:$val, node:$ptr), + (truncstorev2i16 node:$val, node:$ptr), [{ + return isPrivateStore(dyn_cast(N)); +}]>; +def private_v2i32trunc_store : PatFrag<(ops node:$val, node:$ptr), + (truncstorev2i32 node:$val, node:$ptr), [{ + return isPrivateStore(dyn_cast(N)); +}]>; +def private_v2i64trunc_store : PatFrag<(ops node:$val, node:$ptr), + (truncstorev2i64 node:$val, node:$ptr), [{ + return isPrivateStore(dyn_cast(N)); +}]>; +def private_v2f32trunc_store : PatFrag<(ops node:$val, node:$ptr), + (truncstorev2f32 node:$val, node:$ptr), [{ + return isPrivateStore(dyn_cast(N)); +}]>; +def private_v2f64trunc_store : PatFrag<(ops node:$val, node:$ptr), + (truncstorev2f64 node:$val, node:$ptr), [{ + return isPrivateStore(dyn_cast(N)); +}]>; +def private_v4i8trunc_store : PatFrag<(ops node:$val, node:$ptr), + (truncstorev4i8 node:$val, node:$ptr), [{ + return isPrivateStore(dyn_cast(N)); +}]>; +def private_v4i16trunc_store : PatFrag<(ops node:$val, node:$ptr), + (truncstorev4i16 node:$val, node:$ptr), [{ + return isPrivateStore(dyn_cast(N)); +}]>; +def private_v4i32trunc_store : PatFrag<(ops node:$val, node:$ptr), + (truncstorev4i32 node:$val, node:$ptr), [{ + return isPrivateStore(dyn_cast(N)); +}]>; +def private_v4f32trunc_store : PatFrag<(ops node:$val, node:$ptr), + (truncstorev4f32 node:$val, node:$ptr), [{ + return isPrivateStore(dyn_cast(N)); +}]>; + +def local_trunc_store : PatFrag<(ops node:$val, node:$ptr), + (truncstore node:$val, node:$ptr), [{ + return isLocalStore(dyn_cast(N)); +}]>; +def local_i8trunc_store : PatFrag<(ops node:$val, node:$ptr), + (truncstorei8 node:$val, node:$ptr), [{ + return isLocalStore(dyn_cast(N)); +}]>; +def local_i16trunc_store : PatFrag<(ops node:$val, node:$ptr), + (truncstorei16 node:$val, node:$ptr), [{ + return isLocalStore(dyn_cast(N)); +}]>; +def local_i32trunc_store : PatFrag<(ops node:$val, node:$ptr), + (truncstorei32 node:$val, node:$ptr), [{ + return isLocalStore(dyn_cast(N)); +}]>; +def local_i64trunc_store : PatFrag<(ops node:$val, node:$ptr), + (truncstorei64 node:$val, node:$ptr), [{ + return isLocalStore(dyn_cast(N)); +}]>; +def local_f32trunc_store : PatFrag<(ops node:$val, node:$ptr), + (truncstoref32 node:$val, node:$ptr), [{ + return isLocalStore(dyn_cast(N)); +}]>; +def local_f64trunc_store : PatFrag<(ops node:$val, node:$ptr), + (truncstoref64 node:$val, node:$ptr), [{ + return isLocalStore(dyn_cast(N)); +}]>; +def local_v2i8trunc_store : PatFrag<(ops node:$val, node:$ptr), + (truncstorev2i8 node:$val, node:$ptr), [{ + return isLocalStore(dyn_cast(N)); +}]>; +def local_v2i16trunc_store : PatFrag<(ops node:$val, node:$ptr), + (truncstorev2i16 node:$val, node:$ptr), [{ + return isLocalStore(dyn_cast(N)); +}]>; +def local_v2i32trunc_store : PatFrag<(ops node:$val, node:$ptr), + (truncstorev2i32 node:$val, node:$ptr), [{ + return isLocalStore(dyn_cast(N)); +}]>; +def local_v2i64trunc_store : PatFrag<(ops node:$val, node:$ptr), + (truncstorev2i64 node:$val, node:$ptr), [{ + return isLocalStore(dyn_cast(N)); +}]>; +def local_v2f32trunc_store : PatFrag<(ops node:$val, node:$ptr), + (truncstorev2f32 node:$val, node:$ptr), [{ + return isLocalStore(dyn_cast(N)); +}]>; +def local_v2f64trunc_store : PatFrag<(ops node:$val, node:$ptr), + (truncstorev2f64 node:$val, node:$ptr), [{ + return isLocalStore(dyn_cast(N)); +}]>; +def local_v4i8trunc_store : PatFrag<(ops node:$val, node:$ptr), + (truncstorev4i8 node:$val, node:$ptr), [{ + return isLocalStore(dyn_cast(N)); +}]>; +def local_v4i16trunc_store : PatFrag<(ops node:$val, node:$ptr), + (truncstorev4i16 node:$val, node:$ptr), [{ + return isLocalStore(dyn_cast(N)); +}]>; +def local_v4i32trunc_store : PatFrag<(ops node:$val, node:$ptr), + (truncstorev4i32 node:$val, node:$ptr), [{ + return isLocalStore(dyn_cast(N)); +}]>; +def local_v4f32trunc_store : PatFrag<(ops node:$val, node:$ptr), + (truncstorev4f32 node:$val, node:$ptr), [{ + return isLocalStore(dyn_cast(N)); +}]>; + +def region_trunc_store : PatFrag<(ops node:$val, node:$ptr), + (truncstore node:$val, node:$ptr), [{ + return isRegionStore(dyn_cast(N)); +}]>; +def region_i8trunc_store : PatFrag<(ops node:$val, node:$ptr), + (truncstorei8 node:$val, node:$ptr), [{ + return isRegionStore(dyn_cast(N)); +}]>; +def region_i16trunc_store : PatFrag<(ops node:$val, node:$ptr), + (truncstorei16 node:$val, node:$ptr), [{ + return isRegionStore(dyn_cast(N)); +}]>; +def region_i32trunc_store : PatFrag<(ops node:$val, node:$ptr), + (truncstorei32 node:$val, node:$ptr), [{ + return isRegionStore(dyn_cast(N)); +}]>; +def region_i64trunc_store : PatFrag<(ops node:$val, node:$ptr), + (truncstorei64 node:$val, node:$ptr), [{ + return isRegionStore(dyn_cast(N)); +}]>; +def region_f32trunc_store : PatFrag<(ops node:$val, node:$ptr), + (truncstoref32 node:$val, node:$ptr), [{ + return isRegionStore(dyn_cast(N)); +}]>; +def region_f64trunc_store : PatFrag<(ops node:$val, node:$ptr), + (truncstoref64 node:$val, node:$ptr), [{ + return isRegionStore(dyn_cast(N)); +}]>; +def region_v2i8trunc_store : PatFrag<(ops node:$val, node:$ptr), + (truncstorev2i8 node:$val, node:$ptr), [{ + return isRegionStore(dyn_cast(N)); +}]>; +def region_v2i16trunc_store : PatFrag<(ops node:$val, node:$ptr), + (truncstorev2i16 node:$val, node:$ptr), [{ + return isRegionStore(dyn_cast(N)); +}]>; +def region_v2i32trunc_store : PatFrag<(ops node:$val, node:$ptr), + (truncstorev2i32 node:$val, node:$ptr), [{ + return isRegionStore(dyn_cast(N)); +}]>; +def region_v2i64trunc_store : PatFrag<(ops node:$val, node:$ptr), + (truncstorev2i64 node:$val, node:$ptr), [{ + return isRegionStore(dyn_cast(N)); +}]>; +def region_v2f32trunc_store : PatFrag<(ops node:$val, node:$ptr), + (truncstorev2f32 node:$val, node:$ptr), [{ + return isRegionStore(dyn_cast(N)); +}]>; +def region_v2f64trunc_store : PatFrag<(ops node:$val, node:$ptr), + (truncstorev2f64 node:$val, node:$ptr), [{ + return isRegionStore(dyn_cast(N)); +}]>; +def region_v4i8trunc_store : PatFrag<(ops node:$val, node:$ptr), + (truncstorev4i8 node:$val, node:$ptr), [{ + return isRegionStore(dyn_cast(N)); +}]>; +def region_v4i16trunc_store : PatFrag<(ops node:$val, node:$ptr), + (truncstorev4i16 node:$val, node:$ptr), [{ + return isRegionStore(dyn_cast(N)); +}]>; +def region_v4i32trunc_store : PatFrag<(ops node:$val, node:$ptr), + (truncstorev4i32 node:$val, node:$ptr), [{ + return isRegionStore(dyn_cast(N)); +}]>; +def region_v4f32trunc_store : PatFrag<(ops node:$val, node:$ptr), + (truncstorev4f32 node:$val, node:$ptr), [{ + return isRegionStore(dyn_cast(N)); +}]>; + +//===----------------------------------------------------------------------===// +// Load pattern fragments +//===----------------------------------------------------------------------===// +// Global address space loads +def global_load : PatFrag<(ops node:$ptr), (load node:$ptr), [{ + return isGlobalLoad(dyn_cast(N)); +}]>; +def global_sext_load : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ + return isGlobalLoad(dyn_cast(N)); +}]>; +def global_aext_load : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ + return isGlobalLoad(dyn_cast(N)); +}]>; +def global_zext_load : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ + return isGlobalLoad(dyn_cast(N)); +}]>; +// Private address space loads +def private_load : PatFrag<(ops node:$ptr), (load node:$ptr), [{ + return isPrivateLoad(dyn_cast(N)); +}]>; +def private_sext_load : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ + return isPrivateLoad(dyn_cast(N)); +}]>; +def private_aext_load : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ + return isPrivateLoad(dyn_cast(N)); +}]>; +def private_zext_load : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ + return isPrivateLoad(dyn_cast(N)); +}]>; +// Local address space loads +def local_load : PatFrag<(ops node:$ptr), (load node:$ptr), [{ + return isLocalLoad(dyn_cast(N)); +}]>; +def local_sext_load : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ + return isLocalLoad(dyn_cast(N)); +}]>; +def local_aext_load : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ + return isLocalLoad(dyn_cast(N)); +}]>; +def local_zext_load : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ + return isLocalLoad(dyn_cast(N)); +}]>; +// Region address space loads +def region_load : PatFrag<(ops node:$ptr), (load node:$ptr), [{ + return isRegionLoad(dyn_cast(N)); +}]>; +def region_sext_load : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ + return isRegionLoad(dyn_cast(N)); +}]>; +def region_aext_load : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ + return isRegionLoad(dyn_cast(N)); +}]>; +def region_zext_load : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ + return isRegionLoad(dyn_cast(N)); +}]>; +// Constant address space loads +def constant_load : PatFrag<(ops node:$ptr), (load node:$ptr), [{ + return isConstantLoad(dyn_cast(N), -1); +}]>; +def constant_sext_load : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ + return isConstantLoad(dyn_cast(N), -1); +}]>; +def constant_aext_load : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ + return isConstantLoad(dyn_cast(N), -1); +}]>; +def constant_zext_load : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ + return isConstantLoad(dyn_cast(N), -1); +}]>; +// Constant pool loads +def cp_load : PatFrag<(ops node:$ptr), (load node:$ptr), [{ + return isCPLoad(dyn_cast(N)); +}]>; +def cp_sext_load : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{ + return isCPLoad(dyn_cast(N)); +}]>; +def cp_zext_load : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{ + return isCPLoad(dyn_cast(N)); +}]>; +def cp_aext_load : PatFrag<(ops node:$ptr), (extload node:$ptr), [{ + return isCPLoad(dyn_cast(N)); +}]>; + +//===----------------------------------------------------------------------===// +// Complex addressing mode patterns +//===----------------------------------------------------------------------===// +def ADDR : ComplexPattern; +def ADDRF : ComplexPattern; +def ADDR64 : ComplexPattern; +def ADDR64F : ComplexPattern; + + +//===----------------------------------------------------------------------===// +// Conditional Instruction Pattern Leafs +//===----------------------------------------------------------------------===// +class IL_CC_Op : PatLeaf<(i32 N)>; +def IL_CC_D_EQ : IL_CC_Op<0>; +def IL_CC_D_GE : IL_CC_Op<1>; +def IL_CC_D_LT : IL_CC_Op<2>; +def IL_CC_D_NE : IL_CC_Op<3>; +def IL_CC_F_EQ : IL_CC_Op<4>; +def IL_CC_F_GE : IL_CC_Op<5>; +def IL_CC_F_LT : IL_CC_Op<6>; +def IL_CC_F_NE : IL_CC_Op<7>; +def IL_CC_I_EQ : IL_CC_Op<8>; +def IL_CC_I_GE : IL_CC_Op<9>; +def IL_CC_I_LT : IL_CC_Op<10>; +def IL_CC_I_NE : IL_CC_Op<11>; +def IL_CC_U_GE : IL_CC_Op<12>; +def IL_CC_U_LT : IL_CC_Op<13>; +// Pseudo IL comparison instructions that aren't natively supported +def IL_CC_F_GT : IL_CC_Op<14>; +def IL_CC_U_GT : IL_CC_Op<15>; +def IL_CC_I_GT : IL_CC_Op<16>; +def IL_CC_D_GT : IL_CC_Op<17>; +def IL_CC_F_LE : IL_CC_Op<18>; +def IL_CC_U_LE : IL_CC_Op<19>; +def IL_CC_I_LE : IL_CC_Op<20>; +def IL_CC_D_LE : IL_CC_Op<21>; +def IL_CC_F_UNE : IL_CC_Op<22>; +def IL_CC_F_UEQ : IL_CC_Op<23>; +def IL_CC_F_ULT : IL_CC_Op<24>; +def IL_CC_F_UGT : IL_CC_Op<25>; +def IL_CC_F_ULE : IL_CC_Op<26>; +def IL_CC_F_UGE : IL_CC_Op<27>; +def IL_CC_F_ONE : IL_CC_Op<28>; +def IL_CC_F_OEQ : IL_CC_Op<29>; +def IL_CC_F_OLT : IL_CC_Op<30>; +def IL_CC_F_OGT : IL_CC_Op<31>; +def IL_CC_F_OLE : IL_CC_Op<32>; +def IL_CC_F_OGE : IL_CC_Op<33>; +def IL_CC_D_UNE : IL_CC_Op<34>; +def IL_CC_D_UEQ : IL_CC_Op<35>; +def IL_CC_D_ULT : IL_CC_Op<36>; +def IL_CC_D_UGT : IL_CC_Op<37>; +def IL_CC_D_ULE : IL_CC_Op<38>; +def IL_CC_D_UGE : IL_CC_Op<39>; +def IL_CC_D_ONE : IL_CC_Op<30>; +def IL_CC_D_OEQ : IL_CC_Op<41>; +def IL_CC_D_OLT : IL_CC_Op<42>; +def IL_CC_D_OGT : IL_CC_Op<43>; +def IL_CC_D_OLE : IL_CC_Op<44>; +def IL_CC_D_OGE : IL_CC_Op<45>; +def IL_CC_U_EQ : IL_CC_Op<46>; +def IL_CC_U_NE : IL_CC_Op<47>; +def IL_CC_F_O : IL_CC_Op<48>; +def IL_CC_D_O : IL_CC_Op<49>; +def IL_CC_F_UO : IL_CC_Op<50>; +def IL_CC_D_UO : IL_CC_Op<51>; +def IL_CC_L_LE : IL_CC_Op<52>; +def IL_CC_L_GE : IL_CC_Op<53>; +def IL_CC_L_EQ : IL_CC_Op<54>; +def IL_CC_L_NE : IL_CC_Op<55>; +def IL_CC_L_LT : IL_CC_Op<56>; +def IL_CC_L_GT : IL_CC_Op<57>; +def IL_CC_UL_LE : IL_CC_Op<58>; +def IL_CC_UL_GE : IL_CC_Op<59>; +def IL_CC_UL_EQ : IL_CC_Op<60>; +def IL_CC_UL_NE : IL_CC_Op<61>; +def IL_CC_UL_LT : IL_CC_Op<62>; +def IL_CC_UL_GT : IL_CC_Op<63>; diff --git a/lib/Target/AMDIL/AMDILProfiles.td b/lib/Target/AMDIL/AMDILProfiles.td new file mode 100644 index 00000000000..60435a82b66 --- /dev/null +++ b/lib/Target/AMDIL/AMDILProfiles.td @@ -0,0 +1,174 @@ +//===- AMDILProfiles.td - AMD IL Profiles ------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//==-----------------------------------------------------------------------===// +// These are used for custom selection dag type profiles + +//===----------------------------------------------------------------------===// +// Custom Selection DAG Type Profiles +//===----------------------------------------------------------------------===// +// SDTCisDP - The specified operand has double type +// Tablegen needs to be hacked to get this constraint to work +//class SDTCisDP : SDTypeConstraint; + +//===----------------------------------------------------------------------===// +// Generic Profile Types +//===----------------------------------------------------------------------===// + +def SDTIL_GenUnaryOp : SDTypeProfile<1, 1, [ + SDTCisSameAs<0, 1> + ]>; +def SDTIL_GenBinaryOp : SDTypeProfile<1, 2, [ + SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2> + ]>; +def SDTIL_GenTernaryOp : SDTypeProfile<1, 3, [ + SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisSameAs<2, 3> + ]>; +def SDTIL_GenCMovLog : SDTypeProfile<1, 3, [ + SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>, SDTCisInt<1> + ]>; +def SDTIL_GenVecBuild : SDTypeProfile<1, 1, [ + SDTCisEltOfVec<1, 0> + ]>; + +def SDTIL_GenVecExtract : SDTypeProfile<1, 2, [ + SDTCisEltOfVec<0, 1>, SDTCisVT<2, i32> + ]>; + +def SDTIL_GenVecInsert : SDTypeProfile<1, 4, [ + SDTCisEltOfVec<2, 1>, SDTCisSameAs<0, 1>, + SDTCisVT<3, i32>, SDTCisVT<4, i32> + ]>; + +def SDTIL_GenVecShuffle : SDTypeProfile <1, 2, [ + SDTCisSameAs<0, 1>, SDTCisVT<2, i32> + ]>; + +def SDTIL_GenVecConcat : SDTypeProfile <1, 2, [ + SDTCisSameAs<1, 2> + ]>; +//===----------------------------------------------------------------------===// +// Conversion Profile Types +//===----------------------------------------------------------------------===// +def SDTIL_DPToFPOp : SDTypeProfile<1, 1, [ + SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1> + ]>; // d2f + +def SDTIL_AnyToInt : SDTypeProfile<1, 1, [ + SDTCisInt<0> + ]>; +def SDTIL_IntToAny : SDTypeProfile<1, 1, [ + SDTCisInt<1> + ]>; +def SDTIL_GenBitConv : SDTypeProfile<1, 1, []>; +//===----------------------------------------------------------------------===// +// Scalar Profile Types +//===----------------------------------------------------------------------===// + +// Add instruction pattern to handle offsets of memory operationns +def SDTIL_AddAddrri: SDTypeProfile<1, 2, [ + SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisSameAs<0, 2> + ]>; +def SDTIL_AddAddrir : SDTypeProfile<1, 2, [ + SDTCisInt<0>, SDTCisPtrTy<2>, SDTCisSameAs<0, 1> + ]>; + +def SDTIL_LCreate : SDTypeProfile<1, 2, [ + SDTCisVT<0, i64>, SDTCisVT<1, i32>, SDTCisSameAs<1, 2> + ]>; +def SDTIL_LCreate2 : SDTypeProfile<1, 2, [ + SDTCisVT<0, v2i64>, SDTCisVT<1, v2i32>, SDTCisSameAs<1, 2> + ]>; +def SDTIL_LComp : SDTypeProfile<1, 1, [ + SDTCisVT<0, i32>, SDTCisVT<1, i64> + ]>; +def SDTIL_LComp2 : SDTypeProfile<1, 1, [ + SDTCisVT<0, v2i32>, SDTCisVT<1, v2i64> + ]>; +def SDTIL_DCreate : SDTypeProfile<1, 2, [ + SDTCisVT<0, f64>, SDTCisVT<1, i32>, SDTCisSameAs<1, 2> + ]>; +def SDTIL_DComp : SDTypeProfile<1, 1, [ + SDTCisVT<0, i32>, SDTCisVT<1, f64> + ]>; +def SDTIL_DCreate2 : SDTypeProfile<1, 2, [ + SDTCisVT<0, v2f64>, SDTCisVT<1, v2i32>, SDTCisSameAs<1, 2> + ]>; +def SDTIL_DComp2 : SDTypeProfile<1, 1, [ + SDTCisVT<0, v2i32>, SDTCisVT<1, v2f64> + ]>; +//===----------------------------------------------------------------------===// +// Flow Control Profile Types +//===----------------------------------------------------------------------===// +// Profile for Normal Call +def SDTIL_Call : SDTypeProfile<0, 1, [ + SDTCisVT<0, i32> + ]>; +// Branch instruction where second and third are basic blocks +def SDTIL_BRCond : SDTypeProfile<0, 2, [ + SDTCisVT<0, OtherVT> + ]>; +// Comparison instruction +def SDTIL_Cmp : SDTypeProfile<1, 3, [ + SDTCisSameAs<0, 2>, SDTCisSameAs<2,3>, SDTCisVT<1, i32> + ]>; + + +//===----------------------------------------------------------------------===// +// Call Sequence Profiles +//===----------------------------------------------------------------------===// +def SDTIL_CallSeqStart : SDCallSeqStart< [ + SDTCisVT<0, i32> + ]>; +def SDTIL_CallSeqEnd : SDCallSeqEnd< [ + SDTCisVT<0, i32>, SDTCisVT<1, i32> + ]>; + +//===----------------------------------------------------------------------===// +// Image Operation Profiles +//===----------------------------------------------------------------------===// +def SDTIL_ImageRead : SDTypeProfile<1, 3, + [SDTCisVT<0, v4i32>, SDTCisPtrTy<1>, SDTCisVT<2, i32>, SDTCisVT<3, v4f32>]>; +def SDTIL_ImageWrite : SDTypeProfile<0, 3, + [SDTCisPtrTy<0>, SDTCisVT<1, v2i32>, SDTCisVT<2, v4i32>]>; +def SDTIL_ImageWrite3D : SDTypeProfile<0, 3, + [SDTCisPtrTy<0>, SDTCisVT<1, v4i32>, SDTCisVT<2, v4i32>]>; +def SDTIL_ImageInfo : SDTypeProfile<1, 1, + [SDTCisVT<0, v4i32>, SDTCisPtrTy<1>]>; +//===----------------------------------------------------------------------===// +// Atomic Operation Profiles +//===----------------------------------------------------------------------===// +def SDTIL_UniAtomNoRet : SDTypeProfile<0, 2, [ + SDTCisPtrTy<0>, SDTCisVT<1, i32> + ]>; +def SDTIL_BinAtomNoRet : SDTypeProfile<0, 3, [ + SDTCisPtrTy<0>, SDTCisVT<1, i32>, SDTCisVT<2, i32> + ]>; +def SDTIL_TriAtomNoRet : SDTypeProfile<0, 4, [ + SDTCisPtrTy<0>, SDTCisVT<1, i32>, SDTCisVT<2, i32>, SDTCisVT<3, i32> + ]>; +def SDTIL_UniAtom : SDTypeProfile<1, 2, [ + SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, i32> + ]>; +def SDTIL_BinAtom : SDTypeProfile<1, 3, [ + SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, i32>, SDTCisVT<3, i32> + ]>; +def SDTIL_TriAtom : SDTypeProfile<1, 4, [ + SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, i32>, + SDTCisVT<3, i32>, SDTCisVT<4, i32> + ]>; + +def SDTIL_BinAtomFloat : SDTypeProfile<1, 3, [ + SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, f32>, SDTCisVT<3, f32> + ]>; +def SDTIL_BinAtomNoRetFloat : SDTypeProfile<0, 3, [ + SDTCisPtrTy<0>, SDTCisVT<1, f32>, SDTCisVT<2, f32> + ]>; + +def SDTIL_Append : SDTypeProfile<1, 1, [ + SDTCisVT<0, i32>, SDTCisPtrTy<1> + ]>; diff --git a/lib/Target/AMDIL/AMDILRegisterInfo.td b/lib/Target/AMDIL/AMDILRegisterInfo.td new file mode 100644 index 00000000000..17f4b3b46a1 --- /dev/null +++ b/lib/Target/AMDIL/AMDILRegisterInfo.td @@ -0,0 +1,964 @@ +//===- AMDILRegisterInfo.td - AMDIL Register defs ----------*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//==-----------------------------------------------------------------------===// +// +// Declarations that describe the AMDIL register file +// +//===----------------------------------------------------------------------===// + +class AMDILReg num, string n> : Register { + field bits<16> Value; + let Value = num; + let Namespace = "AMDIL"; +} + +// We will start with 8 registers for each class before expanding to more +// Since the swizzle is added based on the register class, we can leave it +// off here and just specify different registers for different register classes +def R1 : AMDILReg<1, "r1">, DwarfRegNum<[1]>; +def R2 : AMDILReg<2, "r2">, DwarfRegNum<[2]>; +def R3 : AMDILReg<3, "r3">, DwarfRegNum<[3]>; +def R4 : AMDILReg<4, "r4">, DwarfRegNum<[4]>; +def R5 : AMDILReg<5, "r5">, DwarfRegNum<[5]>; +def R6 : AMDILReg<6, "r6">, DwarfRegNum<[6]>; +def R7 : AMDILReg<7, "r7">, DwarfRegNum<[7]>; +def R8 : AMDILReg<8, "r8">, DwarfRegNum<[8]>; +def R9 : AMDILReg<9, "r9">, DwarfRegNum<[9]>; +def R10 : AMDILReg<10, "r10">, DwarfRegNum<[10]>; +def R11 : AMDILReg<11, "r11">, DwarfRegNum<[11]>; +def R12 : AMDILReg<12, "r12">, DwarfRegNum<[12]>; +def R13 : AMDILReg<13, "r13">, DwarfRegNum<[13]>; +def R14 : AMDILReg<14, "r14">, DwarfRegNum<[14]>; +def R15 : AMDILReg<15, "r15">, DwarfRegNum<[15]>; +def R16 : AMDILReg<16, "r16">, DwarfRegNum<[16]>; +def R17 : AMDILReg<17, "r17">, DwarfRegNum<[17]>; +def R18 : AMDILReg<18, "r18">, DwarfRegNum<[18]>; +def R19 : AMDILReg<19, "r19">, DwarfRegNum<[19]>; +def R20 : AMDILReg<20, "r20">, DwarfRegNum<[20]>; +def R21 : AMDILReg<21, "r21">, DwarfRegNum<[21]>; +def R22 : AMDILReg<22, "r22">, DwarfRegNum<[22]>; +def R23 : AMDILReg<23, "r23">, DwarfRegNum<[23]>; +def R24 : AMDILReg<24, "r24">, DwarfRegNum<[24]>; +def R25 : AMDILReg<25, "r25">, DwarfRegNum<[25]>; +def R26 : AMDILReg<26, "r26">, DwarfRegNum<[26]>; +def R27 : AMDILReg<27, "r27">, DwarfRegNum<[27]>; +def R28 : AMDILReg<28, "r28">, DwarfRegNum<[28]>; +def R29 : AMDILReg<29, "r29">, DwarfRegNum<[29]>; +def R30 : AMDILReg<30, "r30">, DwarfRegNum<[30]>; +def R31 : AMDILReg<31, "r31">, DwarfRegNum<[31]>; +def R32 : AMDILReg<32, "r32">, DwarfRegNum<[32]>; +def R33 : AMDILReg<33, "r33">, DwarfRegNum<[33]>; +def R34 : AMDILReg<34, "r34">, DwarfRegNum<[34]>; +def R35 : AMDILReg<35, "r35">, DwarfRegNum<[35]>; +def R36 : AMDILReg<36, "r36">, DwarfRegNum<[36]>; +def R37 : AMDILReg<37, "r37">, DwarfRegNum<[37]>; +def R38 : AMDILReg<38, "r38">, DwarfRegNum<[38]>; +def R39 : AMDILReg<39, "r39">, DwarfRegNum<[39]>; +def R40 : AMDILReg<40, "r40">, DwarfRegNum<[40]>; +def R41 : AMDILReg<41, "r41">, DwarfRegNum<[41]>; +def R42 : AMDILReg<42, "r42">, DwarfRegNum<[42]>; +def R43 : AMDILReg<43, "r43">, DwarfRegNum<[43]>; +def R44 : AMDILReg<44, "r44">, DwarfRegNum<[44]>; +def R45 : AMDILReg<45, "r45">, DwarfRegNum<[45]>; +def R46 : AMDILReg<46, "r46">, DwarfRegNum<[46]>; +def R47 : AMDILReg<47, "r47">, DwarfRegNum<[47]>; +def R48 : AMDILReg<48, "r48">, DwarfRegNum<[48]>; +def R49 : AMDILReg<49, "r49">, DwarfRegNum<[49]>; +def R50 : AMDILReg<50, "r50">, DwarfRegNum<[50]>; +def R51 : AMDILReg<51, "r51">, DwarfRegNum<[51]>; +def R52 : AMDILReg<52, "r52">, DwarfRegNum<[52]>; +def R53 : AMDILReg<53, "r53">, DwarfRegNum<[53]>; +def R54 : AMDILReg<54, "r54">, DwarfRegNum<[54]>; +def R55 : AMDILReg<55, "r55">, DwarfRegNum<[55]>; +def R56 : AMDILReg<56, "r56">, DwarfRegNum<[56]>; +def R57 : AMDILReg<57, "r57">, DwarfRegNum<[57]>; +def R58 : AMDILReg<58, "r58">, DwarfRegNum<[58]>; +def R59 : AMDILReg<59, "r59">, DwarfRegNum<[59]>; +def R60 : AMDILReg<60, "r60">, DwarfRegNum<[60]>; +def R61 : AMDILReg<61, "r61">, DwarfRegNum<[61]>; +def R62 : AMDILReg<62, "r62">, DwarfRegNum<[62]>; +def R63 : AMDILReg<63, "r63">, DwarfRegNum<[63]>; +def R64 : AMDILReg<64, "r64">, DwarfRegNum<[64]>; +def R65 : AMDILReg<65, "r65">, DwarfRegNum<[65]>; +def R66 : AMDILReg<66, "r66">, DwarfRegNum<[66]>; +def R67 : AMDILReg<67, "r67">, DwarfRegNum<[67]>; +def R68 : AMDILReg<68, "r68">, DwarfRegNum<[68]>; +def R69 : AMDILReg<69, "r69">, DwarfRegNum<[69]>; +def R70 : AMDILReg<70, "r70">, DwarfRegNum<[70]>; +def R71 : AMDILReg<71, "r71">, DwarfRegNum<[71]>; +def R72 : AMDILReg<72, "r72">, DwarfRegNum<[72]>; +def R73 : AMDILReg<73, "r73">, DwarfRegNum<[73]>; +def R74 : AMDILReg<74, "r74">, DwarfRegNum<[74]>; +def R75 : AMDILReg<75, "r75">, DwarfRegNum<[75]>; +def R76 : AMDILReg<76, "r76">, DwarfRegNum<[76]>; +def R77 : AMDILReg<77, "r77">, DwarfRegNum<[77]>; +def R78 : AMDILReg<78, "r78">, DwarfRegNum<[78]>; +def R79 : AMDILReg<79, "r79">, DwarfRegNum<[79]>; +def R80 : AMDILReg<80, "r80">, DwarfRegNum<[80]>; +def R81 : AMDILReg<81, "r81">, DwarfRegNum<[81]>; +def R82 : AMDILReg<82, "r82">, DwarfRegNum<[82]>; +def R83 : AMDILReg<83, "r83">, DwarfRegNum<[83]>; +def R84 : AMDILReg<84, "r84">, DwarfRegNum<[84]>; +def R85 : AMDILReg<85, "r85">, DwarfRegNum<[85]>; +def R86 : AMDILReg<86, "r86">, DwarfRegNum<[86]>; +def R87 : AMDILReg<87, "r87">, DwarfRegNum<[87]>; +def R88 : AMDILReg<88, "r88">, DwarfRegNum<[88]>; +def R89 : AMDILReg<89, "r89">, DwarfRegNum<[89]>; +def R90 : AMDILReg<90, "r90">, DwarfRegNum<[90]>; +def R91 : AMDILReg<91, "r91">, DwarfRegNum<[91]>; +def R92 : AMDILReg<92, "r92">, DwarfRegNum<[92]>; +def R93 : AMDILReg<93, "r93">, DwarfRegNum<[93]>; +def R94 : AMDILReg<94, "r94">, DwarfRegNum<[94]>; +def R95 : AMDILReg<95, "r95">, DwarfRegNum<[95]>; +def R96 : AMDILReg<96, "r96">, DwarfRegNum<[96]>; +def R97 : AMDILReg<97, "r97">, DwarfRegNum<[97]>; +def R98 : AMDILReg<98, "r98">, DwarfRegNum<[98]>; +def R99 : AMDILReg<99, "r99">, DwarfRegNum<[99]>; +def R100 : AMDILReg<100, "r100">, DwarfRegNum<[100]>; +def R101 : AMDILReg<101, "r101">, DwarfRegNum<[101]>; +def R102 : AMDILReg<102, "r102">, DwarfRegNum<[102]>; +def R103 : AMDILReg<103, "r103">, DwarfRegNum<[103]>; +def R104 : AMDILReg<104, "r104">, DwarfRegNum<[104]>; +def R105 : AMDILReg<105, "r105">, DwarfRegNum<[105]>; +def R106 : AMDILReg<106, "r106">, DwarfRegNum<[106]>; +def R107 : AMDILReg<107, "r107">, DwarfRegNum<[107]>; +def R108 : AMDILReg<108, "r108">, DwarfRegNum<[108]>; +def R109 : AMDILReg<109, "r109">, DwarfRegNum<[109]>; +def R110 : AMDILReg<110, "r110">, DwarfRegNum<[110]>; +def R111 : AMDILReg<111, "r111">, DwarfRegNum<[111]>; +def R112 : AMDILReg<112, "r112">, DwarfRegNum<[112]>; +def R113 : AMDILReg<113, "r113">, DwarfRegNum<[113]>; +def R114 : AMDILReg<114, "r114">, DwarfRegNum<[114]>; +def R115 : AMDILReg<115, "r115">, DwarfRegNum<[115]>; +def R116 : AMDILReg<116, "r116">, DwarfRegNum<[116]>; +def R117 : AMDILReg<117, "r117">, DwarfRegNum<[117]>; +def R118 : AMDILReg<118, "r118">, DwarfRegNum<[118]>; +def R119 : AMDILReg<119, "r119">, DwarfRegNum<[119]>; +def R120 : AMDILReg<120, "r120">, DwarfRegNum<[120]>; +def R121 : AMDILReg<121, "r121">, DwarfRegNum<[121]>; +def R122 : AMDILReg<122, "r122">, DwarfRegNum<[122]>; +def R123 : AMDILReg<123, "r123">, DwarfRegNum<[123]>; +def R124 : AMDILReg<124, "r124">, DwarfRegNum<[124]>; +def R125 : AMDILReg<125, "r125">, DwarfRegNum<[125]>; +def R126 : AMDILReg<126, "r126">, DwarfRegNum<[126]>; +def R127 : AMDILReg<127, "r127">, DwarfRegNum<[127]>; +def R128 : AMDILReg<128, "r128">, DwarfRegNum<[128]>; +def R129 : AMDILReg<129, "r129">, DwarfRegNum<[129]>; +def R130 : AMDILReg<130, "r130">, DwarfRegNum<[130]>; +def R131 : AMDILReg<131, "r131">, DwarfRegNum<[131]>; +def R132 : AMDILReg<132, "r132">, DwarfRegNum<[132]>; +def R133 : AMDILReg<133, "r133">, DwarfRegNum<[133]>; +def R134 : AMDILReg<134, "r134">, DwarfRegNum<[134]>; +def R135 : AMDILReg<135, "r135">, DwarfRegNum<[135]>; +def R136 : AMDILReg<136, "r136">, DwarfRegNum<[136]>; +def R137 : AMDILReg<137, "r137">, DwarfRegNum<[137]>; +def R138 : AMDILReg<138, "r138">, DwarfRegNum<[138]>; +def R139 : AMDILReg<139, "r139">, DwarfRegNum<[139]>; +def R140 : AMDILReg<140, "r140">, DwarfRegNum<[140]>; +def R141 : AMDILReg<141, "r141">, DwarfRegNum<[141]>; +def R142 : AMDILReg<142, "r142">, DwarfRegNum<[142]>; +def R143 : AMDILReg<143, "r143">, DwarfRegNum<[143]>; +def R144 : AMDILReg<144, "r144">, DwarfRegNum<[144]>; +def R145 : AMDILReg<145, "r145">, DwarfRegNum<[145]>; +def R146 : AMDILReg<146, "r146">, DwarfRegNum<[146]>; +def R147 : AMDILReg<147, "r147">, DwarfRegNum<[147]>; +def R148 : AMDILReg<148, "r148">, DwarfRegNum<[148]>; +def R149 : AMDILReg<149, "r149">, DwarfRegNum<[149]>; +def R150 : AMDILReg<150, "r150">, DwarfRegNum<[150]>; +def R151 : AMDILReg<151, "r151">, DwarfRegNum<[151]>; +def R152 : AMDILReg<152, "r152">, DwarfRegNum<[152]>; +def R153 : AMDILReg<153, "r153">, DwarfRegNum<[153]>; +def R154 : AMDILReg<154, "r154">, DwarfRegNum<[154]>; +def R155 : AMDILReg<155, "r155">, DwarfRegNum<[155]>; +def R156 : AMDILReg<156, "r156">, DwarfRegNum<[156]>; +def R157 : AMDILReg<157, "r157">, DwarfRegNum<[157]>; +def R158 : AMDILReg<158, "r158">, DwarfRegNum<[158]>; +def R159 : AMDILReg<159, "r159">, DwarfRegNum<[159]>; +def R160 : AMDILReg<160, "r160">, DwarfRegNum<[160]>; +def R161 : AMDILReg<161, "r161">, DwarfRegNum<[161]>; +def R162 : AMDILReg<162, "r162">, DwarfRegNum<[162]>; +def R163 : AMDILReg<163, "r163">, DwarfRegNum<[163]>; +def R164 : AMDILReg<164, "r164">, DwarfRegNum<[164]>; +def R165 : AMDILReg<165, "r165">, DwarfRegNum<[165]>; +def R166 : AMDILReg<166, "r166">, DwarfRegNum<[166]>; +def R167 : AMDILReg<167, "r167">, DwarfRegNum<[167]>; +def R168 : AMDILReg<168, "r168">, DwarfRegNum<[168]>; +def R169 : AMDILReg<169, "r169">, DwarfRegNum<[169]>; +def R170 : AMDILReg<170, "r170">, DwarfRegNum<[170]>; +def R171 : AMDILReg<171, "r171">, DwarfRegNum<[171]>; +def R172 : AMDILReg<172, "r172">, DwarfRegNum<[172]>; +def R173 : AMDILReg<173, "r173">, DwarfRegNum<[173]>; +def R174 : AMDILReg<174, "r174">, DwarfRegNum<[174]>; +def R175 : AMDILReg<175, "r175">, DwarfRegNum<[175]>; +def R176 : AMDILReg<176, "r176">, DwarfRegNum<[176]>; +def R177 : AMDILReg<177, "r177">, DwarfRegNum<[177]>; +def R178 : AMDILReg<178, "r178">, DwarfRegNum<[178]>; +def R179 : AMDILReg<179, "r179">, DwarfRegNum<[179]>; +def R180 : AMDILReg<180, "r180">, DwarfRegNum<[180]>; +def R181 : AMDILReg<181, "r181">, DwarfRegNum<[181]>; +def R182 : AMDILReg<182, "r182">, DwarfRegNum<[182]>; +def R183 : AMDILReg<183, "r183">, DwarfRegNum<[183]>; +def R184 : AMDILReg<184, "r184">, DwarfRegNum<[184]>; +def R185 : AMDILReg<185, "r185">, DwarfRegNum<[185]>; +def R186 : AMDILReg<186, "r186">, DwarfRegNum<[186]>; +def R187 : AMDILReg<187, "r187">, DwarfRegNum<[187]>; +def R188 : AMDILReg<188, "r188">, DwarfRegNum<[188]>; +def R189 : AMDILReg<189, "r189">, DwarfRegNum<[189]>; +def R190 : AMDILReg<190, "r190">, DwarfRegNum<[190]>; +def R191 : AMDILReg<191, "r191">, DwarfRegNum<[191]>; +def R192 : AMDILReg<192, "r192">, DwarfRegNum<[192]>; +def R193 : AMDILReg<193, "r193">, DwarfRegNum<[193]>; +def R194 : AMDILReg<194, "r194">, DwarfRegNum<[194]>; +def R195 : AMDILReg<195, "r195">, DwarfRegNum<[195]>; +def R196 : AMDILReg<196, "r196">, DwarfRegNum<[196]>; +def R197 : AMDILReg<197, "r197">, DwarfRegNum<[197]>; +def R198 : AMDILReg<198, "r198">, DwarfRegNum<[198]>; +def R199 : AMDILReg<199, "r199">, DwarfRegNum<[199]>; +def R200 : AMDILReg<200, "r200">, DwarfRegNum<[200]>; +def R201 : AMDILReg<201, "r201">, DwarfRegNum<[201]>; +def R202 : AMDILReg<202, "r202">, DwarfRegNum<[202]>; +def R203 : AMDILReg<203, "r203">, DwarfRegNum<[203]>; +def R204 : AMDILReg<204, "r204">, DwarfRegNum<[204]>; +def R205 : AMDILReg<205, "r205">, DwarfRegNum<[205]>; +def R206 : AMDILReg<206, "r206">, DwarfRegNum<[206]>; +def R207 : AMDILReg<207, "r207">, DwarfRegNum<[207]>; +def R208 : AMDILReg<208, "r208">, DwarfRegNum<[208]>; +def R209 : AMDILReg<209, "r209">, DwarfRegNum<[209]>; +def R210 : AMDILReg<210, "r210">, DwarfRegNum<[210]>; +def R211 : AMDILReg<211, "r211">, DwarfRegNum<[211]>; +def R212 : AMDILReg<212, "r212">, DwarfRegNum<[212]>; +def R213 : AMDILReg<213, "r213">, DwarfRegNum<[213]>; +def R214 : AMDILReg<214, "r214">, DwarfRegNum<[214]>; +def R215 : AMDILReg<215, "r215">, DwarfRegNum<[215]>; +def R216 : AMDILReg<216, "r216">, DwarfRegNum<[216]>; +def R217 : AMDILReg<217, "r217">, DwarfRegNum<[217]>; +def R218 : AMDILReg<218, "r218">, DwarfRegNum<[218]>; +def R219 : AMDILReg<219, "r219">, DwarfRegNum<[219]>; +def R220 : AMDILReg<220, "r220">, DwarfRegNum<[220]>; +def R221 : AMDILReg<221, "r221">, DwarfRegNum<[221]>; +def R222 : AMDILReg<222, "r222">, DwarfRegNum<[222]>; +def R223 : AMDILReg<223, "r223">, DwarfRegNum<[223]>; +def R224 : AMDILReg<224, "r224">, DwarfRegNum<[224]>; +def R225 : AMDILReg<225, "r225">, DwarfRegNum<[225]>; +def R226 : AMDILReg<226, "r226">, DwarfRegNum<[226]>; +def R227 : AMDILReg<227, "r227">, DwarfRegNum<[227]>; +def R228 : AMDILReg<228, "r228">, DwarfRegNum<[228]>; +def R229 : AMDILReg<229, "r229">, DwarfRegNum<[229]>; +def R230 : AMDILReg<230, "r230">, DwarfRegNum<[230]>; +def R231 : AMDILReg<231, "r231">, DwarfRegNum<[231]>; +def R232 : AMDILReg<232, "r232">, DwarfRegNum<[232]>; +def R233 : AMDILReg<233, "r233">, DwarfRegNum<[233]>; +def R234 : AMDILReg<234, "r234">, DwarfRegNum<[234]>; +def R235 : AMDILReg<235, "r235">, DwarfRegNum<[235]>; +def R236 : AMDILReg<236, "r236">, DwarfRegNum<[236]>; +def R237 : AMDILReg<237, "r237">, DwarfRegNum<[237]>; +def R238 : AMDILReg<238, "r238">, DwarfRegNum<[238]>; +def R239 : AMDILReg<239, "r239">, DwarfRegNum<[239]>; +def R240 : AMDILReg<240, "r240">, DwarfRegNum<[240]>; +def R241 : AMDILReg<241, "r241">, DwarfRegNum<[241]>; +def R242 : AMDILReg<242, "r242">, DwarfRegNum<[242]>; +def R243 : AMDILReg<243, "r243">, DwarfRegNum<[243]>; +def R244 : AMDILReg<244, "r244">, DwarfRegNum<[244]>; +def R245 : AMDILReg<245, "r245">, DwarfRegNum<[245]>; +def R246 : AMDILReg<246, "r246">, DwarfRegNum<[246]>; +def R247 : AMDILReg<247, "r247">, DwarfRegNum<[247]>; +def R248 : AMDILReg<248, "r248">, DwarfRegNum<[248]>; +def R249 : AMDILReg<249, "r249">, DwarfRegNum<[249]>; +def R250 : AMDILReg<250, "r250">, DwarfRegNum<[250]>; +def R251 : AMDILReg<251, "r251">, DwarfRegNum<[251]>; +def R252 : AMDILReg<252, "r252">, DwarfRegNum<[252]>; +def R253 : AMDILReg<253, "r253">, DwarfRegNum<[253]>; +def R254 : AMDILReg<254, "r254">, DwarfRegNum<[254]>; +def R255 : AMDILReg<255, "r255">, DwarfRegNum<[255]>; +def R256 : AMDILReg<256, "r256">, DwarfRegNum<[256]>; +def R257 : AMDILReg<257, "r257">, DwarfRegNum<[257]>; +def R258 : AMDILReg<258, "r258">, DwarfRegNum<[258]>; +def R259 : AMDILReg<259, "r259">, DwarfRegNum<[259]>; +def R260 : AMDILReg<260, "r260">, DwarfRegNum<[260]>; +def R261 : AMDILReg<261, "r261">, DwarfRegNum<[261]>; +def R262 : AMDILReg<262, "r262">, DwarfRegNum<[262]>; +def R263 : AMDILReg<263, "r263">, DwarfRegNum<[263]>; +def R264 : AMDILReg<264, "r264">, DwarfRegNum<[264]>; +def R265 : AMDILReg<265, "r265">, DwarfRegNum<[265]>; +def R266 : AMDILReg<266, "r266">, DwarfRegNum<[266]>; +def R267 : AMDILReg<267, "r267">, DwarfRegNum<[267]>; +def R268 : AMDILReg<268, "r268">, DwarfRegNum<[268]>; +def R269 : AMDILReg<269, "r269">, DwarfRegNum<[269]>; +def R270 : AMDILReg<270, "r270">, DwarfRegNum<[270]>; +def R271 : AMDILReg<271, "r271">, DwarfRegNum<[271]>; +def R272 : AMDILReg<272, "r272">, DwarfRegNum<[272]>; +def R273 : AMDILReg<273, "r273">, DwarfRegNum<[273]>; +def R274 : AMDILReg<274, "r274">, DwarfRegNum<[274]>; +def R275 : AMDILReg<275, "r275">, DwarfRegNum<[275]>; +def R276 : AMDILReg<276, "r276">, DwarfRegNum<[276]>; +def R277 : AMDILReg<277, "r277">, DwarfRegNum<[277]>; +def R278 : AMDILReg<278, "r278">, DwarfRegNum<[278]>; +def R279 : AMDILReg<279, "r279">, DwarfRegNum<[279]>; +def R280 : AMDILReg<280, "r280">, DwarfRegNum<[280]>; +def R281 : AMDILReg<281, "r281">, DwarfRegNum<[281]>; +def R282 : AMDILReg<282, "r282">, DwarfRegNum<[282]>; +def R283 : AMDILReg<283, "r283">, DwarfRegNum<[283]>; +def R284 : AMDILReg<284, "r284">, DwarfRegNum<[284]>; +def R285 : AMDILReg<285, "r285">, DwarfRegNum<[285]>; +def R286 : AMDILReg<286, "r286">, DwarfRegNum<[286]>; +def R287 : AMDILReg<287, "r287">, DwarfRegNum<[287]>; +def R288 : AMDILReg<288, "r288">, DwarfRegNum<[288]>; +def R289 : AMDILReg<289, "r289">, DwarfRegNum<[289]>; +def R290 : AMDILReg<290, "r290">, DwarfRegNum<[290]>; +def R291 : AMDILReg<291, "r291">, DwarfRegNum<[291]>; +def R292 : AMDILReg<292, "r292">, DwarfRegNum<[292]>; +def R293 : AMDILReg<293, "r293">, DwarfRegNum<[293]>; +def R294 : AMDILReg<294, "r294">, DwarfRegNum<[294]>; +def R295 : AMDILReg<295, "r295">, DwarfRegNum<[295]>; +def R296 : AMDILReg<296, "r296">, DwarfRegNum<[296]>; +def R297 : AMDILReg<297, "r297">, DwarfRegNum<[297]>; +def R298 : AMDILReg<298, "r298">, DwarfRegNum<[298]>; +def R299 : AMDILReg<299, "r299">, DwarfRegNum<[299]>; +def R300 : AMDILReg<300, "r300">, DwarfRegNum<[300]>; +def R301 : AMDILReg<301, "r301">, DwarfRegNum<[301]>; +def R302 : AMDILReg<302, "r302">, DwarfRegNum<[302]>; +def R303 : AMDILReg<303, "r303">, DwarfRegNum<[303]>; +def R304 : AMDILReg<304, "r304">, DwarfRegNum<[304]>; +def R305 : AMDILReg<305, "r305">, DwarfRegNum<[305]>; +def R306 : AMDILReg<306, "r306">, DwarfRegNum<[306]>; +def R307 : AMDILReg<307, "r307">, DwarfRegNum<[307]>; +def R308 : AMDILReg<308, "r308">, DwarfRegNum<[308]>; +def R309 : AMDILReg<309, "r309">, DwarfRegNum<[309]>; +def R310 : AMDILReg<310, "r310">, DwarfRegNum<[310]>; +def R311 : AMDILReg<311, "r311">, DwarfRegNum<[311]>; +def R312 : AMDILReg<312, "r312">, DwarfRegNum<[312]>; +def R313 : AMDILReg<313, "r313">, DwarfRegNum<[313]>; +def R314 : AMDILReg<314, "r314">, DwarfRegNum<[314]>; +def R315 : AMDILReg<315, "r315">, DwarfRegNum<[315]>; +def R316 : AMDILReg<316, "r316">, DwarfRegNum<[316]>; +def R317 : AMDILReg<317, "r317">, DwarfRegNum<[317]>; +def R318 : AMDILReg<318, "r318">, DwarfRegNum<[318]>; +def R319 : AMDILReg<319, "r319">, DwarfRegNum<[319]>; +def R320 : AMDILReg<320, "r320">, DwarfRegNum<[320]>; +def R321 : AMDILReg<321, "r321">, DwarfRegNum<[321]>; +def R322 : AMDILReg<322, "r322">, DwarfRegNum<[322]>; +def R323 : AMDILReg<323, "r323">, DwarfRegNum<[323]>; +def R324 : AMDILReg<324, "r324">, DwarfRegNum<[324]>; +def R325 : AMDILReg<325, "r325">, DwarfRegNum<[325]>; +def R326 : AMDILReg<326, "r326">, DwarfRegNum<[326]>; +def R327 : AMDILReg<327, "r327">, DwarfRegNum<[327]>; +def R328 : AMDILReg<328, "r328">, DwarfRegNum<[328]>; +def R329 : AMDILReg<329, "r329">, DwarfRegNum<[329]>; +def R330 : AMDILReg<330, "r330">, DwarfRegNum<[330]>; +def R331 : AMDILReg<331, "r331">, DwarfRegNum<[331]>; +def R332 : AMDILReg<332, "r332">, DwarfRegNum<[332]>; +def R333 : AMDILReg<333, "r333">, DwarfRegNum<[333]>; +def R334 : AMDILReg<334, "r334">, DwarfRegNum<[334]>; +def R335 : AMDILReg<335, "r335">, DwarfRegNum<[335]>; +def R336 : AMDILReg<336, "r336">, DwarfRegNum<[336]>; +def R337 : AMDILReg<337, "r337">, DwarfRegNum<[337]>; +def R338 : AMDILReg<338, "r338">, DwarfRegNum<[338]>; +def R339 : AMDILReg<339, "r339">, DwarfRegNum<[339]>; +def R340 : AMDILReg<340, "r340">, DwarfRegNum<[340]>; +def R341 : AMDILReg<341, "r341">, DwarfRegNum<[341]>; +def R342 : AMDILReg<342, "r342">, DwarfRegNum<[342]>; +def R343 : AMDILReg<343, "r343">, DwarfRegNum<[343]>; +def R344 : AMDILReg<344, "r344">, DwarfRegNum<[344]>; +def R345 : AMDILReg<345, "r345">, DwarfRegNum<[345]>; +def R346 : AMDILReg<346, "r346">, DwarfRegNum<[346]>; +def R347 : AMDILReg<347, "r347">, DwarfRegNum<[347]>; +def R348 : AMDILReg<348, "r348">, DwarfRegNum<[348]>; +def R349 : AMDILReg<349, "r349">, DwarfRegNum<[349]>; +def R350 : AMDILReg<350, "r350">, DwarfRegNum<[350]>; +def R351 : AMDILReg<351, "r351">, DwarfRegNum<[351]>; +def R352 : AMDILReg<352, "r352">, DwarfRegNum<[352]>; +def R353 : AMDILReg<353, "r353">, DwarfRegNum<[353]>; +def R354 : AMDILReg<354, "r354">, DwarfRegNum<[354]>; +def R355 : AMDILReg<355, "r355">, DwarfRegNum<[355]>; +def R356 : AMDILReg<356, "r356">, DwarfRegNum<[356]>; +def R357 : AMDILReg<357, "r357">, DwarfRegNum<[357]>; +def R358 : AMDILReg<358, "r358">, DwarfRegNum<[358]>; +def R359 : AMDILReg<359, "r359">, DwarfRegNum<[359]>; +def R360 : AMDILReg<360, "r360">, DwarfRegNum<[360]>; +def R361 : AMDILReg<361, "r361">, DwarfRegNum<[361]>; +def R362 : AMDILReg<362, "r362">, DwarfRegNum<[362]>; +def R363 : AMDILReg<363, "r363">, DwarfRegNum<[363]>; +def R364 : AMDILReg<364, "r364">, DwarfRegNum<[364]>; +def R365 : AMDILReg<365, "r365">, DwarfRegNum<[365]>; +def R366 : AMDILReg<366, "r366">, DwarfRegNum<[366]>; +def R367 : AMDILReg<367, "r367">, DwarfRegNum<[367]>; +def R368 : AMDILReg<368, "r368">, DwarfRegNum<[368]>; +def R369 : AMDILReg<369, "r369">, DwarfRegNum<[369]>; +def R370 : AMDILReg<370, "r370">, DwarfRegNum<[370]>; +def R371 : AMDILReg<371, "r371">, DwarfRegNum<[371]>; +def R372 : AMDILReg<372, "r372">, DwarfRegNum<[372]>; +def R373 : AMDILReg<373, "r373">, DwarfRegNum<[373]>; +def R374 : AMDILReg<374, "r374">, DwarfRegNum<[374]>; +def R375 : AMDILReg<375, "r375">, DwarfRegNum<[375]>; +def R376 : AMDILReg<376, "r376">, DwarfRegNum<[376]>; +def R377 : AMDILReg<377, "r377">, DwarfRegNum<[377]>; +def R378 : AMDILReg<378, "r378">, DwarfRegNum<[378]>; +def R379 : AMDILReg<379, "r379">, DwarfRegNum<[379]>; +def R380 : AMDILReg<380, "r380">, DwarfRegNum<[380]>; +def R381 : AMDILReg<381, "r381">, DwarfRegNum<[381]>; +def R382 : AMDILReg<382, "r382">, DwarfRegNum<[382]>; +def R383 : AMDILReg<383, "r383">, DwarfRegNum<[383]>; +def R384 : AMDILReg<384, "r384">, DwarfRegNum<[384]>; +def R385 : AMDILReg<385, "r385">, DwarfRegNum<[385]>; +def R386 : AMDILReg<386, "r386">, DwarfRegNum<[386]>; +def R387 : AMDILReg<387, "r387">, DwarfRegNum<[387]>; +def R388 : AMDILReg<388, "r388">, DwarfRegNum<[388]>; +def R389 : AMDILReg<389, "r389">, DwarfRegNum<[389]>; +def R390 : AMDILReg<390, "r390">, DwarfRegNum<[390]>; +def R391 : AMDILReg<391, "r391">, DwarfRegNum<[391]>; +def R392 : AMDILReg<392, "r392">, DwarfRegNum<[392]>; +def R393 : AMDILReg<393, "r393">, DwarfRegNum<[393]>; +def R394 : AMDILReg<394, "r394">, DwarfRegNum<[394]>; +def R395 : AMDILReg<395, "r395">, DwarfRegNum<[395]>; +def R396 : AMDILReg<396, "r396">, DwarfRegNum<[396]>; +def R397 : AMDILReg<397, "r397">, DwarfRegNum<[397]>; +def R398 : AMDILReg<398, "r398">, DwarfRegNum<[398]>; +def R399 : AMDILReg<399, "r399">, DwarfRegNum<[399]>; +def R400 : AMDILReg<400, "r400">, DwarfRegNum<[400]>; +def R401 : AMDILReg<401, "r401">, DwarfRegNum<[401]>; +def R402 : AMDILReg<402, "r402">, DwarfRegNum<[402]>; +def R403 : AMDILReg<403, "r403">, DwarfRegNum<[403]>; +def R404 : AMDILReg<404, "r404">, DwarfRegNum<[404]>; +def R405 : AMDILReg<405, "r405">, DwarfRegNum<[405]>; +def R406 : AMDILReg<406, "r406">, DwarfRegNum<[406]>; +def R407 : AMDILReg<407, "r407">, DwarfRegNum<[407]>; +def R408 : AMDILReg<408, "r408">, DwarfRegNum<[408]>; +def R409 : AMDILReg<409, "r409">, DwarfRegNum<[409]>; +def R410 : AMDILReg<410, "r410">, DwarfRegNum<[410]>; +def R411 : AMDILReg<411, "r411">, DwarfRegNum<[411]>; +def R412 : AMDILReg<412, "r412">, DwarfRegNum<[412]>; +def R413 : AMDILReg<413, "r413">, DwarfRegNum<[413]>; +def R414 : AMDILReg<414, "r414">, DwarfRegNum<[414]>; +def R415 : AMDILReg<415, "r415">, DwarfRegNum<[415]>; +def R416 : AMDILReg<416, "r416">, DwarfRegNum<[416]>; +def R417 : AMDILReg<417, "r417">, DwarfRegNum<[417]>; +def R418 : AMDILReg<418, "r418">, DwarfRegNum<[418]>; +def R419 : AMDILReg<419, "r419">, DwarfRegNum<[419]>; +def R420 : AMDILReg<420, "r420">, DwarfRegNum<[420]>; +def R421 : AMDILReg<421, "r421">, DwarfRegNum<[421]>; +def R422 : AMDILReg<422, "r422">, DwarfRegNum<[422]>; +def R423 : AMDILReg<423, "r423">, DwarfRegNum<[423]>; +def R424 : AMDILReg<424, "r424">, DwarfRegNum<[424]>; +def R425 : AMDILReg<425, "r425">, DwarfRegNum<[425]>; +def R426 : AMDILReg<426, "r426">, DwarfRegNum<[426]>; +def R427 : AMDILReg<427, "r427">, DwarfRegNum<[427]>; +def R428 : AMDILReg<428, "r428">, DwarfRegNum<[428]>; +def R429 : AMDILReg<429, "r429">, DwarfRegNum<[429]>; +def R430 : AMDILReg<430, "r430">, DwarfRegNum<[430]>; +def R431 : AMDILReg<431, "r431">, DwarfRegNum<[431]>; +def R432 : AMDILReg<432, "r432">, DwarfRegNum<[432]>; +def R433 : AMDILReg<433, "r433">, DwarfRegNum<[433]>; +def R434 : AMDILReg<434, "r434">, DwarfRegNum<[434]>; +def R435 : AMDILReg<435, "r435">, DwarfRegNum<[435]>; +def R436 : AMDILReg<436, "r436">, DwarfRegNum<[436]>; +def R437 : AMDILReg<437, "r437">, DwarfRegNum<[437]>; +def R438 : AMDILReg<438, "r438">, DwarfRegNum<[438]>; +def R439 : AMDILReg<439, "r439">, DwarfRegNum<[439]>; +def R440 : AMDILReg<440, "r440">, DwarfRegNum<[440]>; +def R441 : AMDILReg<441, "r441">, DwarfRegNum<[441]>; +def R442 : AMDILReg<442, "r442">, DwarfRegNum<[442]>; +def R443 : AMDILReg<443, "r443">, DwarfRegNum<[443]>; +def R444 : AMDILReg<444, "r444">, DwarfRegNum<[444]>; +def R445 : AMDILReg<445, "r445">, DwarfRegNum<[445]>; +def R446 : AMDILReg<446, "r446">, DwarfRegNum<[446]>; +def R447 : AMDILReg<447, "r447">, DwarfRegNum<[447]>; +def R448 : AMDILReg<448, "r448">, DwarfRegNum<[448]>; +def R449 : AMDILReg<449, "r449">, DwarfRegNum<[449]>; +def R450 : AMDILReg<450, "r450">, DwarfRegNum<[450]>; +def R451 : AMDILReg<451, "r451">, DwarfRegNum<[451]>; +def R452 : AMDILReg<452, "r452">, DwarfRegNum<[452]>; +def R453 : AMDILReg<453, "r453">, DwarfRegNum<[453]>; +def R454 : AMDILReg<454, "r454">, DwarfRegNum<[454]>; +def R455 : AMDILReg<455, "r455">, DwarfRegNum<[455]>; +def R456 : AMDILReg<456, "r456">, DwarfRegNum<[456]>; +def R457 : AMDILReg<457, "r457">, DwarfRegNum<[457]>; +def R458 : AMDILReg<458, "r458">, DwarfRegNum<[458]>; +def R459 : AMDILReg<459, "r459">, DwarfRegNum<[459]>; +def R460 : AMDILReg<460, "r460">, DwarfRegNum<[460]>; +def R461 : AMDILReg<461, "r461">, DwarfRegNum<[461]>; +def R462 : AMDILReg<462, "r462">, DwarfRegNum<[462]>; +def R463 : AMDILReg<463, "r463">, DwarfRegNum<[463]>; +def R464 : AMDILReg<464, "r464">, DwarfRegNum<[464]>; +def R465 : AMDILReg<465, "r465">, DwarfRegNum<[465]>; +def R466 : AMDILReg<466, "r466">, DwarfRegNum<[466]>; +def R467 : AMDILReg<467, "r467">, DwarfRegNum<[467]>; +def R468 : AMDILReg<468, "r468">, DwarfRegNum<[468]>; +def R469 : AMDILReg<469, "r469">, DwarfRegNum<[469]>; +def R470 : AMDILReg<470, "r470">, DwarfRegNum<[470]>; +def R471 : AMDILReg<471, "r471">, DwarfRegNum<[471]>; +def R472 : AMDILReg<472, "r472">, DwarfRegNum<[472]>; +def R473 : AMDILReg<473, "r473">, DwarfRegNum<[473]>; +def R474 : AMDILReg<474, "r474">, DwarfRegNum<[474]>; +def R475 : AMDILReg<475, "r475">, DwarfRegNum<[475]>; +def R476 : AMDILReg<476, "r476">, DwarfRegNum<[476]>; +def R477 : AMDILReg<477, "r477">, DwarfRegNum<[477]>; +def R478 : AMDILReg<478, "r478">, DwarfRegNum<[478]>; +def R479 : AMDILReg<479, "r479">, DwarfRegNum<[479]>; +def R480 : AMDILReg<480, "r480">, DwarfRegNum<[480]>; +def R481 : AMDILReg<481, "r481">, DwarfRegNum<[481]>; +def R482 : AMDILReg<482, "r482">, DwarfRegNum<[482]>; +def R483 : AMDILReg<483, "r483">, DwarfRegNum<[483]>; +def R484 : AMDILReg<484, "r484">, DwarfRegNum<[484]>; +def R485 : AMDILReg<485, "r485">, DwarfRegNum<[485]>; +def R486 : AMDILReg<486, "r486">, DwarfRegNum<[486]>; +def R487 : AMDILReg<487, "r487">, DwarfRegNum<[487]>; +def R488 : AMDILReg<488, "r488">, DwarfRegNum<[488]>; +def R489 : AMDILReg<489, "r489">, DwarfRegNum<[489]>; +def R490 : AMDILReg<490, "r490">, DwarfRegNum<[490]>; +def R491 : AMDILReg<491, "r491">, DwarfRegNum<[491]>; +def R492 : AMDILReg<492, "r492">, DwarfRegNum<[492]>; +def R493 : AMDILReg<493, "r493">, DwarfRegNum<[493]>; +def R494 : AMDILReg<494, "r494">, DwarfRegNum<[494]>; +def R495 : AMDILReg<495, "r495">, DwarfRegNum<[495]>; +def R496 : AMDILReg<496, "r496">, DwarfRegNum<[496]>; +def R497 : AMDILReg<497, "r497">, DwarfRegNum<[497]>; +def R498 : AMDILReg<498, "r498">, DwarfRegNum<[498]>; +def R499 : AMDILReg<499, "r499">, DwarfRegNum<[499]>; +def R500 : AMDILReg<500, "r500">, DwarfRegNum<[500]>; +def R501 : AMDILReg<501, "r501">, DwarfRegNum<[501]>; +def R502 : AMDILReg<502, "r502">, DwarfRegNum<[502]>; +def R503 : AMDILReg<503, "r503">, DwarfRegNum<[503]>; +def R504 : AMDILReg<504, "r504">, DwarfRegNum<[504]>; +def R505 : AMDILReg<505, "r505">, DwarfRegNum<[505]>; +def R506 : AMDILReg<506, "r506">, DwarfRegNum<[506]>; +def R507 : AMDILReg<507, "r507">, DwarfRegNum<[507]>; +def R508 : AMDILReg<508, "r508">, DwarfRegNum<[508]>; +def R509 : AMDILReg<509, "r509">, DwarfRegNum<[509]>; +def R510 : AMDILReg<510, "r510">, DwarfRegNum<[510]>; +def R511 : AMDILReg<511, "r511">, DwarfRegNum<[511]>; +def R512 : AMDILReg<512, "r512">, DwarfRegNum<[512]>; +def R513 : AMDILReg<513, "r513">, DwarfRegNum<[513]>; +def R514 : AMDILReg<514, "r514">, DwarfRegNum<[514]>; +def R515 : AMDILReg<515, "r515">, DwarfRegNum<[515]>; +def R516 : AMDILReg<516, "r516">, DwarfRegNum<[516]>; +def R517 : AMDILReg<517, "r517">, DwarfRegNum<[517]>; +def R518 : AMDILReg<518, "r518">, DwarfRegNum<[518]>; +def R519 : AMDILReg<519, "r519">, DwarfRegNum<[519]>; +def R520 : AMDILReg<520, "r520">, DwarfRegNum<[520]>; +def R521 : AMDILReg<521, "r521">, DwarfRegNum<[521]>; +def R522 : AMDILReg<522, "r522">, DwarfRegNum<[522]>; +def R523 : AMDILReg<523, "r523">, DwarfRegNum<[523]>; +def R524 : AMDILReg<524, "r524">, DwarfRegNum<[524]>; +def R525 : AMDILReg<525, "r525">, DwarfRegNum<[525]>; +def R526 : AMDILReg<526, "r526">, DwarfRegNum<[526]>; +def R527 : AMDILReg<527, "r527">, DwarfRegNum<[527]>; +def R528 : AMDILReg<528, "r528">, DwarfRegNum<[528]>; +def R529 : AMDILReg<529, "r529">, DwarfRegNum<[529]>; +def R530 : AMDILReg<530, "r530">, DwarfRegNum<[530]>; +def R531 : AMDILReg<531, "r531">, DwarfRegNum<[531]>; +def R532 : AMDILReg<532, "r532">, DwarfRegNum<[532]>; +def R533 : AMDILReg<533, "r533">, DwarfRegNum<[533]>; +def R534 : AMDILReg<534, "r534">, DwarfRegNum<[534]>; +def R535 : AMDILReg<535, "r535">, DwarfRegNum<[535]>; +def R536 : AMDILReg<536, "r536">, DwarfRegNum<[536]>; +def R537 : AMDILReg<537, "r537">, DwarfRegNum<[537]>; +def R538 : AMDILReg<538, "r538">, DwarfRegNum<[538]>; +def R539 : AMDILReg<539, "r539">, DwarfRegNum<[539]>; +def R540 : AMDILReg<540, "r540">, DwarfRegNum<[540]>; +def R541 : AMDILReg<541, "r541">, DwarfRegNum<[541]>; +def R542 : AMDILReg<542, "r542">, DwarfRegNum<[542]>; +def R543 : AMDILReg<543, "r543">, DwarfRegNum<[543]>; +def R544 : AMDILReg<544, "r544">, DwarfRegNum<[544]>; +def R545 : AMDILReg<545, "r545">, DwarfRegNum<[545]>; +def R546 : AMDILReg<546, "r546">, DwarfRegNum<[546]>; +def R547 : AMDILReg<547, "r547">, DwarfRegNum<[547]>; +def R548 : AMDILReg<548, "r548">, DwarfRegNum<[548]>; +def R549 : AMDILReg<549, "r549">, DwarfRegNum<[549]>; +def R550 : AMDILReg<550, "r550">, DwarfRegNum<[550]>; +def R551 : AMDILReg<551, "r551">, DwarfRegNum<[551]>; +def R552 : AMDILReg<552, "r552">, DwarfRegNum<[552]>; +def R553 : AMDILReg<553, "r553">, DwarfRegNum<[553]>; +def R554 : AMDILReg<554, "r554">, DwarfRegNum<[554]>; +def R555 : AMDILReg<555, "r555">, DwarfRegNum<[555]>; +def R556 : AMDILReg<556, "r556">, DwarfRegNum<[556]>; +def R557 : AMDILReg<557, "r557">, DwarfRegNum<[557]>; +def R558 : AMDILReg<558, "r558">, DwarfRegNum<[558]>; +def R559 : AMDILReg<559, "r559">, DwarfRegNum<[559]>; +def R560 : AMDILReg<560, "r560">, DwarfRegNum<[560]>; +def R561 : AMDILReg<561, "r561">, DwarfRegNum<[561]>; +def R562 : AMDILReg<562, "r562">, DwarfRegNum<[562]>; +def R563 : AMDILReg<563, "r563">, DwarfRegNum<[563]>; +def R564 : AMDILReg<564, "r564">, DwarfRegNum<[564]>; +def R565 : AMDILReg<565, "r565">, DwarfRegNum<[565]>; +def R566 : AMDILReg<566, "r566">, DwarfRegNum<[566]>; +def R567 : AMDILReg<567, "r567">, DwarfRegNum<[567]>; +def R568 : AMDILReg<568, "r568">, DwarfRegNum<[568]>; +def R569 : AMDILReg<569, "r569">, DwarfRegNum<[569]>; +def R570 : AMDILReg<570, "r570">, DwarfRegNum<[570]>; +def R571 : AMDILReg<571, "r571">, DwarfRegNum<[571]>; +def R572 : AMDILReg<572, "r572">, DwarfRegNum<[572]>; +def R573 : AMDILReg<573, "r573">, DwarfRegNum<[573]>; +def R574 : AMDILReg<574, "r574">, DwarfRegNum<[574]>; +def R575 : AMDILReg<575, "r575">, DwarfRegNum<[575]>; +def R576 : AMDILReg<576, "r576">, DwarfRegNum<[576]>; +def R577 : AMDILReg<577, "r577">, DwarfRegNum<[577]>; +def R578 : AMDILReg<578, "r578">, DwarfRegNum<[578]>; +def R579 : AMDILReg<579, "r579">, DwarfRegNum<[579]>; +def R580 : AMDILReg<580, "r580">, DwarfRegNum<[580]>; +def R581 : AMDILReg<581, "r581">, DwarfRegNum<[581]>; +def R582 : AMDILReg<582, "r582">, DwarfRegNum<[582]>; +def R583 : AMDILReg<583, "r583">, DwarfRegNum<[583]>; +def R584 : AMDILReg<584, "r584">, DwarfRegNum<[584]>; +def R585 : AMDILReg<585, "r585">, DwarfRegNum<[585]>; +def R586 : AMDILReg<586, "r586">, DwarfRegNum<[586]>; +def R587 : AMDILReg<587, "r587">, DwarfRegNum<[587]>; +def R588 : AMDILReg<588, "r588">, DwarfRegNum<[588]>; +def R589 : AMDILReg<589, "r589">, DwarfRegNum<[589]>; +def R590 : AMDILReg<590, "r590">, DwarfRegNum<[590]>; +def R591 : AMDILReg<591, "r591">, DwarfRegNum<[591]>; +def R592 : AMDILReg<592, "r592">, DwarfRegNum<[592]>; +def R593 : AMDILReg<593, "r593">, DwarfRegNum<[593]>; +def R594 : AMDILReg<594, "r594">, DwarfRegNum<[594]>; +def R595 : AMDILReg<595, "r595">, DwarfRegNum<[595]>; +def R596 : AMDILReg<596, "r596">, DwarfRegNum<[596]>; +def R597 : AMDILReg<597, "r597">, DwarfRegNum<[597]>; +def R598 : AMDILReg<598, "r598">, DwarfRegNum<[598]>; +def R599 : AMDILReg<599, "r599">, DwarfRegNum<[599]>; +def R600 : AMDILReg<600, "r600">, DwarfRegNum<[600]>; +def R601 : AMDILReg<601, "r601">, DwarfRegNum<[601]>; +def R602 : AMDILReg<602, "r602">, DwarfRegNum<[602]>; +def R603 : AMDILReg<603, "r603">, DwarfRegNum<[603]>; +def R604 : AMDILReg<604, "r604">, DwarfRegNum<[604]>; +def R605 : AMDILReg<605, "r605">, DwarfRegNum<[605]>; +def R606 : AMDILReg<606, "r606">, DwarfRegNum<[606]>; +def R607 : AMDILReg<607, "r607">, DwarfRegNum<[607]>; +def R608 : AMDILReg<608, "r608">, DwarfRegNum<[608]>; +def R609 : AMDILReg<609, "r609">, DwarfRegNum<[609]>; +def R610 : AMDILReg<610, "r610">, DwarfRegNum<[610]>; +def R611 : AMDILReg<611, "r611">, DwarfRegNum<[611]>; +def R612 : AMDILReg<612, "r612">, DwarfRegNum<[612]>; +def R613 : AMDILReg<613, "r613">, DwarfRegNum<[613]>; +def R614 : AMDILReg<614, "r614">, DwarfRegNum<[614]>; +def R615 : AMDILReg<615, "r615">, DwarfRegNum<[615]>; +def R616 : AMDILReg<616, "r616">, DwarfRegNum<[616]>; +def R617 : AMDILReg<617, "r617">, DwarfRegNum<[617]>; +def R618 : AMDILReg<618, "r618">, DwarfRegNum<[618]>; +def R619 : AMDILReg<619, "r619">, DwarfRegNum<[619]>; +def R620 : AMDILReg<620, "r620">, DwarfRegNum<[620]>; +def R621 : AMDILReg<621, "r621">, DwarfRegNum<[621]>; +def R622 : AMDILReg<622, "r622">, DwarfRegNum<[622]>; +def R623 : AMDILReg<623, "r623">, DwarfRegNum<[623]>; +def R624 : AMDILReg<624, "r624">, DwarfRegNum<[624]>; +def R625 : AMDILReg<625, "r625">, DwarfRegNum<[625]>; +def R626 : AMDILReg<626, "r626">, DwarfRegNum<[626]>; +def R627 : AMDILReg<627, "r627">, DwarfRegNum<[627]>; +def R628 : AMDILReg<628, "r628">, DwarfRegNum<[628]>; +def R629 : AMDILReg<629, "r629">, DwarfRegNum<[629]>; +def R630 : AMDILReg<630, "r630">, DwarfRegNum<[630]>; +def R631 : AMDILReg<631, "r631">, DwarfRegNum<[631]>; +def R632 : AMDILReg<632, "r632">, DwarfRegNum<[632]>; +def R633 : AMDILReg<633, "r633">, DwarfRegNum<[633]>; +def R634 : AMDILReg<634, "r634">, DwarfRegNum<[634]>; +def R635 : AMDILReg<635, "r635">, DwarfRegNum<[635]>; +def R636 : AMDILReg<636, "r636">, DwarfRegNum<[636]>; +def R637 : AMDILReg<637, "r637">, DwarfRegNum<[637]>; +def R638 : AMDILReg<638, "r638">, DwarfRegNum<[638]>; +def R639 : AMDILReg<639, "r639">, DwarfRegNum<[639]>; +def R640 : AMDILReg<640, "r640">, DwarfRegNum<[640]>; +def R641 : AMDILReg<641, "r641">, DwarfRegNum<[641]>; +def R642 : AMDILReg<642, "r642">, DwarfRegNum<[642]>; +def R643 : AMDILReg<643, "r643">, DwarfRegNum<[643]>; +def R644 : AMDILReg<644, "r644">, DwarfRegNum<[644]>; +def R645 : AMDILReg<645, "r645">, DwarfRegNum<[645]>; +def R646 : AMDILReg<646, "r646">, DwarfRegNum<[646]>; +def R647 : AMDILReg<647, "r647">, DwarfRegNum<[647]>; +def R648 : AMDILReg<648, "r648">, DwarfRegNum<[648]>; +def R649 : AMDILReg<649, "r649">, DwarfRegNum<[649]>; +def R650 : AMDILReg<650, "r650">, DwarfRegNum<[650]>; +def R651 : AMDILReg<651, "r651">, DwarfRegNum<[651]>; +def R652 : AMDILReg<652, "r652">, DwarfRegNum<[652]>; +def R653 : AMDILReg<653, "r653">, DwarfRegNum<[653]>; +def R654 : AMDILReg<654, "r654">, DwarfRegNum<[654]>; +def R655 : AMDILReg<655, "r655">, DwarfRegNum<[655]>; +def R656 : AMDILReg<656, "r656">, DwarfRegNum<[656]>; +def R657 : AMDILReg<657, "r657">, DwarfRegNum<[657]>; +def R658 : AMDILReg<658, "r658">, DwarfRegNum<[658]>; +def R659 : AMDILReg<659, "r659">, DwarfRegNum<[659]>; +def R660 : AMDILReg<660, "r660">, DwarfRegNum<[660]>; +def R661 : AMDILReg<661, "r661">, DwarfRegNum<[661]>; +def R662 : AMDILReg<662, "r662">, DwarfRegNum<[662]>; +def R663 : AMDILReg<663, "r663">, DwarfRegNum<[663]>; +def R664 : AMDILReg<664, "r664">, DwarfRegNum<[664]>; +def R665 : AMDILReg<665, "r665">, DwarfRegNum<[665]>; +def R666 : AMDILReg<666, "r666">, DwarfRegNum<[666]>; +def R667 : AMDILReg<667, "r667">, DwarfRegNum<[667]>; +def R668 : AMDILReg<668, "r668">, DwarfRegNum<[668]>; +def R669 : AMDILReg<669, "r669">, DwarfRegNum<[669]>; +def R670 : AMDILReg<670, "r670">, DwarfRegNum<[670]>; +def R671 : AMDILReg<671, "r671">, DwarfRegNum<[671]>; +def R672 : AMDILReg<672, "r672">, DwarfRegNum<[672]>; +def R673 : AMDILReg<673, "r673">, DwarfRegNum<[673]>; +def R674 : AMDILReg<674, "r674">, DwarfRegNum<[674]>; +def R675 : AMDILReg<675, "r675">, DwarfRegNum<[675]>; +def R676 : AMDILReg<676, "r676">, DwarfRegNum<[676]>; +def R677 : AMDILReg<677, "r677">, DwarfRegNum<[677]>; +def R678 : AMDILReg<678, "r678">, DwarfRegNum<[678]>; +def R679 : AMDILReg<679, "r679">, DwarfRegNum<[679]>; +def R680 : AMDILReg<680, "r680">, DwarfRegNum<[680]>; +def R681 : AMDILReg<681, "r681">, DwarfRegNum<[681]>; +def R682 : AMDILReg<682, "r682">, DwarfRegNum<[682]>; +def R683 : AMDILReg<683, "r683">, DwarfRegNum<[683]>; +def R684 : AMDILReg<684, "r684">, DwarfRegNum<[684]>; +def R685 : AMDILReg<685, "r685">, DwarfRegNum<[685]>; +def R686 : AMDILReg<686, "r686">, DwarfRegNum<[686]>; +def R687 : AMDILReg<687, "r687">, DwarfRegNum<[687]>; +def R688 : AMDILReg<688, "r688">, DwarfRegNum<[688]>; +def R689 : AMDILReg<689, "r689">, DwarfRegNum<[689]>; +def R690 : AMDILReg<690, "r690">, DwarfRegNum<[690]>; +def R691 : AMDILReg<691, "r691">, DwarfRegNum<[691]>; +def R692 : AMDILReg<692, "r692">, DwarfRegNum<[692]>; +def R693 : AMDILReg<693, "r693">, DwarfRegNum<[693]>; +def R694 : AMDILReg<694, "r694">, DwarfRegNum<[694]>; +def R695 : AMDILReg<695, "r695">, DwarfRegNum<[695]>; +def R696 : AMDILReg<696, "r696">, DwarfRegNum<[696]>; +def R697 : AMDILReg<697, "r697">, DwarfRegNum<[697]>; +def R698 : AMDILReg<698, "r698">, DwarfRegNum<[698]>; +def R699 : AMDILReg<699, "r699">, DwarfRegNum<[699]>; +def R700 : AMDILReg<700, "r700">, DwarfRegNum<[700]>; +def R701 : AMDILReg<701, "r701">, DwarfRegNum<[701]>; +def R702 : AMDILReg<702, "r702">, DwarfRegNum<[702]>; +def R703 : AMDILReg<703, "r703">, DwarfRegNum<[703]>; +def R704 : AMDILReg<704, "r704">, DwarfRegNum<[704]>; +def R705 : AMDILReg<705, "r705">, DwarfRegNum<[705]>; +def R706 : AMDILReg<706, "r706">, DwarfRegNum<[706]>; +def R707 : AMDILReg<707, "r707">, DwarfRegNum<[707]>; +def R708 : AMDILReg<708, "r708">, DwarfRegNum<[708]>; +def R709 : AMDILReg<709, "r709">, DwarfRegNum<[709]>; +def R710 : AMDILReg<710, "r710">, DwarfRegNum<[710]>; +def R711 : AMDILReg<711, "r711">, DwarfRegNum<[711]>; +def R712 : AMDILReg<712, "r712">, DwarfRegNum<[712]>; +def R713 : AMDILReg<713, "r713">, DwarfRegNum<[713]>; +def R714 : AMDILReg<714, "r714">, DwarfRegNum<[714]>; +def R715 : AMDILReg<715, "r715">, DwarfRegNum<[715]>; +def R716 : AMDILReg<716, "r716">, DwarfRegNum<[716]>; +def R717 : AMDILReg<717, "r717">, DwarfRegNum<[717]>; +def R718 : AMDILReg<718, "r718">, DwarfRegNum<[718]>; +def R719 : AMDILReg<719, "r719">, DwarfRegNum<[719]>; +def R720 : AMDILReg<720, "r720">, DwarfRegNum<[720]>; +def R721 : AMDILReg<721, "r721">, DwarfRegNum<[721]>; +def R722 : AMDILReg<722, "r722">, DwarfRegNum<[722]>; +def R723 : AMDILReg<723, "r723">, DwarfRegNum<[723]>; +def R724 : AMDILReg<724, "r724">, DwarfRegNum<[724]>; +def R725 : AMDILReg<725, "r725">, DwarfRegNum<[725]>; +def R726 : AMDILReg<726, "r726">, DwarfRegNum<[726]>; +def R727 : AMDILReg<727, "r727">, DwarfRegNum<[727]>; +def R728 : AMDILReg<728, "r728">, DwarfRegNum<[728]>; +def R729 : AMDILReg<729, "r729">, DwarfRegNum<[729]>; +def R730 : AMDILReg<730, "r730">, DwarfRegNum<[730]>; +def R731 : AMDILReg<731, "r731">, DwarfRegNum<[731]>; +def R732 : AMDILReg<732, "r732">, DwarfRegNum<[732]>; +def R733 : AMDILReg<733, "r733">, DwarfRegNum<[733]>; +def R734 : AMDILReg<734, "r734">, DwarfRegNum<[734]>; +def R735 : AMDILReg<735, "r735">, DwarfRegNum<[735]>; +def R736 : AMDILReg<736, "r736">, DwarfRegNum<[736]>; +def R737 : AMDILReg<737, "r737">, DwarfRegNum<[737]>; +def R738 : AMDILReg<738, "r738">, DwarfRegNum<[738]>; +def R739 : AMDILReg<739, "r739">, DwarfRegNum<[739]>; +def R740 : AMDILReg<740, "r740">, DwarfRegNum<[740]>; +def R741 : AMDILReg<741, "r741">, DwarfRegNum<[741]>; +def R742 : AMDILReg<742, "r742">, DwarfRegNum<[742]>; +def R743 : AMDILReg<743, "r743">, DwarfRegNum<[743]>; +def R744 : AMDILReg<744, "r744">, DwarfRegNum<[744]>; +def R745 : AMDILReg<745, "r745">, DwarfRegNum<[745]>; +def R746 : AMDILReg<746, "r746">, DwarfRegNum<[746]>; +def R747 : AMDILReg<747, "r747">, DwarfRegNum<[747]>; +def R748 : AMDILReg<748, "r748">, DwarfRegNum<[748]>; +def R749 : AMDILReg<749, "r749">, DwarfRegNum<[749]>; +def R750 : AMDILReg<750, "r750">, DwarfRegNum<[750]>; +def R751 : AMDILReg<751, "r751">, DwarfRegNum<[751]>; +def R752 : AMDILReg<752, "r752">, DwarfRegNum<[752]>; +def R753 : AMDILReg<753, "r753">, DwarfRegNum<[753]>; +def R754 : AMDILReg<754, "r754">, DwarfRegNum<[754]>; +def R755 : AMDILReg<755, "r755">, DwarfRegNum<[755]>; +def R756 : AMDILReg<756, "r756">, DwarfRegNum<[756]>; +def R757 : AMDILReg<757, "r757">, DwarfRegNum<[757]>; +def R758 : AMDILReg<758, "r758">, DwarfRegNum<[758]>; +def R759 : AMDILReg<759, "r759">, DwarfRegNum<[759]>; +def R760 : AMDILReg<760, "r760">, DwarfRegNum<[760]>; +def R761 : AMDILReg<761, "r761">, DwarfRegNum<[761]>; +def R762 : AMDILReg<762, "r762">, DwarfRegNum<[762]>; +def R763 : AMDILReg<763, "r763">, DwarfRegNum<[763]>; +def R764 : AMDILReg<764, "r764">, DwarfRegNum<[764]>; +def R765 : AMDILReg<765, "r765">, DwarfRegNum<[765]>; +def R766 : AMDILReg<766, "r766">, DwarfRegNum<[766]>; +def R767 : AMDILReg<767, "r767">, DwarfRegNum<[767]>; + +// All registers between 1000 and 1024 are reserved and cannot be used +// unless commented in this section +// r1021-r1025 are used to dynamically calculate the local/group/thread/region/region_local ID's +// r1020 is used to hold the frame index for local arrays +// r1019 is used to hold the dynamic stack allocation pointer +// r1018 is used as a temporary register for handwritten code +// r1017 is used as a temporary register for handwritten code +// r1016 is used as a temporary register for load/store code +// r1015 is used as a temporary register for data segment offset +// r1014 is used as a temporary register for store code +// r1013 is used as the section data pointer register +// r1012-r1010 and r1001-r1008 are used for temporary I/O registers +// r1009 is used as the frame pointer register +// r999 is used as the mem register. +// r998 is used as the return address register. +//def R1025 : AMDILReg<1025, "r1025">, DwarfRegNum<[1025]>; +//def R1024 : AMDILReg<1024, "r1024">, DwarfRegNum<[1024]>; +//def R1023 : AMDILReg<1023, "r1023">, DwarfRegNum<[1023]>; +//def R1022 : AMDILReg<1022, "r1022">, DwarfRegNum<[1022]>; +//def R1021 : AMDILReg<1021, "r1021">, DwarfRegNum<[1021]>; +//def R1020 : AMDILReg<1020, "r1020">, DwarfRegNum<[1020]>; +def SP : AMDILReg<1019, "r1019">, DwarfRegNum<[1019]>; +def T1 : AMDILReg<1018, "r1018">, DwarfRegNum<[1018]>; +def T2 : AMDILReg<1017, "r1017">, DwarfRegNum<[1017]>; +def T3 : AMDILReg<1016, "r1016">, DwarfRegNum<[1016]>; +def T4 : AMDILReg<1015, "r1015">, DwarfRegNum<[1015]>; +def T5 : AMDILReg<1014, "r1014">, DwarfRegNum<[1014]>; +def SDP : AMDILReg<1013, "r1013">, DwarfRegNum<[1013]>; +def R1012: AMDILReg<1012, "r1012">, DwarfRegNum<[1012]>; +def R1011: AMDILReg<1011, "r1011">, DwarfRegNum<[1011]>; +def R1010: AMDILReg<1010, "r1010">, DwarfRegNum<[1010]>; +def DFP : AMDILReg<1009, "r1009">, DwarfRegNum<[1009]>; +def R1008: AMDILReg<1008, "r1008">, DwarfRegNum<[1008]>; +def R1007: AMDILReg<1007, "r1007">, DwarfRegNum<[1007]>; +def R1006: AMDILReg<1006, "r1006">, DwarfRegNum<[1006]>; +def R1005: AMDILReg<1005, "r1005">, DwarfRegNum<[1005]>; +def R1004: AMDILReg<1004, "r1004">, DwarfRegNum<[1004]>; +def R1003: AMDILReg<1003, "r1003">, DwarfRegNum<[1003]>; +def R1002: AMDILReg<1002, "r1002">, DwarfRegNum<[1002]>; +def R1001: AMDILReg<1001, "r1001">, DwarfRegNum<[1001]>; +def MEM : AMDILReg<999, "mem">, DwarfRegNum<[999]>; +def RA : AMDILReg<998, "r998">, DwarfRegNum<[998]>; +def FP : AMDILReg<997, "r997">, DwarfRegNum<[997]>; +def GPRI8 : RegisterClass<"AMDIL", [i8], 8, + (add (sequence "R%u", 1, 767), RA, SP, T1, T2, T3, T4, T5, SDP, R1010, R1011, R1001, R1002, R1003, R1004, R1005, R1006, R1007, R1008, MEM, R1012)> +{ + let AltOrders = [(add (sequence "R%u", 1, 767))]; + let AltOrderSelect = [{ + return 1; + }]; + } +def GPRV2I8 : RegisterClass<"AMDIL", [v2i8], 16, + (add (sequence "R%u", 1, 767), RA, SP, T1, T2, T3, T4, T5, SDP, R1010, R1011, R1001, R1002, R1003, R1004, R1005, R1006, R1007, R1008, MEM, R1012)> +{ + let AltOrders = [(add (sequence "R%u", 1, 767))]; + let AltOrderSelect = [{ + return 1; + }]; + } +def GPRV4I8 : RegisterClass<"AMDIL", [v4i8], 32, + (add (sequence "R%u", 1, 767), RA, SP, T1, T2, T3, T4, T5, SDP, R1010, R1011, R1001, R1002, R1003, R1004, R1005, R1006, R1007, R1008, MEM, R1012)> +{ + let AltOrders = [(add (sequence "R%u", 1, 767))]; + let AltOrderSelect = [{ + return 1; + }]; + } +def GPRI16 : RegisterClass<"AMDIL", [i16], 16, + (add (sequence "R%u", 1, 767), RA, SP, T1, T2, T3, T4, T5, SDP, R1010, R1011, R1001, R1002, R1003, R1004, R1005, R1006, R1007, R1008, MEM, R1012)> +{ + let AltOrders = [(add (sequence "R%u", 1, 767))]; + let AltOrderSelect = [{ + return 1; + }]; + } +def GPRV2I16 : RegisterClass<"AMDIL", [v2i16], 32, + (add (sequence "R%u", 1, 767), RA, SP, T1, T2, T3, T4, T5, SDP, R1010, R1011, R1001, R1002, R1003, R1004, R1005, R1006, R1007, R1008, MEM, R1012)> +{ + let AltOrders = [(add (sequence "R%u", 1, 767))]; + let AltOrderSelect = [{ + return 1; + }]; + } +def GPRV4I16 : RegisterClass<"AMDIL", [v4i16], 64, + (add (sequence "R%u", 1, 767), RA, SP, T1, T2, T3, T4, T5, SDP, R1010, R1011, R1001, R1002, R1003, R1004, R1005, R1006, R1007, R1008, MEM, R1012)> +{ + let AltOrders = [(add (sequence "R%u", 1, 767))]; + let AltOrderSelect = [{ + return 1; + }]; + } +def GPRI32 : RegisterClass<"AMDIL", [i32], 32, + (add (sequence "R%u", 1, 767), RA, SP, T1, T2, T3, T4, T5, SDP, R1010, R1011, R1001, R1002, R1003, R1004, R1005, R1006, R1007, R1008, MEM, R1012)> +{ + let AltOrders = [(add (sequence "R%u", 1, 767))]; + let AltOrderSelect = [{ + return 1; + }]; + } +def GPRF32 : RegisterClass<"AMDIL", [f32], 32, + (add (sequence "R%u", 1, 767), RA, SP, T1, T2, T3, T4, T5, SDP, R1010, R1011, R1001, R1002, R1003, R1004, R1005, R1006, R1007, R1008, MEM, R1012)> +{ + let AltOrders = [(add (sequence "R%u", 1, 767))]; + let AltOrderSelect = [{ + return 1; + }]; + } +// For 64 bit integer emulation, the lower 32 bits are in x +// and the upper 32 bits are in y +def GPRI64 : RegisterClass<"AMDIL", [i64], 64, + (add (sequence "R%u", 1, 767), RA, SP, T1, T2, T3, T4, T5, SDP, R1010, R1011, R1001, R1002, R1003, R1004, R1005, R1006, R1007, R1008, MEM, R1012)> +{ + let AltOrders = [(add (sequence "R%u", 1, 767))]; + let AltOrderSelect = [{ + return 1; + }]; + } +def GPRF64 : RegisterClass<"AMDIL", [f64], 64, + (add (sequence "R%u", 1, 767), RA, SP, T1, T2, T3, T4, T5, SDP, R1010, R1011, R1001, R1002, R1003, R1004, R1005, R1006, R1007, R1008, MEM, R1012)> +{ + let AltOrders = [(add (sequence "R%u", 1, 767))]; + let AltOrderSelect = [{ + return 1; + }]; + } +def GPRV4F32 : RegisterClass<"AMDIL", [v4f32], 128, + (add (sequence "R%u", 1, 767), RA, SP, T1, T2, T3, T4, T5, SDP, R1010, R1011, R1001, R1002, R1003, R1004, R1005, R1006, R1007, R1008, MEM, R1012)> +{ + let AltOrders = [(add (sequence "R%u", 1, 767))]; + let AltOrderSelect = [{ + return 1; + }]; + } +def GPRV4I32 : RegisterClass<"AMDIL", [v4i32], 128, + (add (sequence "R%u", 1, 767), RA, SP, T1, T2, T3, T4, T5, SDP, R1010, R1011, R1001, R1002, R1003, R1004, R1005, R1006, R1007, R1008, MEM, R1012)> +{ + let AltOrders = [(add (sequence "R%u", 1, 767))]; + let AltOrderSelect = [{ + return 1; + }]; + } +def GPRV2I32 : RegisterClass<"AMDIL", [v2i32], 64, + (add (sequence "R%u", 1, 767), RA, SP, T1, T2, T3, T4, T5, SDP, R1010, R1011, R1001, R1002, R1003, R1004, R1005, R1006, R1007, R1008, MEM, R1012)> +{ + let AltOrders = [(add (sequence "R%u", 1, 767))]; + let AltOrderSelect = [{ + return 1; + }]; + } +def GPRV2F32 : RegisterClass<"AMDIL", [v2f32], 64, + (add (sequence "R%u", 1, 767), RA, SP, T1, T2, T3, T4, T5, SDP, R1010, R1011, R1001, R1002, R1003, R1004, R1005, R1006, R1007, R1008, MEM, R1012)> +{ + let AltOrders = [(add (sequence "R%u", 1, 767))]; + let AltOrderSelect = [{ + return 1; + }]; + } +def GPRV2I64 : RegisterClass<"AMDIL", [v2i64], 128, + (add (sequence "R%u", 1, 767), RA, SP, T1, T2, T3, T4, T5, SDP, R1010, R1011, R1001, R1002, R1003, R1004, R1005, R1006, R1007, R1008, MEM, R1012)> +{ + let AltOrders = [(add (sequence "R%u", 1, 767))]; + let AltOrderSelect = [{ + return 1; + }]; + } +def GPRV2F64 : RegisterClass<"AMDIL", [v2f64], 128, + (add (sequence "R%u", 1, 767), RA, SP, T1, T2, T3, T4, T5, SDP, R1010, R1011, R1001, R1002, R1003, R1004, R1005, R1006, R1007, R1008, MEM, R1012)> +{ + let AltOrders = [(add (sequence "R%u", 1, 767))]; + let AltOrderSelect = [{ + return 1; + }]; + } + diff --git a/lib/Target/AMDIL/AMDILTokenDesc.td b/lib/Target/AMDIL/AMDILTokenDesc.td new file mode 100644 index 00000000000..2dafb2cd559 --- /dev/null +++ b/lib/Target/AMDIL/AMDILTokenDesc.td @@ -0,0 +1,120 @@ +//===-- AMDILTokenDesc.td - AMDIL Token Definitions --*- tablegen -*-----===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===--------------------------------------------------------------------===// + +include "AMDILEnumeratedTypes.td" + +// Each token is 32 bits as specified in section 2.1 of the IL spec +class ILToken n> { + field bits<32> _bits = n; +} + +// Section 2.2.1 - IL Language Token +class ILLang client_type> : ILToken<0> { + let _bits{0-7} = client_type; +} + +// Section 2.2.2 - IL Version Token +class ILVersion minor_version, bits<8> major_version, ILShader shader_type> : ILToken<0> { + let _bits{0-7} = minor_version; + let _bits{8-15} = major_version; + let _bits{16-23} = shader_type.Value; +} + +// Section 2.2.3 - IL Opcode Token +class ILOpcode control, bit sec_mod_pre, bit pri_mod_pre> : ILToken<0> { + let _bits{0-15} = opcode.Value; + let _bits{16-29} = control; + let _bits{30} = sec_mod_pre; + let _bits{31} = pri_mod_pre; +} + +// Section 2.2.4 - IL Destination Token +class ILDst relative_address, bit dimension, bit immediate_pre, bit extended> : ILToken<0> { + let _bits{0-15} = register_num.Value; + let _bits{16-21} = register_type.Value; + let _bits{22} = mod_pre; + let _bits{23-24} = relative_address; + let _bits{25} = dimension; + let _bits{26} = immediate_pre; + let _bits{31} = extended; +} + +// Section 2.2.5 - IL Destination Modifier Token +class ILDstMod : ILToken<0> { + let _bits{0-1} = x.Value; + let _bits{2-3} = y.Value; + let _bits{4-5} = z.Value; + let _bits{6-7} = w.Value; + let _bits{8} = clamp; + //let _bits{9-12} = shift_scale; +} + +// Section 2.2.6 - IL Source Token +class ILSrc relative_address, bit dimension, bit immediate_pre, bit extended> : ILToken<0> { + let _bits{0-15} = register_num.Value; + let _bits{16-21} = register_type.Value; + let _bits{22} = mod_pre; + let _bits{23-24} = relative_address; + let _bits{25} = dimension; + let _bits{26} = immediate_pre; + let _bits{31} = extended; +} + +// Section 2.2.7 - IL Source Modifier Token +class ILSrcMod clamp> : ILToken<0> { + let _bits{0-2} = swizzle_x.Value; + let _bits{3} = negate_x; + let _bits{4-6} = swizzle_y.Value; + let _bits{7} = negate_y; + let _bits{8-10} = swizzle_z.Value; + let _bits{11} = negate_z; + let _bits{12-14} = swizzle_w.Value; + let _bits{15} = negate_w; + let _bits{16} = invert; + let _bits{17} = bias; + let _bits{18} = x2; + let _bits{19} = sign; + let _bits{20} = abs; + let _bits{21-23} = divComp.Value; + let _bits{24-31} = clamp; +} + +// Section 2.2.8 - IL Relative Address Token +class ILRelAddr : ILToken<0> { + let _bits{0-15} = address_register.Value; + let _bits{16} = loop_relative; + let _bits{17-19} = component.Value; +} + +// IL Literal Token +class ILLiteral val> : ILToken<0> { + let _bits = val; +} + +// All tokens required for a destination register +class ILDstReg { + ILDst reg = Reg; + ILDstMod mod = Mod; + ILRelAddr rel = Rel; + ILSrc reg_rel = Reg_Rel; + ILSrcMod reg_rel_mod = Reg_Rel_Mod; +} + +// All tokens required for a source register +class ILSrcReg { + ILSrc reg = Reg; + ILSrcMod mod = Mod; + ILRelAddr rel = Rel; + ILSrc reg_rel = Reg_Rel; + ILSrcMod reg_rel_mod = Reg_Rel_Mod; +} + diff --git a/lib/Target/AMDIL/AMDILVersion.td b/lib/Target/AMDIL/AMDILVersion.td new file mode 100644 index 00000000000..d863b068131 --- /dev/null +++ b/lib/Target/AMDIL/AMDILVersion.td @@ -0,0 +1,75 @@ +//===-- AMDILVersion.td - Barrier Instruction/Intrinsic definitions------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===--------------------------------------------------------------------===// +// Intrinsic operation support +//===--------------------------------------------------------------------===// +let TargetPrefix = "AMDIL", isTarget = 1 in { +def int_AMDIL_barrier : GCCBuiltin<"barrier">, + BinaryIntNoRetInt; +def int_AMDIL_barrier_global : GCCBuiltin<"barrierGlobal">, + BinaryIntNoRetInt; +def int_AMDIL_barrier_local : GCCBuiltin<"barrierLocal">, + BinaryIntNoRetInt; +def int_AMDIL_barrier_region : GCCBuiltin<"barrierRegion">, + BinaryIntNoRetInt; +def int_AMDIL_get_region_id : GCCBuiltin<"__amdil_get_region_id_int">, + Intrinsic<[llvm_v4i32_ty], [], []>; +def int_AMDIL_get_region_local_id : GCCBuiltin<"__amdil_get_region_local_id_int">, + Intrinsic<[llvm_v4i32_ty], [], []>; +def int_AMDIL_get_num_regions : GCCBuiltin<"__amdil_get_num_regions_int">, + Intrinsic<[llvm_v4i32_ty], [], []>; +def int_AMDIL_get_region_size : GCCBuiltin<"__amdil_get_region_size_int">, + Intrinsic<[llvm_v4i32_ty], [], []>; +} + +let isCall=1, isNotDuplicable=1 in { + let Predicates=[hasRegionAS] in { +def BARRIER_EGNI : BinaryOpNoRet; +} +let Predicates=[noRegionAS] in { +def BARRIER_7XX : BinaryOpNoRet; +} + +def BARRIER_LOCAL : BinaryOpNoRet; + +def BARRIER_GLOBAL : BinaryOpNoRet; + +def BARRIER_REGION : BinaryOpNoRet; + +def GET_REGION_ID : ILFormat; + +def GET_REGION_LOCAL_ID : ILFormat; + +def GET_REGION_SIZE : ILFormat; + +def GET_NUM_REGIONS : ILFormat; + +} diff --git a/lib/Target/AMDIL/Processors.td b/lib/Target/AMDIL/Processors.td new file mode 100644 index 00000000000..6d1b411e207 --- /dev/null +++ b/lib/Target/AMDIL/Processors.td @@ -0,0 +1,28 @@ +//===-- Processors.td - TODO: Add brief description -------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// AMDIL processors supported. +// +//===----------------------------------------------------------------------===// + +class Proc Features> +: Processor; +def : Proc<"rv710", R600_EG_Itin, []>; +def : Proc<"rv730", R600_EG_Itin, []>; +def : Proc<"rv770", R600_EG_Itin, [FeatureFP64]>; +def : Proc<"cedar", R600_EG_Itin, [FeatureByteAddress, FeatureImages]>; +def : Proc<"redwood", R600_EG_Itin, [FeatureByteAddress, FeatureImages]>; +def : Proc<"juniper", R600_EG_Itin, [FeatureByteAddress, FeatureImages]>; +def : Proc<"cypress", R600_EG_Itin, [FeatureByteAddress, FeatureImages, FeatureFP64]>; +def : Proc<"barts", R600_EG_Itin, [FeatureByteAddress, FeatureImages]>; +def : Proc<"turks", R600_EG_Itin, [FeatureByteAddress, FeatureImages]>; +def : Proc<"caicos", R600_EG_Itin, [FeatureByteAddress, FeatureImages]>; +def : Proc<"cayman", R600_EG_Itin, [FeatureByteAddress, FeatureImages, FeatureFP64]>; +def : Proc<"SI", SI_Itin, []>; + diff --git a/lib/Target/AMDIL/R600GenRegisterInfo.pl b/lib/Target/AMDIL/R600GenRegisterInfo.pl new file mode 100644 index 00000000000..f01fa26104f --- /dev/null +++ b/lib/Target/AMDIL/R600GenRegisterInfo.pl @@ -0,0 +1,202 @@ +#===-- R600GenRegisterInfo.pl - Script for generating register info files --===# +# +# The LLVM Compiler Infrastructure +# +# This file is distributed under the University of Illinois Open Source +# License. See LICENSE.TXT for details. +# +#===------------------------------------------------------------------------===# +# +# This perl script prints to stdout .td code to be used as R600RegisterInfo.td +# it also generates a file called R600HwRegInfo.include, which contains helper +# functions for determining the hw encoding of registers. +# +#===------------------------------------------------------------------------===# + +use strict; +use warnings; + +use constant CONST_REG_COUNT => 256; +use constant TEMP_REG_COUNT => 128; + +my $CREG_MAX = CONST_REG_COUNT - 1; +my $TREG_MAX = TEMP_REG_COUNT - 1; + +print < : Register { + let Namespace = "AMDIL"; +} + +class R600Reg_128 subregs> : RegisterWithSubRegs { + let Namespace = "AMDIL"; + let SubRegIndices = [sel_x, sel_y, sel_z, sel_w]; +} + +STRING + +my $i; + +### REG DEFS ### + +my @creg_list = print_reg_defs(CONST_REG_COUNT * 4, "C"); +my @treg_list = print_reg_defs(TEMP_REG_COUNT * 4, "T"); + +my @t128reg; +my @treg_x; +for (my $i = 0; $i < TEMP_REG_COUNT; $i++) { + my $name = "T$i\_XYZW"; + print qq{def $name : R600Reg_128 <"T$i.XYZW", [T$i\_X, T$i\_Y, T$i\_Z, T$i\_W] >;\n}; + $t128reg[$i] = $name; + $treg_x[$i] = "T$i\_X"; + if ($i % 10 == 0) { + $t128reg[$i] .= "\n"; + $treg_x[$i] .= "\n"; + } +} + +my $treg_string = join(",", @treg_list); +my $creg_list = join(",", @creg_list); +my $t128_string = join(",", @t128reg); +my $treg_x_string = join(",", @treg_x); +print < { + dag set = s; +} + +def ZERO : R600Reg<"0.0">; +def HALF : R600Reg<"0.5">; +def ONE : R600Reg<"1.0">; +def ONE_INT : R600Reg<"1">; +def NEG_HALF : R600Reg<"-0.5">; +def NEG_ONE : R600Reg<"-1.0">; +def PV_X : R600Reg<"pv.x">; +def ALU_LITERAL_X : R600Reg<"literal.x">; + +def R600_CReg32 : RegisterClass <"AMDIL", [f32, i32], 32, (add + $creg_list)>; + +def R600_TReg32 : RegisterClass <"AMDIL", [f32, i32], 32, (add + $treg_string)>; + +def R600_TReg32_X : RegisterClass <"AMDIL", [f32, i32], 32, (add + $treg_x_string)>; + +def R600_Reg32 : RegisterClass <"AMDIL", [f32, i32], 32, (add + R600_TReg32, + R600_CReg32, + ZERO, HALF, ONE, ONE_INT, PV_X, ALU_LITERAL_X, NEG_ONE, NEG_HALF)>; + +def R600_Reg128 : RegisterClass<"AMDIL", [v4f32, v4i32], 128, (add + $t128_string)> +{ + let CopyCost = -1; +} + +STRING + +my %index_map; +my %chan_map; + +for ($i = 0; $i <= $#creg_list; $i++) { + push(@{$index_map{get_hw_index($i)}}, $creg_list[$i]); + push(@{$chan_map{get_chan_str($i)}}, $creg_list[$i]); +} + +for ($i = 0; $i <= $#treg_list; $i++) { + push(@{$index_map{get_hw_index($i)}}, $treg_list[$i]); + push(@{$chan_map{get_chan_str($i)}}, $treg_list[$i]); +} + +for ($i = 0; $i <= $#t128reg; $i++) { + push(@{$index_map{$i}}, $t128reg[$i]); + push(@{$chan_map{'X'}}, $t128reg[$i]); +} + +open(OUTFILE, ">", "R600HwRegInfo.inc"); + +print OUTFILE <;\n}; + $reg_list[$i] = $name; + if ($i % 10 == 0) { + $reg_list[$i] .= "\n"; + } + } + return @reg_list; +} + +#Helper functions +sub get_hw_index { + my ($index) = @_; + return int($index / 4); +} + +sub get_chan_str { + my ($index) = @_; + my $chan = $index % 4; + if ($chan == 0 ) { + return 'X'; + } elsif ($chan == 1) { + return 'Y'; + } elsif ($chan == 2) { + return 'Z'; + } elsif ($chan == 3) { + return 'W'; + } else { + die("Unknown chan value: $chan"); + } +} diff --git a/lib/Target/AMDIL/R600HwRegInfo.include b/lib/Target/AMDIL/R600HwRegInfo.include new file mode 100644 index 00000000000..93301e14361 --- /dev/null +++ b/lib/Target/AMDIL/R600HwRegInfo.include @@ -0,0 +1,3864 @@ + +unsigned R600RegisterInfo::getHWRegIndexGen(unsigned reg) const +{ + switch(reg) { + default: assert(!"Unknown register"); return 0; + case AMDIL::C127_X: + case AMDIL::C127_Y: + case AMDIL::C127_Z: + case AMDIL::C127_W: + case AMDIL::T127_X: + case AMDIL::T127_Y: + case AMDIL::T127_Z: + case AMDIL::T127_W: + case AMDIL::T127_XYZW: + return 127; + + case AMDIL::C32_X: + case AMDIL::C32_Y: + case AMDIL::C32_Z: + case AMDIL::C32_W: + case AMDIL::T32_X: + case AMDIL::T32_Y: + case AMDIL::T32_Z: + case AMDIL::T32_W: + case AMDIL::T32_XYZW: + return 32; + + case AMDIL::C90_X: + case AMDIL::C90_Y: + case AMDIL::C90_Z: + case AMDIL::C90_W: + case AMDIL::T90_X: + case AMDIL::T90_Y: + case AMDIL::T90_Z: + case AMDIL::T90_W: + case AMDIL::T90_XYZW: + return 90; + + case AMDIL::C206_X: + case AMDIL::C206_Y: + case AMDIL::C206_Z: + case AMDIL::C206_W: + return 206; + + case AMDIL::C118_X: + case AMDIL::C118_Y: + case AMDIL::C118_Z: + case AMDIL::C118_W: + case AMDIL::T118_X: + case AMDIL::T118_Y: + case AMDIL::T118_Z: + case AMDIL::T118_W: + case AMDIL::T118_XYZW: + return 118; + + case AMDIL::C71_X: + case AMDIL::C71_Y: + case AMDIL::C71_Z: + case AMDIL::C71_W: + case AMDIL::T71_X: + case AMDIL::T71_Y: + case AMDIL::T71_Z: + case AMDIL::T71_W: + case AMDIL::T71_XYZW: + return 71; + + case AMDIL::C102_X: + case AMDIL::C102_Y: + case AMDIL::C102_Z: + case AMDIL::C102_W: + case AMDIL::T102_X: + case AMDIL::T102_Y: + case AMDIL::T102_Z: + case AMDIL::T102_W: + case AMDIL::T102_XYZW: + return 102; + + case AMDIL::C200_X: + case AMDIL::C200_Y: + case AMDIL::C200_Z: + case AMDIL::C200_W: + return 200; + + case AMDIL::C18_X: + case AMDIL::C18_Y: + case AMDIL::C18_Z: + case AMDIL::C18_W: + case AMDIL::T18_X: + case AMDIL::T18_Y: + case AMDIL::T18_Z: + case AMDIL::T18_W: + case AMDIL::T18_XYZW: + return 18; + + case AMDIL::C125_X: + case AMDIL::C125_Y: + case AMDIL::C125_Z: + case AMDIL::C125_W: + case AMDIL::T125_X: + case AMDIL::T125_Y: + case AMDIL::T125_Z: + case AMDIL::T125_W: + case AMDIL::T125_XYZW: + return 125; + + case AMDIL::C16_X: + case AMDIL::C16_Y: + case AMDIL::C16_Z: + case AMDIL::C16_W: + case AMDIL::T16_X: + case AMDIL::T16_Y: + case AMDIL::T16_Z: + case AMDIL::T16_W: + case AMDIL::T16_XYZW: + return 16; + + case AMDIL::C44_X: + case AMDIL::C44_Y: + case AMDIL::C44_Z: + case AMDIL::C44_W: + case AMDIL::T44_X: + case AMDIL::T44_Y: + case AMDIL::T44_Z: + case AMDIL::T44_W: + case AMDIL::T44_XYZW: + return 44; + + case AMDIL::C55_X: + case AMDIL::C55_Y: + case AMDIL::C55_Z: + case AMDIL::C55_W: + case AMDIL::T55_X: + case AMDIL::T55_Y: + case AMDIL::T55_Z: + case AMDIL::T55_W: + case AMDIL::T55_XYZW: + return 55; + + case AMDIL::C84_X: + case AMDIL::C84_Y: + case AMDIL::C84_Z: + case AMDIL::C84_W: + case AMDIL::T84_X: + case AMDIL::T84_Y: + case AMDIL::T84_Z: + case AMDIL::T84_W: + case AMDIL::T84_XYZW: + return 84; + + case AMDIL::C27_X: + case AMDIL::C27_Y: + case AMDIL::C27_Z: + case AMDIL::C27_W: + case AMDIL::T27_X: + case AMDIL::T27_Y: + case AMDIL::T27_Z: + case AMDIL::T27_W: + case AMDIL::T27_XYZW: + return 27; + + case AMDIL::C233_X: + case AMDIL::C233_Y: + case AMDIL::C233_Z: + case AMDIL::C233_W: + return 233; + + case AMDIL::C190_X: + case AMDIL::C190_Y: + case AMDIL::C190_Z: + case AMDIL::C190_W: + return 190; + + case AMDIL::C161_X: + case AMDIL::C161_Y: + case AMDIL::C161_Z: + case AMDIL::C161_W: + return 161; + + case AMDIL::C194_X: + case AMDIL::C194_Y: + case AMDIL::C194_Z: + case AMDIL::C194_W: + return 194; + + case AMDIL::C95_X: + case AMDIL::C95_Y: + case AMDIL::C95_Z: + case AMDIL::C95_W: + case AMDIL::T95_X: + case AMDIL::T95_Y: + case AMDIL::T95_Z: + case AMDIL::T95_W: + case AMDIL::T95_XYZW: + return 95; + + case AMDIL::C57_X: + case AMDIL::C57_Y: + case AMDIL::C57_Z: + case AMDIL::C57_W: + case AMDIL::T57_X: + case AMDIL::T57_Y: + case AMDIL::T57_Z: + case AMDIL::T57_W: + case AMDIL::T57_XYZW: + return 57; + + case AMDIL::C220_X: + case AMDIL::C220_Y: + case AMDIL::C220_Z: + case AMDIL::C220_W: + return 220; + + case AMDIL::C20_X: + case AMDIL::C20_Y: + case AMDIL::C20_Z: + case AMDIL::C20_W: + case AMDIL::T20_X: + case AMDIL::T20_Y: + case AMDIL::T20_Z: + case AMDIL::T20_W: + case AMDIL::T20_XYZW: + return 20; + + case AMDIL::C243_X: + case AMDIL::C243_Y: + case AMDIL::C243_Z: + case AMDIL::C243_W: + return 243; + + case AMDIL::C231_X: + case AMDIL::C231_Y: + case AMDIL::C231_Z: + case AMDIL::C231_W: + return 231; + + case AMDIL::C163_X: + case AMDIL::C163_Y: + case AMDIL::C163_Z: + case AMDIL::C163_W: + return 163; + + case AMDIL::C109_X: + case AMDIL::C109_Y: + case AMDIL::C109_Z: + case AMDIL::C109_W: + case AMDIL::T109_X: + case AMDIL::T109_Y: + case AMDIL::T109_Z: + case AMDIL::T109_W: + case AMDIL::T109_XYZW: + return 109; + + case AMDIL::C151_X: + case AMDIL::C151_Y: + case AMDIL::C151_Z: + case AMDIL::C151_W: + return 151; + + case AMDIL::C89_X: + case AMDIL::C89_Y: + case AMDIL::C89_Z: + case AMDIL::C89_W: + case AMDIL::T89_X: + case AMDIL::T89_Y: + case AMDIL::T89_Z: + case AMDIL::T89_W: + case AMDIL::T89_XYZW: + return 89; + + case AMDIL::C175_X: + case AMDIL::C175_Y: + case AMDIL::C175_Z: + case AMDIL::C175_W: + return 175; + + case AMDIL::C148_X: + case AMDIL::C148_Y: + case AMDIL::C148_Z: + case AMDIL::C148_W: + return 148; + + case AMDIL::C31_X: + case AMDIL::C31_Y: + case AMDIL::C31_Z: + case AMDIL::C31_W: + case AMDIL::T31_X: + case AMDIL::T31_Y: + case AMDIL::T31_Z: + case AMDIL::T31_W: + case AMDIL::T31_XYZW: + return 31; + + case AMDIL::C35_X: + case AMDIL::C35_Y: + case AMDIL::C35_Z: + case AMDIL::C35_W: + case AMDIL::T35_X: + case AMDIL::T35_Y: + case AMDIL::T35_Z: + case AMDIL::T35_W: + case AMDIL::T35_XYZW: + return 35; + + case AMDIL::C11_X: + case AMDIL::C11_Y: + case AMDIL::C11_Z: + case AMDIL::C11_W: + case AMDIL::T11_X: + case AMDIL::T11_Y: + case AMDIL::T11_Z: + case AMDIL::T11_W: + case AMDIL::T11_XYZW: + return 11; + + case AMDIL::C208_X: + case AMDIL::C208_Y: + case AMDIL::C208_Z: + case AMDIL::C208_W: + return 208; + + case AMDIL::C78_X: + case AMDIL::C78_Y: + case AMDIL::C78_Z: + case AMDIL::C78_W: + case AMDIL::T78_X: + case AMDIL::T78_Y: + case AMDIL::T78_Z: + case AMDIL::T78_W: + case AMDIL::T78_XYZW: + return 78; + + case AMDIL::C93_X: + case AMDIL::C93_Y: + case AMDIL::C93_Z: + case AMDIL::C93_W: + case AMDIL::T93_X: + case AMDIL::T93_Y: + case AMDIL::T93_Z: + case AMDIL::T93_W: + case AMDIL::T93_XYZW: + return 93; + + case AMDIL::C106_X: + case AMDIL::C106_Y: + case AMDIL::C106_Z: + case AMDIL::C106_W: + case AMDIL::T106_X: + case AMDIL::T106_Y: + case AMDIL::T106_Z: + case AMDIL::T106_W: + case AMDIL::T106_XYZW: + return 106; + + case AMDIL::C157_X: + case AMDIL::C157_Y: + case AMDIL::C157_Z: + case AMDIL::C157_W: + return 157; + + case AMDIL::C65_X: + case AMDIL::C65_Y: + case AMDIL::C65_Z: + case AMDIL::C65_W: + case AMDIL::T65_X: + case AMDIL::T65_Y: + case AMDIL::T65_Z: + case AMDIL::T65_W: + case AMDIL::T65_XYZW: + return 65; + + case AMDIL::C29_X: + case AMDIL::C29_Y: + case AMDIL::C29_Z: + case AMDIL::C29_W: + case AMDIL::T29_X: + case AMDIL::T29_Y: + case AMDIL::T29_Z: + case AMDIL::T29_W: + case AMDIL::T29_XYZW: + return 29; + + case AMDIL::C197_X: + case AMDIL::C197_Y: + case AMDIL::C197_Z: + case AMDIL::C197_W: + return 197; + + case AMDIL::C203_X: + case AMDIL::C203_Y: + case AMDIL::C203_Z: + case AMDIL::C203_W: + return 203; + + case AMDIL::C138_X: + case AMDIL::C138_Y: + case AMDIL::C138_Z: + case AMDIL::C138_W: + return 138; + + case AMDIL::C199_X: + case AMDIL::C199_Y: + case AMDIL::C199_Z: + case AMDIL::C199_W: + return 199; + + case AMDIL::C114_X: + case AMDIL::C114_Y: + case AMDIL::C114_Z: + case AMDIL::C114_W: + case AMDIL::T114_X: + case AMDIL::T114_Y: + case AMDIL::T114_Z: + case AMDIL::T114_W: + case AMDIL::T114_XYZW: + return 114; + + case AMDIL::C226_X: + case AMDIL::C226_Y: + case AMDIL::C226_Z: + case AMDIL::C226_W: + return 226; + + case AMDIL::C58_X: + case AMDIL::C58_Y: + case AMDIL::C58_Z: + case AMDIL::C58_W: + case AMDIL::T58_X: + case AMDIL::T58_Y: + case AMDIL::T58_Z: + case AMDIL::T58_W: + case AMDIL::T58_XYZW: + return 58; + + case AMDIL::C211_X: + case AMDIL::C211_Y: + case AMDIL::C211_Z: + case AMDIL::C211_W: + return 211; + + case AMDIL::C153_X: + case AMDIL::C153_Y: + case AMDIL::C153_Z: + case AMDIL::C153_W: + return 153; + + case AMDIL::C15_X: + case AMDIL::C15_Y: + case AMDIL::C15_Z: + case AMDIL::C15_W: + case AMDIL::T15_X: + case AMDIL::T15_Y: + case AMDIL::T15_Z: + case AMDIL::T15_W: + case AMDIL::T15_XYZW: + return 15; + + case AMDIL::C137_X: + case AMDIL::C137_Y: + case AMDIL::C137_Z: + case AMDIL::C137_W: + return 137; + + case AMDIL::C81_X: + case AMDIL::C81_Y: + case AMDIL::C81_Z: + case AMDIL::C81_W: + case AMDIL::T81_X: + case AMDIL::T81_Y: + case AMDIL::T81_Z: + case AMDIL::T81_W: + case AMDIL::T81_XYZW: + return 81; + + case AMDIL::C60_X: + case AMDIL::C60_Y: + case AMDIL::C60_Z: + case AMDIL::C60_W: + case AMDIL::T60_X: + case AMDIL::T60_Y: + case AMDIL::T60_Z: + case AMDIL::T60_W: + case AMDIL::T60_XYZW: + return 60; + + case AMDIL::C101_X: + case AMDIL::C101_Y: + case AMDIL::C101_Z: + case AMDIL::C101_W: + case AMDIL::T101_X: + case AMDIL::T101_Y: + case AMDIL::T101_Z: + case AMDIL::T101_W: + case AMDIL::T101_XYZW: + return 101; + + case AMDIL::C73_X: + case AMDIL::C73_Y: + case AMDIL::C73_Z: + case AMDIL::C73_W: + case AMDIL::T73_X: + case AMDIL::T73_Y: + case AMDIL::T73_Z: + case AMDIL::T73_W: + case AMDIL::T73_XYZW: + return 73; + + case AMDIL::C86_X: + case AMDIL::C86_Y: + case AMDIL::C86_Z: + case AMDIL::C86_W: + case AMDIL::T86_X: + case AMDIL::T86_Y: + case AMDIL::T86_Z: + case AMDIL::T86_W: + case AMDIL::T86_XYZW: + return 86; + + case AMDIL::C76_X: + case AMDIL::C76_Y: + case AMDIL::C76_Z: + case AMDIL::C76_W: + case AMDIL::T76_X: + case AMDIL::T76_Y: + case AMDIL::T76_Z: + case AMDIL::T76_W: + case AMDIL::T76_XYZW: + return 76; + + case AMDIL::C62_X: + case AMDIL::C62_Y: + case AMDIL::C62_Z: + case AMDIL::C62_W: + case AMDIL::T62_X: + case AMDIL::T62_Y: + case AMDIL::T62_Z: + case AMDIL::T62_W: + case AMDIL::T62_XYZW: + return 62; + + case AMDIL::C247_X: + case AMDIL::C247_Y: + case AMDIL::C247_Z: + case AMDIL::C247_W: + return 247; + + case AMDIL::C67_X: + case AMDIL::C67_Y: + case AMDIL::C67_Z: + case AMDIL::C67_W: + case AMDIL::T67_X: + case AMDIL::T67_Y: + case AMDIL::T67_Z: + case AMDIL::T67_W: + case AMDIL::T67_XYZW: + return 67; + + case AMDIL::C204_X: + case AMDIL::C204_Y: + case AMDIL::C204_Z: + case AMDIL::C204_W: + return 204; + + case AMDIL::C241_X: + case AMDIL::C241_Y: + case AMDIL::C241_Z: + case AMDIL::C241_W: + return 241; + + case AMDIL::C165_X: + case AMDIL::C165_Y: + case AMDIL::C165_Z: + case AMDIL::C165_W: + return 165; + + case AMDIL::C198_X: + case AMDIL::C198_Y: + case AMDIL::C198_Z: + case AMDIL::C198_W: + return 198; + + case AMDIL::C139_X: + case AMDIL::C139_Y: + case AMDIL::C139_Z: + case AMDIL::C139_W: + return 139; + + case AMDIL::C129_X: + case AMDIL::C129_Y: + case AMDIL::C129_Z: + case AMDIL::C129_W: + return 129; + + case AMDIL::C2_X: + case AMDIL::C2_Y: + case AMDIL::C2_Z: + case AMDIL::C2_W: + case AMDIL::T2_X: + case AMDIL::T2_Y: + case AMDIL::T2_Z: + case AMDIL::T2_W: + case AMDIL::T2_XYZW: + return 2; + + case AMDIL::C17_X: + case AMDIL::C17_Y: + case AMDIL::C17_Z: + case AMDIL::C17_W: + case AMDIL::T17_X: + case AMDIL::T17_Y: + case AMDIL::T17_Z: + case AMDIL::T17_W: + case AMDIL::T17_XYZW: + return 17; + + case AMDIL::C186_X: + case AMDIL::C186_Y: + case AMDIL::C186_Z: + case AMDIL::C186_W: + return 186; + + case AMDIL::C110_X: + case AMDIL::C110_Y: + case AMDIL::C110_Z: + case AMDIL::C110_W: + case AMDIL::T110_X: + case AMDIL::T110_Y: + case AMDIL::T110_Z: + case AMDIL::T110_W: + case AMDIL::T110_XYZW: + return 110; + + case AMDIL::C82_X: + case AMDIL::C82_Y: + case AMDIL::C82_Z: + case AMDIL::C82_W: + case AMDIL::T82_X: + case AMDIL::T82_Y: + case AMDIL::T82_Z: + case AMDIL::T82_W: + case AMDIL::T82_XYZW: + return 82; + + case AMDIL::C147_X: + case AMDIL::C147_Y: + case AMDIL::C147_Z: + case AMDIL::C147_W: + return 147; + + case AMDIL::C228_X: + case AMDIL::C228_Y: + case AMDIL::C228_Z: + case AMDIL::C228_W: + return 228; + + case AMDIL::C236_X: + case AMDIL::C236_Y: + case AMDIL::C236_Z: + case AMDIL::C236_W: + return 236; + + case AMDIL::C249_X: + case AMDIL::C249_Y: + case AMDIL::C249_Z: + case AMDIL::C249_W: + return 249; + + case AMDIL::C218_X: + case AMDIL::C218_Y: + case AMDIL::C218_Z: + case AMDIL::C218_W: + return 218; + + case AMDIL::C202_X: + case AMDIL::C202_Y: + case AMDIL::C202_Z: + case AMDIL::C202_W: + return 202; + + case AMDIL::C168_X: + case AMDIL::C168_Y: + case AMDIL::C168_Z: + case AMDIL::C168_W: + return 168; + + case AMDIL::C184_X: + case AMDIL::C184_Y: + case AMDIL::C184_Z: + case AMDIL::C184_W: + return 184; + + case AMDIL::C135_X: + case AMDIL::C135_Y: + case AMDIL::C135_Z: + case AMDIL::C135_W: + return 135; + + case AMDIL::C14_X: + case AMDIL::C14_Y: + case AMDIL::C14_Z: + case AMDIL::C14_W: + case AMDIL::T14_X: + case AMDIL::T14_Y: + case AMDIL::T14_Z: + case AMDIL::T14_W: + case AMDIL::T14_XYZW: + return 14; + + case AMDIL::C112_X: + case AMDIL::C112_Y: + case AMDIL::C112_Z: + case AMDIL::C112_W: + case AMDIL::T112_X: + case AMDIL::T112_Y: + case AMDIL::T112_Z: + case AMDIL::T112_W: + case AMDIL::T112_XYZW: + return 112; + + case AMDIL::C69_X: + case AMDIL::C69_Y: + case AMDIL::C69_Z: + case AMDIL::C69_W: + case AMDIL::T69_X: + case AMDIL::T69_Y: + case AMDIL::T69_Z: + case AMDIL::T69_W: + case AMDIL::T69_XYZW: + return 69; + + case AMDIL::C191_X: + case AMDIL::C191_Y: + case AMDIL::C191_Z: + case AMDIL::C191_W: + return 191; + + case AMDIL::C172_X: + case AMDIL::C172_Y: + case AMDIL::C172_Z: + case AMDIL::C172_W: + return 172; + + case AMDIL::C145_X: + case AMDIL::C145_Y: + case AMDIL::C145_Z: + case AMDIL::C145_W: + return 145; + + case AMDIL::C49_X: + case AMDIL::C49_Y: + case AMDIL::C49_Z: + case AMDIL::C49_W: + case AMDIL::T49_X: + case AMDIL::T49_Y: + case AMDIL::T49_Z: + case AMDIL::T49_W: + case AMDIL::T49_XYZW: + return 49; + + case AMDIL::C178_X: + case AMDIL::C178_Y: + case AMDIL::C178_Z: + case AMDIL::C178_W: + return 178; + + case AMDIL::C24_X: + case AMDIL::C24_Y: + case AMDIL::C24_Z: + case AMDIL::C24_W: + case AMDIL::T24_X: + case AMDIL::T24_Y: + case AMDIL::T24_Z: + case AMDIL::T24_W: + case AMDIL::T24_XYZW: + return 24; + + case AMDIL::C224_X: + case AMDIL::C224_Y: + case AMDIL::C224_Z: + case AMDIL::C224_W: + return 224; + + case AMDIL::C187_X: + case AMDIL::C187_Y: + case AMDIL::C187_Z: + case AMDIL::C187_W: + return 187; + + case AMDIL::C140_X: + case AMDIL::C140_Y: + case AMDIL::C140_Z: + case AMDIL::C140_W: + return 140; + + case AMDIL::C223_X: + case AMDIL::C223_Y: + case AMDIL::C223_Z: + case AMDIL::C223_W: + return 223; + + case AMDIL::C124_X: + case AMDIL::C124_Y: + case AMDIL::C124_Z: + case AMDIL::C124_W: + case AMDIL::T124_X: + case AMDIL::T124_Y: + case AMDIL::T124_Z: + case AMDIL::T124_W: + case AMDIL::T124_XYZW: + return 124; + + case AMDIL::C104_X: + case AMDIL::C104_Y: + case AMDIL::C104_Z: + case AMDIL::C104_W: + case AMDIL::T104_X: + case AMDIL::T104_Y: + case AMDIL::T104_Z: + case AMDIL::T104_W: + case AMDIL::T104_XYZW: + return 104; + + case AMDIL::C131_X: + case AMDIL::C131_Y: + case AMDIL::C131_Z: + case AMDIL::C131_W: + return 131; + + case AMDIL::C181_X: + case AMDIL::C181_Y: + case AMDIL::C181_Z: + case AMDIL::C181_W: + return 181; + + case AMDIL::C234_X: + case AMDIL::C234_Y: + case AMDIL::C234_Z: + case AMDIL::C234_W: + return 234; + + case AMDIL::C121_X: + case AMDIL::C121_Y: + case AMDIL::C121_Z: + case AMDIL::C121_W: + case AMDIL::T121_X: + case AMDIL::T121_Y: + case AMDIL::T121_Z: + case AMDIL::T121_W: + case AMDIL::T121_XYZW: + return 121; + + case AMDIL::C79_X: + case AMDIL::C79_Y: + case AMDIL::C79_Z: + case AMDIL::C79_W: + case AMDIL::T79_X: + case AMDIL::T79_Y: + case AMDIL::T79_Z: + case AMDIL::T79_W: + case AMDIL::T79_XYZW: + return 79; + + case AMDIL::C212_X: + case AMDIL::C212_Y: + case AMDIL::C212_Z: + case AMDIL::C212_W: + return 212; + + case AMDIL::C154_X: + case AMDIL::C154_Y: + case AMDIL::C154_Z: + case AMDIL::C154_W: + return 154; + + case AMDIL::C0_X: + case AMDIL::C0_Y: + case AMDIL::C0_Z: + case AMDIL::C0_W: + case AMDIL::T0_X: + case AMDIL::T0_Y: + case AMDIL::T0_Z: + case AMDIL::T0_W: + case AMDIL::T0_XYZW: + return 0; + + case AMDIL::C23_X: + case AMDIL::C23_Y: + case AMDIL::C23_Z: + case AMDIL::C23_W: + case AMDIL::T23_X: + case AMDIL::T23_Y: + case AMDIL::T23_Z: + case AMDIL::T23_W: + case AMDIL::T23_XYZW: + return 23; + + case AMDIL::C96_X: + case AMDIL::C96_Y: + case AMDIL::C96_Z: + case AMDIL::C96_W: + case AMDIL::T96_X: + case AMDIL::T96_Y: + case AMDIL::T96_Z: + case AMDIL::T96_W: + case AMDIL::T96_XYZW: + return 96; + + case AMDIL::C126_X: + case AMDIL::C126_Y: + case AMDIL::C126_Z: + case AMDIL::C126_W: + case AMDIL::T126_X: + case AMDIL::T126_Y: + case AMDIL::T126_Z: + case AMDIL::T126_W: + case AMDIL::T126_XYZW: + return 126; + + case AMDIL::C238_X: + case AMDIL::C238_Y: + case AMDIL::C238_Z: + case AMDIL::C238_W: + return 238; + + case AMDIL::C159_X: + case AMDIL::C159_Y: + case AMDIL::C159_Z: + case AMDIL::C159_W: + return 159; + + case AMDIL::C251_X: + case AMDIL::C251_Y: + case AMDIL::C251_Z: + case AMDIL::C251_W: + return 251; + + case AMDIL::C253_X: + case AMDIL::C253_Y: + case AMDIL::C253_Z: + case AMDIL::C253_W: + return 253; + + case AMDIL::C160_X: + case AMDIL::C160_Y: + case AMDIL::C160_Z: + case AMDIL::C160_W: + return 160; + + case AMDIL::C176_X: + case AMDIL::C176_Y: + case AMDIL::C176_Z: + case AMDIL::C176_W: + return 176; + + case AMDIL::C47_X: + case AMDIL::C47_Y: + case AMDIL::C47_Z: + case AMDIL::C47_W: + case AMDIL::T47_X: + case AMDIL::T47_Y: + case AMDIL::T47_Z: + case AMDIL::T47_W: + case AMDIL::T47_XYZW: + return 47; + + case AMDIL::C8_X: + case AMDIL::C8_Y: + case AMDIL::C8_Z: + case AMDIL::C8_W: + case AMDIL::T8_X: + case AMDIL::T8_Y: + case AMDIL::T8_Z: + case AMDIL::T8_W: + case AMDIL::T8_XYZW: + return 8; + + case AMDIL::C209_X: + case AMDIL::C209_Y: + case AMDIL::C209_Z: + case AMDIL::C209_W: + return 209; + + case AMDIL::C98_X: + case AMDIL::C98_Y: + case AMDIL::C98_Z: + case AMDIL::C98_W: + case AMDIL::T98_X: + case AMDIL::T98_Y: + case AMDIL::T98_Z: + case AMDIL::T98_W: + case AMDIL::T98_XYZW: + return 98; + + case AMDIL::C216_X: + case AMDIL::C216_Y: + case AMDIL::C216_Z: + case AMDIL::C216_W: + return 216; + + case AMDIL::C37_X: + case AMDIL::C37_Y: + case AMDIL::C37_Z: + case AMDIL::C37_W: + case AMDIL::T37_X: + case AMDIL::T37_Y: + case AMDIL::T37_Z: + case AMDIL::T37_W: + case AMDIL::T37_XYZW: + return 37; + + case AMDIL::C117_X: + case AMDIL::C117_Y: + case AMDIL::C117_Z: + case AMDIL::C117_W: + case AMDIL::T117_X: + case AMDIL::T117_Y: + case AMDIL::T117_Z: + case AMDIL::T117_W: + case AMDIL::T117_XYZW: + return 117; + + case AMDIL::C43_X: + case AMDIL::C43_Y: + case AMDIL::C43_Z: + case AMDIL::C43_W: + case AMDIL::T43_X: + case AMDIL::T43_Y: + case AMDIL::T43_Z: + case AMDIL::T43_W: + case AMDIL::T43_XYZW: + return 43; + + case AMDIL::C195_X: + case AMDIL::C195_Y: + case AMDIL::C195_Z: + case AMDIL::C195_W: + return 195; + + case AMDIL::C5_X: + case AMDIL::C5_Y: + case AMDIL::C5_Z: + case AMDIL::C5_W: + case AMDIL::T5_X: + case AMDIL::T5_Y: + case AMDIL::T5_Z: + case AMDIL::T5_W: + case AMDIL::T5_XYZW: + return 5; + + case AMDIL::C170_X: + case AMDIL::C170_Y: + case AMDIL::C170_Z: + case AMDIL::C170_W: + return 170; + + case AMDIL::C33_X: + case AMDIL::C33_Y: + case AMDIL::C33_Z: + case AMDIL::C33_W: + case AMDIL::T33_X: + case AMDIL::T33_Y: + case AMDIL::T33_Z: + case AMDIL::T33_W: + case AMDIL::T33_XYZW: + return 33; + + case AMDIL::C21_X: + case AMDIL::C21_Y: + case AMDIL::C21_Z: + case AMDIL::C21_W: + case AMDIL::T21_X: + case AMDIL::T21_Y: + case AMDIL::T21_Z: + case AMDIL::T21_W: + case AMDIL::T21_XYZW: + return 21; + + case AMDIL::C63_X: + case AMDIL::C63_Y: + case AMDIL::C63_Z: + case AMDIL::C63_W: + case AMDIL::T63_X: + case AMDIL::T63_Y: + case AMDIL::T63_Z: + case AMDIL::T63_W: + case AMDIL::T63_XYZW: + return 63; + + case AMDIL::C7_X: + case AMDIL::C7_Y: + case AMDIL::C7_Z: + case AMDIL::C7_W: + case AMDIL::T7_X: + case AMDIL::T7_Y: + case AMDIL::T7_Z: + case AMDIL::T7_W: + case AMDIL::T7_XYZW: + return 7; + + case AMDIL::C227_X: + case AMDIL::C227_Y: + case AMDIL::C227_Z: + case AMDIL::C227_W: + return 227; + + case AMDIL::C26_X: + case AMDIL::C26_Y: + case AMDIL::C26_Z: + case AMDIL::C26_W: + case AMDIL::T26_X: + case AMDIL::T26_Y: + case AMDIL::T26_Z: + case AMDIL::T26_W: + case AMDIL::T26_XYZW: + return 26; + + case AMDIL::C80_X: + case AMDIL::C80_Y: + case AMDIL::C80_Z: + case AMDIL::C80_W: + case AMDIL::T80_X: + case AMDIL::T80_Y: + case AMDIL::T80_Z: + case AMDIL::T80_W: + case AMDIL::T80_XYZW: + return 80; + + case AMDIL::C193_X: + case AMDIL::C193_Y: + case AMDIL::C193_Z: + case AMDIL::C193_W: + return 193; + + case AMDIL::C119_X: + case AMDIL::C119_Y: + case AMDIL::C119_Z: + case AMDIL::C119_W: + case AMDIL::T119_X: + case AMDIL::T119_Y: + case AMDIL::T119_Z: + case AMDIL::T119_W: + case AMDIL::T119_XYZW: + return 119; + + case AMDIL::C180_X: + case AMDIL::C180_Y: + case AMDIL::C180_Z: + case AMDIL::C180_W: + return 180; + + case AMDIL::C99_X: + case AMDIL::C99_Y: + case AMDIL::C99_Z: + case AMDIL::C99_W: + case AMDIL::T99_X: + case AMDIL::T99_Y: + case AMDIL::T99_Z: + case AMDIL::T99_W: + case AMDIL::T99_XYZW: + return 99; + + case AMDIL::C244_X: + case AMDIL::C244_Y: + case AMDIL::C244_Z: + case AMDIL::C244_W: + return 244; + + case AMDIL::C179_X: + case AMDIL::C179_Y: + case AMDIL::C179_Z: + case AMDIL::C179_W: + return 179; + + case AMDIL::C162_X: + case AMDIL::C162_Y: + case AMDIL::C162_Z: + case AMDIL::C162_W: + return 162; + + case AMDIL::C72_X: + case AMDIL::C72_Y: + case AMDIL::C72_Z: + case AMDIL::C72_W: + case AMDIL::T72_X: + case AMDIL::T72_Y: + case AMDIL::T72_Z: + case AMDIL::T72_W: + case AMDIL::T72_XYZW: + return 72; + + case AMDIL::C255_X: + case AMDIL::C255_Y: + case AMDIL::C255_Z: + case AMDIL::C255_W: + return 255; + + case AMDIL::C246_X: + case AMDIL::C246_Y: + case AMDIL::C246_Z: + case AMDIL::C246_W: + return 246; + + case AMDIL::C240_X: + case AMDIL::C240_Y: + case AMDIL::C240_Z: + case AMDIL::C240_W: + return 240; + + case AMDIL::C74_X: + case AMDIL::C74_Y: + case AMDIL::C74_Z: + case AMDIL::C74_W: + case AMDIL::T74_X: + case AMDIL::T74_Y: + case AMDIL::T74_Z: + case AMDIL::T74_W: + case AMDIL::T74_XYZW: + return 74; + + case AMDIL::C182_X: + case AMDIL::C182_Y: + case AMDIL::C182_Z: + case AMDIL::C182_W: + return 182; + + case AMDIL::C61_X: + case AMDIL::C61_Y: + case AMDIL::C61_Z: + case AMDIL::C61_W: + case AMDIL::T61_X: + case AMDIL::T61_Y: + case AMDIL::T61_Z: + case AMDIL::T61_W: + case AMDIL::T61_XYZW: + return 61; + + case AMDIL::C230_X: + case AMDIL::C230_Y: + case AMDIL::C230_Z: + case AMDIL::C230_W: + return 230; + + case AMDIL::C108_X: + case AMDIL::C108_Y: + case AMDIL::C108_Z: + case AMDIL::C108_W: + case AMDIL::T108_X: + case AMDIL::T108_Y: + case AMDIL::T108_Z: + case AMDIL::T108_W: + case AMDIL::T108_XYZW: + return 108; + + case AMDIL::C115_X: + case AMDIL::C115_Y: + case AMDIL::C115_Z: + case AMDIL::C115_W: + case AMDIL::T115_X: + case AMDIL::T115_Y: + case AMDIL::T115_Z: + case AMDIL::T115_W: + case AMDIL::T115_XYZW: + return 115; + + case AMDIL::C92_X: + case AMDIL::C92_Y: + case AMDIL::C92_Z: + case AMDIL::C92_W: + case AMDIL::T92_X: + case AMDIL::T92_Y: + case AMDIL::T92_Z: + case AMDIL::T92_W: + case AMDIL::T92_XYZW: + return 92; + + case AMDIL::C103_X: + case AMDIL::C103_Y: + case AMDIL::C103_Z: + case AMDIL::C103_W: + case AMDIL::T103_X: + case AMDIL::T103_Y: + case AMDIL::T103_Z: + case AMDIL::T103_W: + case AMDIL::T103_XYZW: + return 103; + + case AMDIL::C201_X: + case AMDIL::C201_Y: + case AMDIL::C201_Z: + case AMDIL::C201_W: + return 201; + + case AMDIL::C232_X: + case AMDIL::C232_Y: + case AMDIL::C232_Z: + case AMDIL::C232_W: + return 232; + + case AMDIL::C10_X: + case AMDIL::C10_Y: + case AMDIL::C10_Z: + case AMDIL::C10_W: + case AMDIL::T10_X: + case AMDIL::T10_Y: + case AMDIL::T10_Z: + case AMDIL::T10_W: + case AMDIL::T10_XYZW: + return 10; + + case AMDIL::C113_X: + case AMDIL::C113_Y: + case AMDIL::C113_Z: + case AMDIL::C113_W: + case AMDIL::T113_X: + case AMDIL::T113_Y: + case AMDIL::T113_Z: + case AMDIL::T113_W: + case AMDIL::T113_XYZW: + return 113; + + case AMDIL::C152_X: + case AMDIL::C152_Y: + case AMDIL::C152_Z: + case AMDIL::C152_W: + return 152; + + case AMDIL::C189_X: + case AMDIL::C189_Y: + case AMDIL::C189_Z: + case AMDIL::C189_W: + return 189; + + case AMDIL::C225_X: + case AMDIL::C225_Y: + case AMDIL::C225_Z: + case AMDIL::C225_W: + return 225; + + case AMDIL::C207_X: + case AMDIL::C207_Y: + case AMDIL::C207_Z: + case AMDIL::C207_W: + return 207; + + case AMDIL::C142_X: + case AMDIL::C142_Y: + case AMDIL::C142_Z: + case AMDIL::C142_W: + return 142; + + case AMDIL::C91_X: + case AMDIL::C91_Y: + case AMDIL::C91_Z: + case AMDIL::C91_W: + case AMDIL::T91_X: + case AMDIL::T91_Y: + case AMDIL::T91_Z: + case AMDIL::T91_W: + case AMDIL::T91_XYZW: + return 91; + + case AMDIL::C167_X: + case AMDIL::C167_Y: + case AMDIL::C167_Z: + case AMDIL::C167_W: + return 167; + + case AMDIL::C48_X: + case AMDIL::C48_Y: + case AMDIL::C48_Z: + case AMDIL::C48_W: + case AMDIL::T48_X: + case AMDIL::T48_Y: + case AMDIL::T48_Z: + case AMDIL::T48_W: + case AMDIL::T48_XYZW: + return 48; + + case AMDIL::C107_X: + case AMDIL::C107_Y: + case AMDIL::C107_Z: + case AMDIL::C107_W: + case AMDIL::T107_X: + case AMDIL::T107_Y: + case AMDIL::T107_Z: + case AMDIL::T107_W: + case AMDIL::T107_XYZW: + return 107; + + case AMDIL::C87_X: + case AMDIL::C87_Y: + case AMDIL::C87_Z: + case AMDIL::C87_W: + case AMDIL::T87_X: + case AMDIL::T87_Y: + case AMDIL::T87_Z: + case AMDIL::T87_W: + case AMDIL::T87_XYZW: + return 87; + + case AMDIL::C174_X: + case AMDIL::C174_Y: + case AMDIL::C174_Z: + case AMDIL::C174_W: + return 174; + + case AMDIL::C77_X: + case AMDIL::C77_Y: + case AMDIL::C77_Z: + case AMDIL::C77_W: + case AMDIL::T77_X: + case AMDIL::T77_Y: + case AMDIL::T77_Z: + case AMDIL::T77_W: + case AMDIL::T77_XYZW: + return 77; + + case AMDIL::C214_X: + case AMDIL::C214_Y: + case AMDIL::C214_Z: + case AMDIL::C214_W: + return 214; + + case AMDIL::C133_X: + case AMDIL::C133_Y: + case AMDIL::C133_Z: + case AMDIL::C133_W: + return 133; + + case AMDIL::C149_X: + case AMDIL::C149_Y: + case AMDIL::C149_Z: + case AMDIL::C149_W: + return 149; + + case AMDIL::C123_X: + case AMDIL::C123_Y: + case AMDIL::C123_Z: + case AMDIL::C123_W: + case AMDIL::T123_X: + case AMDIL::T123_Y: + case AMDIL::T123_Z: + case AMDIL::T123_W: + case AMDIL::T123_XYZW: + return 123; + + case AMDIL::C221_X: + case AMDIL::C221_Y: + case AMDIL::C221_Z: + case AMDIL::C221_W: + return 221; + + case AMDIL::C50_X: + case AMDIL::C50_Y: + case AMDIL::C50_Z: + case AMDIL::C50_W: + case AMDIL::T50_X: + case AMDIL::T50_Y: + case AMDIL::T50_Z: + case AMDIL::T50_W: + case AMDIL::T50_XYZW: + return 50; + + case AMDIL::C39_X: + case AMDIL::C39_Y: + case AMDIL::C39_Z: + case AMDIL::C39_W: + case AMDIL::T39_X: + case AMDIL::T39_Y: + case AMDIL::T39_Z: + case AMDIL::T39_W: + case AMDIL::T39_XYZW: + return 39; + + case AMDIL::C210_X: + case AMDIL::C210_Y: + case AMDIL::C210_Z: + case AMDIL::C210_W: + return 210; + + case AMDIL::C64_X: + case AMDIL::C64_Y: + case AMDIL::C64_Z: + case AMDIL::C64_W: + case AMDIL::T64_X: + case AMDIL::T64_Y: + case AMDIL::T64_Z: + case AMDIL::T64_W: + case AMDIL::T64_XYZW: + return 64; + + case AMDIL::C97_X: + case AMDIL::C97_Y: + case AMDIL::C97_Z: + case AMDIL::C97_W: + case AMDIL::T97_X: + case AMDIL::T97_Y: + case AMDIL::T97_Z: + case AMDIL::T97_W: + case AMDIL::T97_XYZW: + return 97; + + case AMDIL::C12_X: + case AMDIL::C12_Y: + case AMDIL::C12_Z: + case AMDIL::C12_W: + case AMDIL::T12_X: + case AMDIL::T12_Y: + case AMDIL::T12_Z: + case AMDIL::T12_W: + case AMDIL::T12_XYZW: + return 12; + + case AMDIL::C41_X: + case AMDIL::C41_Y: + case AMDIL::C41_Z: + case AMDIL::C41_W: + case AMDIL::T41_X: + case AMDIL::T41_Y: + case AMDIL::T41_Z: + case AMDIL::T41_W: + case AMDIL::T41_XYZW: + return 41; + + case AMDIL::C52_X: + case AMDIL::C52_Y: + case AMDIL::C52_Z: + case AMDIL::C52_W: + case AMDIL::T52_X: + case AMDIL::T52_Y: + case AMDIL::T52_Z: + case AMDIL::T52_W: + case AMDIL::T52_XYZW: + return 52; + + case AMDIL::C173_X: + case AMDIL::C173_Y: + case AMDIL::C173_Z: + case AMDIL::C173_W: + return 173; + + case AMDIL::C56_X: + case AMDIL::C56_Y: + case AMDIL::C56_Z: + case AMDIL::C56_W: + case AMDIL::T56_X: + case AMDIL::T56_Y: + case AMDIL::T56_Z: + case AMDIL::T56_W: + case AMDIL::T56_XYZW: + return 56; + + case AMDIL::C229_X: + case AMDIL::C229_Y: + case AMDIL::C229_Z: + case AMDIL::C229_W: + return 229; + + case AMDIL::C45_X: + case AMDIL::C45_Y: + case AMDIL::C45_Z: + case AMDIL::C45_W: + case AMDIL::T45_X: + case AMDIL::T45_Y: + case AMDIL::T45_Z: + case AMDIL::T45_W: + case AMDIL::T45_XYZW: + return 45; + + case AMDIL::C66_X: + case AMDIL::C66_Y: + case AMDIL::C66_Z: + case AMDIL::C66_W: + case AMDIL::T66_X: + case AMDIL::T66_Y: + case AMDIL::T66_Z: + case AMDIL::T66_W: + case AMDIL::T66_XYZW: + return 66; + + case AMDIL::C19_X: + case AMDIL::C19_Y: + case AMDIL::C19_Z: + case AMDIL::C19_W: + case AMDIL::T19_X: + case AMDIL::T19_Y: + case AMDIL::T19_Z: + case AMDIL::T19_W: + case AMDIL::T19_XYZW: + return 19; + + case AMDIL::C54_X: + case AMDIL::C54_Y: + case AMDIL::C54_Z: + case AMDIL::C54_W: + case AMDIL::T54_X: + case AMDIL::T54_Y: + case AMDIL::T54_Z: + case AMDIL::T54_W: + case AMDIL::T54_XYZW: + return 54; + + case AMDIL::C237_X: + case AMDIL::C237_Y: + case AMDIL::C237_Z: + case AMDIL::C237_W: + return 237; + + case AMDIL::C70_X: + case AMDIL::C70_Y: + case AMDIL::C70_Z: + case AMDIL::C70_W: + case AMDIL::T70_X: + case AMDIL::T70_Y: + case AMDIL::T70_Z: + case AMDIL::T70_W: + case AMDIL::T70_XYZW: + return 70; + + case AMDIL::C188_X: + case AMDIL::C188_Y: + case AMDIL::C188_Z: + case AMDIL::C188_W: + return 188; + + case AMDIL::C68_X: + case AMDIL::C68_Y: + case AMDIL::C68_Z: + case AMDIL::C68_W: + case AMDIL::T68_X: + case AMDIL::T68_Y: + case AMDIL::T68_Z: + case AMDIL::T68_W: + case AMDIL::T68_XYZW: + return 68; + + case AMDIL::C166_X: + case AMDIL::C166_Y: + case AMDIL::C166_Z: + case AMDIL::C166_W: + return 166; + + case AMDIL::C1_X: + case AMDIL::C1_Y: + case AMDIL::C1_Z: + case AMDIL::C1_W: + case AMDIL::T1_X: + case AMDIL::T1_Y: + case AMDIL::T1_Z: + case AMDIL::T1_W: + case AMDIL::T1_XYZW: + return 1; + + case AMDIL::C136_X: + case AMDIL::C136_Y: + case AMDIL::C136_Z: + case AMDIL::C136_W: + return 136; + + case AMDIL::C88_X: + case AMDIL::C88_Y: + case AMDIL::C88_Z: + case AMDIL::C88_W: + case AMDIL::T88_X: + case AMDIL::T88_Y: + case AMDIL::T88_Z: + case AMDIL::T88_W: + case AMDIL::T88_XYZW: + return 88; + + case AMDIL::C116_X: + case AMDIL::C116_Y: + case AMDIL::C116_Z: + case AMDIL::C116_W: + case AMDIL::T116_X: + case AMDIL::T116_Y: + case AMDIL::T116_Z: + case AMDIL::T116_W: + case AMDIL::T116_XYZW: + return 116; + + case AMDIL::C144_X: + case AMDIL::C144_Y: + case AMDIL::C144_Z: + case AMDIL::C144_W: + return 144; + + case AMDIL::C141_X: + case AMDIL::C141_Y: + case AMDIL::C141_Z: + case AMDIL::C141_W: + return 141; + + case AMDIL::C30_X: + case AMDIL::C30_Y: + case AMDIL::C30_Z: + case AMDIL::C30_W: + case AMDIL::T30_X: + case AMDIL::T30_Y: + case AMDIL::T30_Z: + case AMDIL::T30_W: + case AMDIL::T30_XYZW: + return 30; + + case AMDIL::C100_X: + case AMDIL::C100_Y: + case AMDIL::C100_Z: + case AMDIL::C100_W: + case AMDIL::T100_X: + case AMDIL::T100_Y: + case AMDIL::T100_Z: + case AMDIL::T100_W: + case AMDIL::T100_XYZW: + return 100; + + case AMDIL::C222_X: + case AMDIL::C222_Y: + case AMDIL::C222_Z: + case AMDIL::C222_W: + return 222; + + case AMDIL::C128_X: + case AMDIL::C128_Y: + case AMDIL::C128_Z: + case AMDIL::C128_W: + return 128; + + case AMDIL::C25_X: + case AMDIL::C25_Y: + case AMDIL::C25_Z: + case AMDIL::C25_W: + case AMDIL::T25_X: + case AMDIL::T25_Y: + case AMDIL::T25_Z: + case AMDIL::T25_W: + case AMDIL::T25_XYZW: + return 25; + + case AMDIL::C252_X: + case AMDIL::C252_Y: + case AMDIL::C252_Z: + case AMDIL::C252_W: + return 252; + + case AMDIL::C28_X: + case AMDIL::C28_Y: + case AMDIL::C28_Z: + case AMDIL::C28_W: + case AMDIL::T28_X: + case AMDIL::T28_Y: + case AMDIL::T28_Z: + case AMDIL::T28_W: + case AMDIL::T28_XYZW: + return 28; + + case AMDIL::C120_X: + case AMDIL::C120_Y: + case AMDIL::C120_Z: + case AMDIL::C120_W: + case AMDIL::T120_X: + case AMDIL::T120_Y: + case AMDIL::T120_Z: + case AMDIL::T120_W: + case AMDIL::T120_XYZW: + return 120; + + case AMDIL::C156_X: + case AMDIL::C156_Y: + case AMDIL::C156_Z: + case AMDIL::C156_W: + return 156; + + case AMDIL::C134_X: + case AMDIL::C134_Y: + case AMDIL::C134_Z: + case AMDIL::C134_W: + return 134; + + case AMDIL::C40_X: + case AMDIL::C40_Y: + case AMDIL::C40_Z: + case AMDIL::C40_W: + case AMDIL::T40_X: + case AMDIL::T40_Y: + case AMDIL::T40_Z: + case AMDIL::T40_W: + case AMDIL::T40_XYZW: + return 40; + + case AMDIL::C75_X: + case AMDIL::C75_Y: + case AMDIL::C75_Z: + case AMDIL::C75_W: + case AMDIL::T75_X: + case AMDIL::T75_Y: + case AMDIL::T75_Z: + case AMDIL::T75_W: + case AMDIL::T75_XYZW: + return 75; + + case AMDIL::C83_X: + case AMDIL::C83_Y: + case AMDIL::C83_Z: + case AMDIL::C83_W: + case AMDIL::T83_X: + case AMDIL::T83_Y: + case AMDIL::T83_Z: + case AMDIL::T83_W: + case AMDIL::T83_XYZW: + return 83; + + case AMDIL::C250_X: + case AMDIL::C250_Y: + case AMDIL::C250_Z: + case AMDIL::C250_W: + return 250; + + case AMDIL::C192_X: + case AMDIL::C192_Y: + case AMDIL::C192_Z: + case AMDIL::C192_W: + return 192; + + case AMDIL::C59_X: + case AMDIL::C59_Y: + case AMDIL::C59_Z: + case AMDIL::C59_W: + case AMDIL::T59_X: + case AMDIL::T59_Y: + case AMDIL::T59_Z: + case AMDIL::T59_W: + case AMDIL::T59_XYZW: + return 59; + + case AMDIL::C254_X: + case AMDIL::C254_Y: + case AMDIL::C254_Z: + case AMDIL::C254_W: + return 254; + + case AMDIL::C215_X: + case AMDIL::C215_Y: + case AMDIL::C215_Z: + case AMDIL::C215_W: + return 215; + + case AMDIL::C177_X: + case AMDIL::C177_Y: + case AMDIL::C177_Z: + case AMDIL::C177_W: + return 177; + + case AMDIL::C150_X: + case AMDIL::C150_Y: + case AMDIL::C150_Z: + case AMDIL::C150_W: + return 150; + + case AMDIL::C155_X: + case AMDIL::C155_Y: + case AMDIL::C155_Z: + case AMDIL::C155_W: + return 155; + + case AMDIL::C130_X: + case AMDIL::C130_Y: + case AMDIL::C130_Z: + case AMDIL::C130_W: + return 130; + + case AMDIL::C217_X: + case AMDIL::C217_Y: + case AMDIL::C217_Z: + case AMDIL::C217_W: + return 217; + + case AMDIL::C53_X: + case AMDIL::C53_Y: + case AMDIL::C53_Z: + case AMDIL::C53_W: + case AMDIL::T53_X: + case AMDIL::T53_Y: + case AMDIL::T53_Z: + case AMDIL::T53_W: + case AMDIL::T53_XYZW: + return 53; + + case AMDIL::C245_X: + case AMDIL::C245_Y: + case AMDIL::C245_Z: + case AMDIL::C245_W: + return 245; + + case AMDIL::C239_X: + case AMDIL::C239_Y: + case AMDIL::C239_Z: + case AMDIL::C239_W: + return 239; + + case AMDIL::C122_X: + case AMDIL::C122_Y: + case AMDIL::C122_Z: + case AMDIL::C122_W: + case AMDIL::T122_X: + case AMDIL::T122_Y: + case AMDIL::T122_Z: + case AMDIL::T122_W: + case AMDIL::T122_XYZW: + return 122; + + case AMDIL::C143_X: + case AMDIL::C143_Y: + case AMDIL::C143_Z: + case AMDIL::C143_W: + return 143; + + case AMDIL::C205_X: + case AMDIL::C205_Y: + case AMDIL::C205_Z: + case AMDIL::C205_W: + return 205; + + case AMDIL::C158_X: + case AMDIL::C158_Y: + case AMDIL::C158_Z: + case AMDIL::C158_W: + return 158; + + case AMDIL::C42_X: + case AMDIL::C42_Y: + case AMDIL::C42_Z: + case AMDIL::C42_W: + case AMDIL::T42_X: + case AMDIL::T42_Y: + case AMDIL::T42_Z: + case AMDIL::T42_W: + case AMDIL::T42_XYZW: + return 42; + + case AMDIL::C22_X: + case AMDIL::C22_Y: + case AMDIL::C22_Z: + case AMDIL::C22_W: + case AMDIL::T22_X: + case AMDIL::T22_Y: + case AMDIL::T22_Z: + case AMDIL::T22_W: + case AMDIL::T22_XYZW: + return 22; + + case AMDIL::C219_X: + case AMDIL::C219_Y: + case AMDIL::C219_Z: + case AMDIL::C219_W: + return 219; + + case AMDIL::C46_X: + case AMDIL::C46_Y: + case AMDIL::C46_Z: + case AMDIL::C46_W: + case AMDIL::T46_X: + case AMDIL::T46_Y: + case AMDIL::T46_Z: + case AMDIL::T46_W: + case AMDIL::T46_XYZW: + return 46; + + case AMDIL::C13_X: + case AMDIL::C13_Y: + case AMDIL::C13_Z: + case AMDIL::C13_W: + case AMDIL::T13_X: + case AMDIL::T13_Y: + case AMDIL::T13_Z: + case AMDIL::T13_W: + case AMDIL::T13_XYZW: + return 13; + + case AMDIL::C235_X: + case AMDIL::C235_Y: + case AMDIL::C235_Z: + case AMDIL::C235_W: + return 235; + + case AMDIL::C105_X: + case AMDIL::C105_Y: + case AMDIL::C105_Z: + case AMDIL::C105_W: + case AMDIL::T105_X: + case AMDIL::T105_Y: + case AMDIL::T105_Z: + case AMDIL::T105_W: + case AMDIL::T105_XYZW: + return 105; + + case AMDIL::C6_X: + case AMDIL::C6_Y: + case AMDIL::C6_Z: + case AMDIL::C6_W: + case AMDIL::T6_X: + case AMDIL::T6_Y: + case AMDIL::T6_Z: + case AMDIL::T6_W: + case AMDIL::T6_XYZW: + return 6; + + case AMDIL::C85_X: + case AMDIL::C85_Y: + case AMDIL::C85_Z: + case AMDIL::C85_W: + case AMDIL::T85_X: + case AMDIL::T85_Y: + case AMDIL::T85_Z: + case AMDIL::T85_W: + case AMDIL::T85_XYZW: + return 85; + + case AMDIL::C185_X: + case AMDIL::C185_Y: + case AMDIL::C185_Z: + case AMDIL::C185_W: + return 185; + + case AMDIL::C36_X: + case AMDIL::C36_Y: + case AMDIL::C36_Z: + case AMDIL::C36_W: + case AMDIL::T36_X: + case AMDIL::T36_Y: + case AMDIL::T36_Z: + case AMDIL::T36_W: + case AMDIL::T36_XYZW: + return 36; + + case AMDIL::C3_X: + case AMDIL::C3_Y: + case AMDIL::C3_Z: + case AMDIL::C3_W: + case AMDIL::T3_X: + case AMDIL::T3_Y: + case AMDIL::T3_Z: + case AMDIL::T3_W: + case AMDIL::T3_XYZW: + return 3; + + case AMDIL::C248_X: + case AMDIL::C248_Y: + case AMDIL::C248_Z: + case AMDIL::C248_W: + return 248; + + case AMDIL::C213_X: + case AMDIL::C213_Y: + case AMDIL::C213_Z: + case AMDIL::C213_W: + return 213; + + case AMDIL::C183_X: + case AMDIL::C183_Y: + case AMDIL::C183_Z: + case AMDIL::C183_W: + return 183; + + case AMDIL::C94_X: + case AMDIL::C94_Y: + case AMDIL::C94_Z: + case AMDIL::C94_W: + case AMDIL::T94_X: + case AMDIL::T94_Y: + case AMDIL::T94_Z: + case AMDIL::T94_W: + case AMDIL::T94_XYZW: + return 94; + + case AMDIL::C146_X: + case AMDIL::C146_Y: + case AMDIL::C146_Z: + case AMDIL::C146_W: + return 146; + + case AMDIL::C51_X: + case AMDIL::C51_Y: + case AMDIL::C51_Z: + case AMDIL::C51_W: + case AMDIL::T51_X: + case AMDIL::T51_Y: + case AMDIL::T51_Z: + case AMDIL::T51_W: + case AMDIL::T51_XYZW: + return 51; + + case AMDIL::C9_X: + case AMDIL::C9_Y: + case AMDIL::C9_Z: + case AMDIL::C9_W: + case AMDIL::T9_X: + case AMDIL::T9_Y: + case AMDIL::T9_Z: + case AMDIL::T9_W: + case AMDIL::T9_XYZW: + return 9; + + case AMDIL::C111_X: + case AMDIL::C111_Y: + case AMDIL::C111_Z: + case AMDIL::C111_W: + case AMDIL::T111_X: + case AMDIL::T111_Y: + case AMDIL::T111_Z: + case AMDIL::T111_W: + case AMDIL::T111_XYZW: + return 111; + + case AMDIL::C38_X: + case AMDIL::C38_Y: + case AMDIL::C38_Z: + case AMDIL::C38_W: + case AMDIL::T38_X: + case AMDIL::T38_Y: + case AMDIL::T38_Z: + case AMDIL::T38_W: + case AMDIL::T38_XYZW: + return 38; + + case AMDIL::C4_X: + case AMDIL::C4_Y: + case AMDIL::C4_Z: + case AMDIL::C4_W: + case AMDIL::T4_X: + case AMDIL::T4_Y: + case AMDIL::T4_Z: + case AMDIL::T4_W: + case AMDIL::T4_XYZW: + return 4; + + case AMDIL::C34_X: + case AMDIL::C34_Y: + case AMDIL::C34_Z: + case AMDIL::C34_W: + case AMDIL::T34_X: + case AMDIL::T34_Y: + case AMDIL::T34_Z: + case AMDIL::T34_W: + case AMDIL::T34_XYZW: + return 34; + + case AMDIL::C169_X: + case AMDIL::C169_Y: + case AMDIL::C169_Z: + case AMDIL::C169_W: + return 169; + + case AMDIL::C164_X: + case AMDIL::C164_Y: + case AMDIL::C164_Z: + case AMDIL::C164_W: + return 164; + + case AMDIL::C132_X: + case AMDIL::C132_Y: + case AMDIL::C132_Z: + case AMDIL::C132_W: + return 132; + + case AMDIL::C196_X: + case AMDIL::C196_Y: + case AMDIL::C196_Z: + case AMDIL::C196_W: + return 196; + + case AMDIL::C171_X: + case AMDIL::C171_Y: + case AMDIL::C171_Z: + case AMDIL::C171_W: + return 171; + + case AMDIL::C242_X: + case AMDIL::C242_Y: + case AMDIL::C242_Z: + case AMDIL::C242_W: + return 242; + + } +} + + +unsigned R600RegisterInfo::getHWRegChanGen(unsigned reg) const +{ + switch(reg) { + default: assert(!"Unknown register"); return 0; + case AMDIL::C0_Z: + case AMDIL::C1_Z: + case AMDIL::C2_Z: + case AMDIL::C3_Z: + case AMDIL::C4_Z: + case AMDIL::C5_Z: + case AMDIL::C6_Z: + case AMDIL::C7_Z: + case AMDIL::C8_Z: + case AMDIL::C9_Z: + case AMDIL::C10_Z: + case AMDIL::C11_Z: + case AMDIL::C12_Z: + case AMDIL::C13_Z: + case AMDIL::C14_Z: + case AMDIL::C15_Z: + case AMDIL::C16_Z: + case AMDIL::C17_Z: + case AMDIL::C18_Z: + case AMDIL::C19_Z: + case AMDIL::C20_Z: + case AMDIL::C21_Z: + case AMDIL::C22_Z: + case AMDIL::C23_Z: + case AMDIL::C24_Z: + case AMDIL::C25_Z: + case AMDIL::C26_Z: + case AMDIL::C27_Z: + case AMDIL::C28_Z: + case AMDIL::C29_Z: + case AMDIL::C30_Z: + case AMDIL::C31_Z: + case AMDIL::C32_Z: + case AMDIL::C33_Z: + case AMDIL::C34_Z: + case AMDIL::C35_Z: + case AMDIL::C36_Z: + case AMDIL::C37_Z: + case AMDIL::C38_Z: + case AMDIL::C39_Z: + case AMDIL::C40_Z: + case AMDIL::C41_Z: + case AMDIL::C42_Z: + case AMDIL::C43_Z: + case AMDIL::C44_Z: + case AMDIL::C45_Z: + case AMDIL::C46_Z: + case AMDIL::C47_Z: + case AMDIL::C48_Z: + case AMDIL::C49_Z: + case AMDIL::C50_Z: + case AMDIL::C51_Z: + case AMDIL::C52_Z: + case AMDIL::C53_Z: + case AMDIL::C54_Z: + case AMDIL::C55_Z: + case AMDIL::C56_Z: + case AMDIL::C57_Z: + case AMDIL::C58_Z: + case AMDIL::C59_Z: + case AMDIL::C60_Z: + case AMDIL::C61_Z: + case AMDIL::C62_Z: + case AMDIL::C63_Z: + case AMDIL::C64_Z: + case AMDIL::C65_Z: + case AMDIL::C66_Z: + case AMDIL::C67_Z: + case AMDIL::C68_Z: + case AMDIL::C69_Z: + case AMDIL::C70_Z: + case AMDIL::C71_Z: + case AMDIL::C72_Z: + case AMDIL::C73_Z: + case AMDIL::C74_Z: + case AMDIL::C75_Z: + case AMDIL::C76_Z: + case AMDIL::C77_Z: + case AMDIL::C78_Z: + case AMDIL::C79_Z: + case AMDIL::C80_Z: + case AMDIL::C81_Z: + case AMDIL::C82_Z: + case AMDIL::C83_Z: + case AMDIL::C84_Z: + case AMDIL::C85_Z: + case AMDIL::C86_Z: + case AMDIL::C87_Z: + case AMDIL::C88_Z: + case AMDIL::C89_Z: + case AMDIL::C90_Z: + case AMDIL::C91_Z: + case AMDIL::C92_Z: + case AMDIL::C93_Z: + case AMDIL::C94_Z: + case AMDIL::C95_Z: + case AMDIL::C96_Z: + case AMDIL::C97_Z: + case AMDIL::C98_Z: + case AMDIL::C99_Z: + case AMDIL::C100_Z: + case AMDIL::C101_Z: + case AMDIL::C102_Z: + case AMDIL::C103_Z: + case AMDIL::C104_Z: + case AMDIL::C105_Z: + case AMDIL::C106_Z: + case AMDIL::C107_Z: + case AMDIL::C108_Z: + case AMDIL::C109_Z: + case AMDIL::C110_Z: + case AMDIL::C111_Z: + case AMDIL::C112_Z: + case AMDIL::C113_Z: + case AMDIL::C114_Z: + case AMDIL::C115_Z: + case AMDIL::C116_Z: + case AMDIL::C117_Z: + case AMDIL::C118_Z: + case AMDIL::C119_Z: + case AMDIL::C120_Z: + case AMDIL::C121_Z: + case AMDIL::C122_Z: + case AMDIL::C123_Z: + case AMDIL::C124_Z: + case AMDIL::C125_Z: + case AMDIL::C126_Z: + case AMDIL::C127_Z: + case AMDIL::C128_Z: + case AMDIL::C129_Z: + case AMDIL::C130_Z: + case AMDIL::C131_Z: + case AMDIL::C132_Z: + case AMDIL::C133_Z: + case AMDIL::C134_Z: + case AMDIL::C135_Z: + case AMDIL::C136_Z: + case AMDIL::C137_Z: + case AMDIL::C138_Z: + case AMDIL::C139_Z: + case AMDIL::C140_Z: + case AMDIL::C141_Z: + case AMDIL::C142_Z: + case AMDIL::C143_Z: + case AMDIL::C144_Z: + case AMDIL::C145_Z: + case AMDIL::C146_Z: + case AMDIL::C147_Z: + case AMDIL::C148_Z: + case AMDIL::C149_Z: + case AMDIL::C150_Z: + case AMDIL::C151_Z: + case AMDIL::C152_Z: + case AMDIL::C153_Z: + case AMDIL::C154_Z: + case AMDIL::C155_Z: + case AMDIL::C156_Z: + case AMDIL::C157_Z: + case AMDIL::C158_Z: + case AMDIL::C159_Z: + case AMDIL::C160_Z: + case AMDIL::C161_Z: + case AMDIL::C162_Z: + case AMDIL::C163_Z: + case AMDIL::C164_Z: + case AMDIL::C165_Z: + case AMDIL::C166_Z: + case AMDIL::C167_Z: + case AMDIL::C168_Z: + case AMDIL::C169_Z: + case AMDIL::C170_Z: + case AMDIL::C171_Z: + case AMDIL::C172_Z: + case AMDIL::C173_Z: + case AMDIL::C174_Z: + case AMDIL::C175_Z: + case AMDIL::C176_Z: + case AMDIL::C177_Z: + case AMDIL::C178_Z: + case AMDIL::C179_Z: + case AMDIL::C180_Z: + case AMDIL::C181_Z: + case AMDIL::C182_Z: + case AMDIL::C183_Z: + case AMDIL::C184_Z: + case AMDIL::C185_Z: + case AMDIL::C186_Z: + case AMDIL::C187_Z: + case AMDIL::C188_Z: + case AMDIL::C189_Z: + case AMDIL::C190_Z: + case AMDIL::C191_Z: + case AMDIL::C192_Z: + case AMDIL::C193_Z: + case AMDIL::C194_Z: + case AMDIL::C195_Z: + case AMDIL::C196_Z: + case AMDIL::C197_Z: + case AMDIL::C198_Z: + case AMDIL::C199_Z: + case AMDIL::C200_Z: + case AMDIL::C201_Z: + case AMDIL::C202_Z: + case AMDIL::C203_Z: + case AMDIL::C204_Z: + case AMDIL::C205_Z: + case AMDIL::C206_Z: + case AMDIL::C207_Z: + case AMDIL::C208_Z: + case AMDIL::C209_Z: + case AMDIL::C210_Z: + case AMDIL::C211_Z: + case AMDIL::C212_Z: + case AMDIL::C213_Z: + case AMDIL::C214_Z: + case AMDIL::C215_Z: + case AMDIL::C216_Z: + case AMDIL::C217_Z: + case AMDIL::C218_Z: + case AMDIL::C219_Z: + case AMDIL::C220_Z: + case AMDIL::C221_Z: + case AMDIL::C222_Z: + case AMDIL::C223_Z: + case AMDIL::C224_Z: + case AMDIL::C225_Z: + case AMDIL::C226_Z: + case AMDIL::C227_Z: + case AMDIL::C228_Z: + case AMDIL::C229_Z: + case AMDIL::C230_Z: + case AMDIL::C231_Z: + case AMDIL::C232_Z: + case AMDIL::C233_Z: + case AMDIL::C234_Z: + case AMDIL::C235_Z: + case AMDIL::C236_Z: + case AMDIL::C237_Z: + case AMDIL::C238_Z: + case AMDIL::C239_Z: + case AMDIL::C240_Z: + case AMDIL::C241_Z: + case AMDIL::C242_Z: + case AMDIL::C243_Z: + case AMDIL::C244_Z: + case AMDIL::C245_Z: + case AMDIL::C246_Z: + case AMDIL::C247_Z: + case AMDIL::C248_Z: + case AMDIL::C249_Z: + case AMDIL::C250_Z: + case AMDIL::C251_Z: + case AMDIL::C252_Z: + case AMDIL::C253_Z: + case AMDIL::C254_Z: + case AMDIL::C255_Z: + case AMDIL::T0_Z: + case AMDIL::T1_Z: + case AMDIL::T2_Z: + case AMDIL::T3_Z: + case AMDIL::T4_Z: + case AMDIL::T5_Z: + case AMDIL::T6_Z: + case AMDIL::T7_Z: + case AMDIL::T8_Z: + case AMDIL::T9_Z: + case AMDIL::T10_Z: + case AMDIL::T11_Z: + case AMDIL::T12_Z: + case AMDIL::T13_Z: + case AMDIL::T14_Z: + case AMDIL::T15_Z: + case AMDIL::T16_Z: + case AMDIL::T17_Z: + case AMDIL::T18_Z: + case AMDIL::T19_Z: + case AMDIL::T20_Z: + case AMDIL::T21_Z: + case AMDIL::T22_Z: + case AMDIL::T23_Z: + case AMDIL::T24_Z: + case AMDIL::T25_Z: + case AMDIL::T26_Z: + case AMDIL::T27_Z: + case AMDIL::T28_Z: + case AMDIL::T29_Z: + case AMDIL::T30_Z: + case AMDIL::T31_Z: + case AMDIL::T32_Z: + case AMDIL::T33_Z: + case AMDIL::T34_Z: + case AMDIL::T35_Z: + case AMDIL::T36_Z: + case AMDIL::T37_Z: + case AMDIL::T38_Z: + case AMDIL::T39_Z: + case AMDIL::T40_Z: + case AMDIL::T41_Z: + case AMDIL::T42_Z: + case AMDIL::T43_Z: + case AMDIL::T44_Z: + case AMDIL::T45_Z: + case AMDIL::T46_Z: + case AMDIL::T47_Z: + case AMDIL::T48_Z: + case AMDIL::T49_Z: + case AMDIL::T50_Z: + case AMDIL::T51_Z: + case AMDIL::T52_Z: + case AMDIL::T53_Z: + case AMDIL::T54_Z: + case AMDIL::T55_Z: + case AMDIL::T56_Z: + case AMDIL::T57_Z: + case AMDIL::T58_Z: + case AMDIL::T59_Z: + case AMDIL::T60_Z: + case AMDIL::T61_Z: + case AMDIL::T62_Z: + case AMDIL::T63_Z: + case AMDIL::T64_Z: + case AMDIL::T65_Z: + case AMDIL::T66_Z: + case AMDIL::T67_Z: + case AMDIL::T68_Z: + case AMDIL::T69_Z: + case AMDIL::T70_Z: + case AMDIL::T71_Z: + case AMDIL::T72_Z: + case AMDIL::T73_Z: + case AMDIL::T74_Z: + case AMDIL::T75_Z: + case AMDIL::T76_Z: + case AMDIL::T77_Z: + case AMDIL::T78_Z: + case AMDIL::T79_Z: + case AMDIL::T80_Z: + case AMDIL::T81_Z: + case AMDIL::T82_Z: + case AMDIL::T83_Z: + case AMDIL::T84_Z: + case AMDIL::T85_Z: + case AMDIL::T86_Z: + case AMDIL::T87_Z: + case AMDIL::T88_Z: + case AMDIL::T89_Z: + case AMDIL::T90_Z: + case AMDIL::T91_Z: + case AMDIL::T92_Z: + case AMDIL::T93_Z: + case AMDIL::T94_Z: + case AMDIL::T95_Z: + case AMDIL::T96_Z: + case AMDIL::T97_Z: + case AMDIL::T98_Z: + case AMDIL::T99_Z: + case AMDIL::T100_Z: + case AMDIL::T101_Z: + case AMDIL::T102_Z: + case AMDIL::T103_Z: + case AMDIL::T104_Z: + case AMDIL::T105_Z: + case AMDIL::T106_Z: + case AMDIL::T107_Z: + case AMDIL::T108_Z: + case AMDIL::T109_Z: + case AMDIL::T110_Z: + case AMDIL::T111_Z: + case AMDIL::T112_Z: + case AMDIL::T113_Z: + case AMDIL::T114_Z: + case AMDIL::T115_Z: + case AMDIL::T116_Z: + case AMDIL::T117_Z: + case AMDIL::T118_Z: + case AMDIL::T119_Z: + case AMDIL::T120_Z: + case AMDIL::T121_Z: + case AMDIL::T122_Z: + case AMDIL::T123_Z: + case AMDIL::T124_Z: + case AMDIL::T125_Z: + case AMDIL::T126_Z: + case AMDIL::T127_Z: + return 2; + + case AMDIL::C0_W: + case AMDIL::C1_W: + case AMDIL::C2_W: + case AMDIL::C3_W: + case AMDIL::C4_W: + case AMDIL::C5_W: + case AMDIL::C6_W: + case AMDIL::C7_W: + case AMDIL::C8_W: + case AMDIL::C9_W: + case AMDIL::C10_W: + case AMDIL::C11_W: + case AMDIL::C12_W: + case AMDIL::C13_W: + case AMDIL::C14_W: + case AMDIL::C15_W: + case AMDIL::C16_W: + case AMDIL::C17_W: + case AMDIL::C18_W: + case AMDIL::C19_W: + case AMDIL::C20_W: + case AMDIL::C21_W: + case AMDIL::C22_W: + case AMDIL::C23_W: + case AMDIL::C24_W: + case AMDIL::C25_W: + case AMDIL::C26_W: + case AMDIL::C27_W: + case AMDIL::C28_W: + case AMDIL::C29_W: + case AMDIL::C30_W: + case AMDIL::C31_W: + case AMDIL::C32_W: + case AMDIL::C33_W: + case AMDIL::C34_W: + case AMDIL::C35_W: + case AMDIL::C36_W: + case AMDIL::C37_W: + case AMDIL::C38_W: + case AMDIL::C39_W: + case AMDIL::C40_W: + case AMDIL::C41_W: + case AMDIL::C42_W: + case AMDIL::C43_W: + case AMDIL::C44_W: + case AMDIL::C45_W: + case AMDIL::C46_W: + case AMDIL::C47_W: + case AMDIL::C48_W: + case AMDIL::C49_W: + case AMDIL::C50_W: + case AMDIL::C51_W: + case AMDIL::C52_W: + case AMDIL::C53_W: + case AMDIL::C54_W: + case AMDIL::C55_W: + case AMDIL::C56_W: + case AMDIL::C57_W: + case AMDIL::C58_W: + case AMDIL::C59_W: + case AMDIL::C60_W: + case AMDIL::C61_W: + case AMDIL::C62_W: + case AMDIL::C63_W: + case AMDIL::C64_W: + case AMDIL::C65_W: + case AMDIL::C66_W: + case AMDIL::C67_W: + case AMDIL::C68_W: + case AMDIL::C69_W: + case AMDIL::C70_W: + case AMDIL::C71_W: + case AMDIL::C72_W: + case AMDIL::C73_W: + case AMDIL::C74_W: + case AMDIL::C75_W: + case AMDIL::C76_W: + case AMDIL::C77_W: + case AMDIL::C78_W: + case AMDIL::C79_W: + case AMDIL::C80_W: + case AMDIL::C81_W: + case AMDIL::C82_W: + case AMDIL::C83_W: + case AMDIL::C84_W: + case AMDIL::C85_W: + case AMDIL::C86_W: + case AMDIL::C87_W: + case AMDIL::C88_W: + case AMDIL::C89_W: + case AMDIL::C90_W: + case AMDIL::C91_W: + case AMDIL::C92_W: + case AMDIL::C93_W: + case AMDIL::C94_W: + case AMDIL::C95_W: + case AMDIL::C96_W: + case AMDIL::C97_W: + case AMDIL::C98_W: + case AMDIL::C99_W: + case AMDIL::C100_W: + case AMDIL::C101_W: + case AMDIL::C102_W: + case AMDIL::C103_W: + case AMDIL::C104_W: + case AMDIL::C105_W: + case AMDIL::C106_W: + case AMDIL::C107_W: + case AMDIL::C108_W: + case AMDIL::C109_W: + case AMDIL::C110_W: + case AMDIL::C111_W: + case AMDIL::C112_W: + case AMDIL::C113_W: + case AMDIL::C114_W: + case AMDIL::C115_W: + case AMDIL::C116_W: + case AMDIL::C117_W: + case AMDIL::C118_W: + case AMDIL::C119_W: + case AMDIL::C120_W: + case AMDIL::C121_W: + case AMDIL::C122_W: + case AMDIL::C123_W: + case AMDIL::C124_W: + case AMDIL::C125_W: + case AMDIL::C126_W: + case AMDIL::C127_W: + case AMDIL::C128_W: + case AMDIL::C129_W: + case AMDIL::C130_W: + case AMDIL::C131_W: + case AMDIL::C132_W: + case AMDIL::C133_W: + case AMDIL::C134_W: + case AMDIL::C135_W: + case AMDIL::C136_W: + case AMDIL::C137_W: + case AMDIL::C138_W: + case AMDIL::C139_W: + case AMDIL::C140_W: + case AMDIL::C141_W: + case AMDIL::C142_W: + case AMDIL::C143_W: + case AMDIL::C144_W: + case AMDIL::C145_W: + case AMDIL::C146_W: + case AMDIL::C147_W: + case AMDIL::C148_W: + case AMDIL::C149_W: + case AMDIL::C150_W: + case AMDIL::C151_W: + case AMDIL::C152_W: + case AMDIL::C153_W: + case AMDIL::C154_W: + case AMDIL::C155_W: + case AMDIL::C156_W: + case AMDIL::C157_W: + case AMDIL::C158_W: + case AMDIL::C159_W: + case AMDIL::C160_W: + case AMDIL::C161_W: + case AMDIL::C162_W: + case AMDIL::C163_W: + case AMDIL::C164_W: + case AMDIL::C165_W: + case AMDIL::C166_W: + case AMDIL::C167_W: + case AMDIL::C168_W: + case AMDIL::C169_W: + case AMDIL::C170_W: + case AMDIL::C171_W: + case AMDIL::C172_W: + case AMDIL::C173_W: + case AMDIL::C174_W: + case AMDIL::C175_W: + case AMDIL::C176_W: + case AMDIL::C177_W: + case AMDIL::C178_W: + case AMDIL::C179_W: + case AMDIL::C180_W: + case AMDIL::C181_W: + case AMDIL::C182_W: + case AMDIL::C183_W: + case AMDIL::C184_W: + case AMDIL::C185_W: + case AMDIL::C186_W: + case AMDIL::C187_W: + case AMDIL::C188_W: + case AMDIL::C189_W: + case AMDIL::C190_W: + case AMDIL::C191_W: + case AMDIL::C192_W: + case AMDIL::C193_W: + case AMDIL::C194_W: + case AMDIL::C195_W: + case AMDIL::C196_W: + case AMDIL::C197_W: + case AMDIL::C198_W: + case AMDIL::C199_W: + case AMDIL::C200_W: + case AMDIL::C201_W: + case AMDIL::C202_W: + case AMDIL::C203_W: + case AMDIL::C204_W: + case AMDIL::C205_W: + case AMDIL::C206_W: + case AMDIL::C207_W: + case AMDIL::C208_W: + case AMDIL::C209_W: + case AMDIL::C210_W: + case AMDIL::C211_W: + case AMDIL::C212_W: + case AMDIL::C213_W: + case AMDIL::C214_W: + case AMDIL::C215_W: + case AMDIL::C216_W: + case AMDIL::C217_W: + case AMDIL::C218_W: + case AMDIL::C219_W: + case AMDIL::C220_W: + case AMDIL::C221_W: + case AMDIL::C222_W: + case AMDIL::C223_W: + case AMDIL::C224_W: + case AMDIL::C225_W: + case AMDIL::C226_W: + case AMDIL::C227_W: + case AMDIL::C228_W: + case AMDIL::C229_W: + case AMDIL::C230_W: + case AMDIL::C231_W: + case AMDIL::C232_W: + case AMDIL::C233_W: + case AMDIL::C234_W: + case AMDIL::C235_W: + case AMDIL::C236_W: + case AMDIL::C237_W: + case AMDIL::C238_W: + case AMDIL::C239_W: + case AMDIL::C240_W: + case AMDIL::C241_W: + case AMDIL::C242_W: + case AMDIL::C243_W: + case AMDIL::C244_W: + case AMDIL::C245_W: + case AMDIL::C246_W: + case AMDIL::C247_W: + case AMDIL::C248_W: + case AMDIL::C249_W: + case AMDIL::C250_W: + case AMDIL::C251_W: + case AMDIL::C252_W: + case AMDIL::C253_W: + case AMDIL::C254_W: + case AMDIL::C255_W: + case AMDIL::T0_W: + case AMDIL::T1_W: + case AMDIL::T2_W: + case AMDIL::T3_W: + case AMDIL::T4_W: + case AMDIL::T5_W: + case AMDIL::T6_W: + case AMDIL::T7_W: + case AMDIL::T8_W: + case AMDIL::T9_W: + case AMDIL::T10_W: + case AMDIL::T11_W: + case AMDIL::T12_W: + case AMDIL::T13_W: + case AMDIL::T14_W: + case AMDIL::T15_W: + case AMDIL::T16_W: + case AMDIL::T17_W: + case AMDIL::T18_W: + case AMDIL::T19_W: + case AMDIL::T20_W: + case AMDIL::T21_W: + case AMDIL::T22_W: + case AMDIL::T23_W: + case AMDIL::T24_W: + case AMDIL::T25_W: + case AMDIL::T26_W: + case AMDIL::T27_W: + case AMDIL::T28_W: + case AMDIL::T29_W: + case AMDIL::T30_W: + case AMDIL::T31_W: + case AMDIL::T32_W: + case AMDIL::T33_W: + case AMDIL::T34_W: + case AMDIL::T35_W: + case AMDIL::T36_W: + case AMDIL::T37_W: + case AMDIL::T38_W: + case AMDIL::T39_W: + case AMDIL::T40_W: + case AMDIL::T41_W: + case AMDIL::T42_W: + case AMDIL::T43_W: + case AMDIL::T44_W: + case AMDIL::T45_W: + case AMDIL::T46_W: + case AMDIL::T47_W: + case AMDIL::T48_W: + case AMDIL::T49_W: + case AMDIL::T50_W: + case AMDIL::T51_W: + case AMDIL::T52_W: + case AMDIL::T53_W: + case AMDIL::T54_W: + case AMDIL::T55_W: + case AMDIL::T56_W: + case AMDIL::T57_W: + case AMDIL::T58_W: + case AMDIL::T59_W: + case AMDIL::T60_W: + case AMDIL::T61_W: + case AMDIL::T62_W: + case AMDIL::T63_W: + case AMDIL::T64_W: + case AMDIL::T65_W: + case AMDIL::T66_W: + case AMDIL::T67_W: + case AMDIL::T68_W: + case AMDIL::T69_W: + case AMDIL::T70_W: + case AMDIL::T71_W: + case AMDIL::T72_W: + case AMDIL::T73_W: + case AMDIL::T74_W: + case AMDIL::T75_W: + case AMDIL::T76_W: + case AMDIL::T77_W: + case AMDIL::T78_W: + case AMDIL::T79_W: + case AMDIL::T80_W: + case AMDIL::T81_W: + case AMDIL::T82_W: + case AMDIL::T83_W: + case AMDIL::T84_W: + case AMDIL::T85_W: + case AMDIL::T86_W: + case AMDIL::T87_W: + case AMDIL::T88_W: + case AMDIL::T89_W: + case AMDIL::T90_W: + case AMDIL::T91_W: + case AMDIL::T92_W: + case AMDIL::T93_W: + case AMDIL::T94_W: + case AMDIL::T95_W: + case AMDIL::T96_W: + case AMDIL::T97_W: + case AMDIL::T98_W: + case AMDIL::T99_W: + case AMDIL::T100_W: + case AMDIL::T101_W: + case AMDIL::T102_W: + case AMDIL::T103_W: + case AMDIL::T104_W: + case AMDIL::T105_W: + case AMDIL::T106_W: + case AMDIL::T107_W: + case AMDIL::T108_W: + case AMDIL::T109_W: + case AMDIL::T110_W: + case AMDIL::T111_W: + case AMDIL::T112_W: + case AMDIL::T113_W: + case AMDIL::T114_W: + case AMDIL::T115_W: + case AMDIL::T116_W: + case AMDIL::T117_W: + case AMDIL::T118_W: + case AMDIL::T119_W: + case AMDIL::T120_W: + case AMDIL::T121_W: + case AMDIL::T122_W: + case AMDIL::T123_W: + case AMDIL::T124_W: + case AMDIL::T125_W: + case AMDIL::T126_W: + case AMDIL::T127_W: + return 3; + + case AMDIL::C0_X: + case AMDIL::C1_X: + case AMDIL::C2_X: + case AMDIL::C3_X: + case AMDIL::C4_X: + case AMDIL::C5_X: + case AMDIL::C6_X: + case AMDIL::C7_X: + case AMDIL::C8_X: + case AMDIL::C9_X: + case AMDIL::C10_X: + case AMDIL::C11_X: + case AMDIL::C12_X: + case AMDIL::C13_X: + case AMDIL::C14_X: + case AMDIL::C15_X: + case AMDIL::C16_X: + case AMDIL::C17_X: + case AMDIL::C18_X: + case AMDIL::C19_X: + case AMDIL::C20_X: + case AMDIL::C21_X: + case AMDIL::C22_X: + case AMDIL::C23_X: + case AMDIL::C24_X: + case AMDIL::C25_X: + case AMDIL::C26_X: + case AMDIL::C27_X: + case AMDIL::C28_X: + case AMDIL::C29_X: + case AMDIL::C30_X: + case AMDIL::C31_X: + case AMDIL::C32_X: + case AMDIL::C33_X: + case AMDIL::C34_X: + case AMDIL::C35_X: + case AMDIL::C36_X: + case AMDIL::C37_X: + case AMDIL::C38_X: + case AMDIL::C39_X: + case AMDIL::C40_X: + case AMDIL::C41_X: + case AMDIL::C42_X: + case AMDIL::C43_X: + case AMDIL::C44_X: + case AMDIL::C45_X: + case AMDIL::C46_X: + case AMDIL::C47_X: + case AMDIL::C48_X: + case AMDIL::C49_X: + case AMDIL::C50_X: + case AMDIL::C51_X: + case AMDIL::C52_X: + case AMDIL::C53_X: + case AMDIL::C54_X: + case AMDIL::C55_X: + case AMDIL::C56_X: + case AMDIL::C57_X: + case AMDIL::C58_X: + case AMDIL::C59_X: + case AMDIL::C60_X: + case AMDIL::C61_X: + case AMDIL::C62_X: + case AMDIL::C63_X: + case AMDIL::C64_X: + case AMDIL::C65_X: + case AMDIL::C66_X: + case AMDIL::C67_X: + case AMDIL::C68_X: + case AMDIL::C69_X: + case AMDIL::C70_X: + case AMDIL::C71_X: + case AMDIL::C72_X: + case AMDIL::C73_X: + case AMDIL::C74_X: + case AMDIL::C75_X: + case AMDIL::C76_X: + case AMDIL::C77_X: + case AMDIL::C78_X: + case AMDIL::C79_X: + case AMDIL::C80_X: + case AMDIL::C81_X: + case AMDIL::C82_X: + case AMDIL::C83_X: + case AMDIL::C84_X: + case AMDIL::C85_X: + case AMDIL::C86_X: + case AMDIL::C87_X: + case AMDIL::C88_X: + case AMDIL::C89_X: + case AMDIL::C90_X: + case AMDIL::C91_X: + case AMDIL::C92_X: + case AMDIL::C93_X: + case AMDIL::C94_X: + case AMDIL::C95_X: + case AMDIL::C96_X: + case AMDIL::C97_X: + case AMDIL::C98_X: + case AMDIL::C99_X: + case AMDIL::C100_X: + case AMDIL::C101_X: + case AMDIL::C102_X: + case AMDIL::C103_X: + case AMDIL::C104_X: + case AMDIL::C105_X: + case AMDIL::C106_X: + case AMDIL::C107_X: + case AMDIL::C108_X: + case AMDIL::C109_X: + case AMDIL::C110_X: + case AMDIL::C111_X: + case AMDIL::C112_X: + case AMDIL::C113_X: + case AMDIL::C114_X: + case AMDIL::C115_X: + case AMDIL::C116_X: + case AMDIL::C117_X: + case AMDIL::C118_X: + case AMDIL::C119_X: + case AMDIL::C120_X: + case AMDIL::C121_X: + case AMDIL::C122_X: + case AMDIL::C123_X: + case AMDIL::C124_X: + case AMDIL::C125_X: + case AMDIL::C126_X: + case AMDIL::C127_X: + case AMDIL::C128_X: + case AMDIL::C129_X: + case AMDIL::C130_X: + case AMDIL::C131_X: + case AMDIL::C132_X: + case AMDIL::C133_X: + case AMDIL::C134_X: + case AMDIL::C135_X: + case AMDIL::C136_X: + case AMDIL::C137_X: + case AMDIL::C138_X: + case AMDIL::C139_X: + case AMDIL::C140_X: + case AMDIL::C141_X: + case AMDIL::C142_X: + case AMDIL::C143_X: + case AMDIL::C144_X: + case AMDIL::C145_X: + case AMDIL::C146_X: + case AMDIL::C147_X: + case AMDIL::C148_X: + case AMDIL::C149_X: + case AMDIL::C150_X: + case AMDIL::C151_X: + case AMDIL::C152_X: + case AMDIL::C153_X: + case AMDIL::C154_X: + case AMDIL::C155_X: + case AMDIL::C156_X: + case AMDIL::C157_X: + case AMDIL::C158_X: + case AMDIL::C159_X: + case AMDIL::C160_X: + case AMDIL::C161_X: + case AMDIL::C162_X: + case AMDIL::C163_X: + case AMDIL::C164_X: + case AMDIL::C165_X: + case AMDIL::C166_X: + case AMDIL::C167_X: + case AMDIL::C168_X: + case AMDIL::C169_X: + case AMDIL::C170_X: + case AMDIL::C171_X: + case AMDIL::C172_X: + case AMDIL::C173_X: + case AMDIL::C174_X: + case AMDIL::C175_X: + case AMDIL::C176_X: + case AMDIL::C177_X: + case AMDIL::C178_X: + case AMDIL::C179_X: + case AMDIL::C180_X: + case AMDIL::C181_X: + case AMDIL::C182_X: + case AMDIL::C183_X: + case AMDIL::C184_X: + case AMDIL::C185_X: + case AMDIL::C186_X: + case AMDIL::C187_X: + case AMDIL::C188_X: + case AMDIL::C189_X: + case AMDIL::C190_X: + case AMDIL::C191_X: + case AMDIL::C192_X: + case AMDIL::C193_X: + case AMDIL::C194_X: + case AMDIL::C195_X: + case AMDIL::C196_X: + case AMDIL::C197_X: + case AMDIL::C198_X: + case AMDIL::C199_X: + case AMDIL::C200_X: + case AMDIL::C201_X: + case AMDIL::C202_X: + case AMDIL::C203_X: + case AMDIL::C204_X: + case AMDIL::C205_X: + case AMDIL::C206_X: + case AMDIL::C207_X: + case AMDIL::C208_X: + case AMDIL::C209_X: + case AMDIL::C210_X: + case AMDIL::C211_X: + case AMDIL::C212_X: + case AMDIL::C213_X: + case AMDIL::C214_X: + case AMDIL::C215_X: + case AMDIL::C216_X: + case AMDIL::C217_X: + case AMDIL::C218_X: + case AMDIL::C219_X: + case AMDIL::C220_X: + case AMDIL::C221_X: + case AMDIL::C222_X: + case AMDIL::C223_X: + case AMDIL::C224_X: + case AMDIL::C225_X: + case AMDIL::C226_X: + case AMDIL::C227_X: + case AMDIL::C228_X: + case AMDIL::C229_X: + case AMDIL::C230_X: + case AMDIL::C231_X: + case AMDIL::C232_X: + case AMDIL::C233_X: + case AMDIL::C234_X: + case AMDIL::C235_X: + case AMDIL::C236_X: + case AMDIL::C237_X: + case AMDIL::C238_X: + case AMDIL::C239_X: + case AMDIL::C240_X: + case AMDIL::C241_X: + case AMDIL::C242_X: + case AMDIL::C243_X: + case AMDIL::C244_X: + case AMDIL::C245_X: + case AMDIL::C246_X: + case AMDIL::C247_X: + case AMDIL::C248_X: + case AMDIL::C249_X: + case AMDIL::C250_X: + case AMDIL::C251_X: + case AMDIL::C252_X: + case AMDIL::C253_X: + case AMDIL::C254_X: + case AMDIL::C255_X: + case AMDIL::T0_X: + case AMDIL::T1_X: + case AMDIL::T2_X: + case AMDIL::T3_X: + case AMDIL::T4_X: + case AMDIL::T5_X: + case AMDIL::T6_X: + case AMDIL::T7_X: + case AMDIL::T8_X: + case AMDIL::T9_X: + case AMDIL::T10_X: + case AMDIL::T11_X: + case AMDIL::T12_X: + case AMDIL::T13_X: + case AMDIL::T14_X: + case AMDIL::T15_X: + case AMDIL::T16_X: + case AMDIL::T17_X: + case AMDIL::T18_X: + case AMDIL::T19_X: + case AMDIL::T20_X: + case AMDIL::T21_X: + case AMDIL::T22_X: + case AMDIL::T23_X: + case AMDIL::T24_X: + case AMDIL::T25_X: + case AMDIL::T26_X: + case AMDIL::T27_X: + case AMDIL::T28_X: + case AMDIL::T29_X: + case AMDIL::T30_X: + case AMDIL::T31_X: + case AMDIL::T32_X: + case AMDIL::T33_X: + case AMDIL::T34_X: + case AMDIL::T35_X: + case AMDIL::T36_X: + case AMDIL::T37_X: + case AMDIL::T38_X: + case AMDIL::T39_X: + case AMDIL::T40_X: + case AMDIL::T41_X: + case AMDIL::T42_X: + case AMDIL::T43_X: + case AMDIL::T44_X: + case AMDIL::T45_X: + case AMDIL::T46_X: + case AMDIL::T47_X: + case AMDIL::T48_X: + case AMDIL::T49_X: + case AMDIL::T50_X: + case AMDIL::T51_X: + case AMDIL::T52_X: + case AMDIL::T53_X: + case AMDIL::T54_X: + case AMDIL::T55_X: + case AMDIL::T56_X: + case AMDIL::T57_X: + case AMDIL::T58_X: + case AMDIL::T59_X: + case AMDIL::T60_X: + case AMDIL::T61_X: + case AMDIL::T62_X: + case AMDIL::T63_X: + case AMDIL::T64_X: + case AMDIL::T65_X: + case AMDIL::T66_X: + case AMDIL::T67_X: + case AMDIL::T68_X: + case AMDIL::T69_X: + case AMDIL::T70_X: + case AMDIL::T71_X: + case AMDIL::T72_X: + case AMDIL::T73_X: + case AMDIL::T74_X: + case AMDIL::T75_X: + case AMDIL::T76_X: + case AMDIL::T77_X: + case AMDIL::T78_X: + case AMDIL::T79_X: + case AMDIL::T80_X: + case AMDIL::T81_X: + case AMDIL::T82_X: + case AMDIL::T83_X: + case AMDIL::T84_X: + case AMDIL::T85_X: + case AMDIL::T86_X: + case AMDIL::T87_X: + case AMDIL::T88_X: + case AMDIL::T89_X: + case AMDIL::T90_X: + case AMDIL::T91_X: + case AMDIL::T92_X: + case AMDIL::T93_X: + case AMDIL::T94_X: + case AMDIL::T95_X: + case AMDIL::T96_X: + case AMDIL::T97_X: + case AMDIL::T98_X: + case AMDIL::T99_X: + case AMDIL::T100_X: + case AMDIL::T101_X: + case AMDIL::T102_X: + case AMDIL::T103_X: + case AMDIL::T104_X: + case AMDIL::T105_X: + case AMDIL::T106_X: + case AMDIL::T107_X: + case AMDIL::T108_X: + case AMDIL::T109_X: + case AMDIL::T110_X: + case AMDIL::T111_X: + case AMDIL::T112_X: + case AMDIL::T113_X: + case AMDIL::T114_X: + case AMDIL::T115_X: + case AMDIL::T116_X: + case AMDIL::T117_X: + case AMDIL::T118_X: + case AMDIL::T119_X: + case AMDIL::T120_X: + case AMDIL::T121_X: + case AMDIL::T122_X: + case AMDIL::T123_X: + case AMDIL::T124_X: + case AMDIL::T125_X: + case AMDIL::T126_X: + case AMDIL::T127_X: + case AMDIL::T0_XYZW: + case AMDIL::T1_XYZW: + case AMDIL::T2_XYZW: + case AMDIL::T3_XYZW: + case AMDIL::T4_XYZW: + case AMDIL::T5_XYZW: + case AMDIL::T6_XYZW: + case AMDIL::T7_XYZW: + case AMDIL::T8_XYZW: + case AMDIL::T9_XYZW: + case AMDIL::T10_XYZW: + case AMDIL::T11_XYZW: + case AMDIL::T12_XYZW: + case AMDIL::T13_XYZW: + case AMDIL::T14_XYZW: + case AMDIL::T15_XYZW: + case AMDIL::T16_XYZW: + case AMDIL::T17_XYZW: + case AMDIL::T18_XYZW: + case AMDIL::T19_XYZW: + case AMDIL::T20_XYZW: + case AMDIL::T21_XYZW: + case AMDIL::T22_XYZW: + case AMDIL::T23_XYZW: + case AMDIL::T24_XYZW: + case AMDIL::T25_XYZW: + case AMDIL::T26_XYZW: + case AMDIL::T27_XYZW: + case AMDIL::T28_XYZW: + case AMDIL::T29_XYZW: + case AMDIL::T30_XYZW: + case AMDIL::T31_XYZW: + case AMDIL::T32_XYZW: + case AMDIL::T33_XYZW: + case AMDIL::T34_XYZW: + case AMDIL::T35_XYZW: + case AMDIL::T36_XYZW: + case AMDIL::T37_XYZW: + case AMDIL::T38_XYZW: + case AMDIL::T39_XYZW: + case AMDIL::T40_XYZW: + case AMDIL::T41_XYZW: + case AMDIL::T42_XYZW: + case AMDIL::T43_XYZW: + case AMDIL::T44_XYZW: + case AMDIL::T45_XYZW: + case AMDIL::T46_XYZW: + case AMDIL::T47_XYZW: + case AMDIL::T48_XYZW: + case AMDIL::T49_XYZW: + case AMDIL::T50_XYZW: + case AMDIL::T51_XYZW: + case AMDIL::T52_XYZW: + case AMDIL::T53_XYZW: + case AMDIL::T54_XYZW: + case AMDIL::T55_XYZW: + case AMDIL::T56_XYZW: + case AMDIL::T57_XYZW: + case AMDIL::T58_XYZW: + case AMDIL::T59_XYZW: + case AMDIL::T60_XYZW: + case AMDIL::T61_XYZW: + case AMDIL::T62_XYZW: + case AMDIL::T63_XYZW: + case AMDIL::T64_XYZW: + case AMDIL::T65_XYZW: + case AMDIL::T66_XYZW: + case AMDIL::T67_XYZW: + case AMDIL::T68_XYZW: + case AMDIL::T69_XYZW: + case AMDIL::T70_XYZW: + case AMDIL::T71_XYZW: + case AMDIL::T72_XYZW: + case AMDIL::T73_XYZW: + case AMDIL::T74_XYZW: + case AMDIL::T75_XYZW: + case AMDIL::T76_XYZW: + case AMDIL::T77_XYZW: + case AMDIL::T78_XYZW: + case AMDIL::T79_XYZW: + case AMDIL::T80_XYZW: + case AMDIL::T81_XYZW: + case AMDIL::T82_XYZW: + case AMDIL::T83_XYZW: + case AMDIL::T84_XYZW: + case AMDIL::T85_XYZW: + case AMDIL::T86_XYZW: + case AMDIL::T87_XYZW: + case AMDIL::T88_XYZW: + case AMDIL::T89_XYZW: + case AMDIL::T90_XYZW: + case AMDIL::T91_XYZW: + case AMDIL::T92_XYZW: + case AMDIL::T93_XYZW: + case AMDIL::T94_XYZW: + case AMDIL::T95_XYZW: + case AMDIL::T96_XYZW: + case AMDIL::T97_XYZW: + case AMDIL::T98_XYZW: + case AMDIL::T99_XYZW: + case AMDIL::T100_XYZW: + case AMDIL::T101_XYZW: + case AMDIL::T102_XYZW: + case AMDIL::T103_XYZW: + case AMDIL::T104_XYZW: + case AMDIL::T105_XYZW: + case AMDIL::T106_XYZW: + case AMDIL::T107_XYZW: + case AMDIL::T108_XYZW: + case AMDIL::T109_XYZW: + case AMDIL::T110_XYZW: + case AMDIL::T111_XYZW: + case AMDIL::T112_XYZW: + case AMDIL::T113_XYZW: + case AMDIL::T114_XYZW: + case AMDIL::T115_XYZW: + case AMDIL::T116_XYZW: + case AMDIL::T117_XYZW: + case AMDIL::T118_XYZW: + case AMDIL::T119_XYZW: + case AMDIL::T120_XYZW: + case AMDIL::T121_XYZW: + case AMDIL::T122_XYZW: + case AMDIL::T123_XYZW: + case AMDIL::T124_XYZW: + case AMDIL::T125_XYZW: + case AMDIL::T126_XYZW: + case AMDIL::T127_XYZW: + return 0; + + case AMDIL::C0_Y: + case AMDIL::C1_Y: + case AMDIL::C2_Y: + case AMDIL::C3_Y: + case AMDIL::C4_Y: + case AMDIL::C5_Y: + case AMDIL::C6_Y: + case AMDIL::C7_Y: + case AMDIL::C8_Y: + case AMDIL::C9_Y: + case AMDIL::C10_Y: + case AMDIL::C11_Y: + case AMDIL::C12_Y: + case AMDIL::C13_Y: + case AMDIL::C14_Y: + case AMDIL::C15_Y: + case AMDIL::C16_Y: + case AMDIL::C17_Y: + case AMDIL::C18_Y: + case AMDIL::C19_Y: + case AMDIL::C20_Y: + case AMDIL::C21_Y: + case AMDIL::C22_Y: + case AMDIL::C23_Y: + case AMDIL::C24_Y: + case AMDIL::C25_Y: + case AMDIL::C26_Y: + case AMDIL::C27_Y: + case AMDIL::C28_Y: + case AMDIL::C29_Y: + case AMDIL::C30_Y: + case AMDIL::C31_Y: + case AMDIL::C32_Y: + case AMDIL::C33_Y: + case AMDIL::C34_Y: + case AMDIL::C35_Y: + case AMDIL::C36_Y: + case AMDIL::C37_Y: + case AMDIL::C38_Y: + case AMDIL::C39_Y: + case AMDIL::C40_Y: + case AMDIL::C41_Y: + case AMDIL::C42_Y: + case AMDIL::C43_Y: + case AMDIL::C44_Y: + case AMDIL::C45_Y: + case AMDIL::C46_Y: + case AMDIL::C47_Y: + case AMDIL::C48_Y: + case AMDIL::C49_Y: + case AMDIL::C50_Y: + case AMDIL::C51_Y: + case AMDIL::C52_Y: + case AMDIL::C53_Y: + case AMDIL::C54_Y: + case AMDIL::C55_Y: + case AMDIL::C56_Y: + case AMDIL::C57_Y: + case AMDIL::C58_Y: + case AMDIL::C59_Y: + case AMDIL::C60_Y: + case AMDIL::C61_Y: + case AMDIL::C62_Y: + case AMDIL::C63_Y: + case AMDIL::C64_Y: + case AMDIL::C65_Y: + case AMDIL::C66_Y: + case AMDIL::C67_Y: + case AMDIL::C68_Y: + case AMDIL::C69_Y: + case AMDIL::C70_Y: + case AMDIL::C71_Y: + case AMDIL::C72_Y: + case AMDIL::C73_Y: + case AMDIL::C74_Y: + case AMDIL::C75_Y: + case AMDIL::C76_Y: + case AMDIL::C77_Y: + case AMDIL::C78_Y: + case AMDIL::C79_Y: + case AMDIL::C80_Y: + case AMDIL::C81_Y: + case AMDIL::C82_Y: + case AMDIL::C83_Y: + case AMDIL::C84_Y: + case AMDIL::C85_Y: + case AMDIL::C86_Y: + case AMDIL::C87_Y: + case AMDIL::C88_Y: + case AMDIL::C89_Y: + case AMDIL::C90_Y: + case AMDIL::C91_Y: + case AMDIL::C92_Y: + case AMDIL::C93_Y: + case AMDIL::C94_Y: + case AMDIL::C95_Y: + case AMDIL::C96_Y: + case AMDIL::C97_Y: + case AMDIL::C98_Y: + case AMDIL::C99_Y: + case AMDIL::C100_Y: + case AMDIL::C101_Y: + case AMDIL::C102_Y: + case AMDIL::C103_Y: + case AMDIL::C104_Y: + case AMDIL::C105_Y: + case AMDIL::C106_Y: + case AMDIL::C107_Y: + case AMDIL::C108_Y: + case AMDIL::C109_Y: + case AMDIL::C110_Y: + case AMDIL::C111_Y: + case AMDIL::C112_Y: + case AMDIL::C113_Y: + case AMDIL::C114_Y: + case AMDIL::C115_Y: + case AMDIL::C116_Y: + case AMDIL::C117_Y: + case AMDIL::C118_Y: + case AMDIL::C119_Y: + case AMDIL::C120_Y: + case AMDIL::C121_Y: + case AMDIL::C122_Y: + case AMDIL::C123_Y: + case AMDIL::C124_Y: + case AMDIL::C125_Y: + case AMDIL::C126_Y: + case AMDIL::C127_Y: + case AMDIL::C128_Y: + case AMDIL::C129_Y: + case AMDIL::C130_Y: + case AMDIL::C131_Y: + case AMDIL::C132_Y: + case AMDIL::C133_Y: + case AMDIL::C134_Y: + case AMDIL::C135_Y: + case AMDIL::C136_Y: + case AMDIL::C137_Y: + case AMDIL::C138_Y: + case AMDIL::C139_Y: + case AMDIL::C140_Y: + case AMDIL::C141_Y: + case AMDIL::C142_Y: + case AMDIL::C143_Y: + case AMDIL::C144_Y: + case AMDIL::C145_Y: + case AMDIL::C146_Y: + case AMDIL::C147_Y: + case AMDIL::C148_Y: + case AMDIL::C149_Y: + case AMDIL::C150_Y: + case AMDIL::C151_Y: + case AMDIL::C152_Y: + case AMDIL::C153_Y: + case AMDIL::C154_Y: + case AMDIL::C155_Y: + case AMDIL::C156_Y: + case AMDIL::C157_Y: + case AMDIL::C158_Y: + case AMDIL::C159_Y: + case AMDIL::C160_Y: + case AMDIL::C161_Y: + case AMDIL::C162_Y: + case AMDIL::C163_Y: + case AMDIL::C164_Y: + case AMDIL::C165_Y: + case AMDIL::C166_Y: + case AMDIL::C167_Y: + case AMDIL::C168_Y: + case AMDIL::C169_Y: + case AMDIL::C170_Y: + case AMDIL::C171_Y: + case AMDIL::C172_Y: + case AMDIL::C173_Y: + case AMDIL::C174_Y: + case AMDIL::C175_Y: + case AMDIL::C176_Y: + case AMDIL::C177_Y: + case AMDIL::C178_Y: + case AMDIL::C179_Y: + case AMDIL::C180_Y: + case AMDIL::C181_Y: + case AMDIL::C182_Y: + case AMDIL::C183_Y: + case AMDIL::C184_Y: + case AMDIL::C185_Y: + case AMDIL::C186_Y: + case AMDIL::C187_Y: + case AMDIL::C188_Y: + case AMDIL::C189_Y: + case AMDIL::C190_Y: + case AMDIL::C191_Y: + case AMDIL::C192_Y: + case AMDIL::C193_Y: + case AMDIL::C194_Y: + case AMDIL::C195_Y: + case AMDIL::C196_Y: + case AMDIL::C197_Y: + case AMDIL::C198_Y: + case AMDIL::C199_Y: + case AMDIL::C200_Y: + case AMDIL::C201_Y: + case AMDIL::C202_Y: + case AMDIL::C203_Y: + case AMDIL::C204_Y: + case AMDIL::C205_Y: + case AMDIL::C206_Y: + case AMDIL::C207_Y: + case AMDIL::C208_Y: + case AMDIL::C209_Y: + case AMDIL::C210_Y: + case AMDIL::C211_Y: + case AMDIL::C212_Y: + case AMDIL::C213_Y: + case AMDIL::C214_Y: + case AMDIL::C215_Y: + case AMDIL::C216_Y: + case AMDIL::C217_Y: + case AMDIL::C218_Y: + case AMDIL::C219_Y: + case AMDIL::C220_Y: + case AMDIL::C221_Y: + case AMDIL::C222_Y: + case AMDIL::C223_Y: + case AMDIL::C224_Y: + case AMDIL::C225_Y: + case AMDIL::C226_Y: + case AMDIL::C227_Y: + case AMDIL::C228_Y: + case AMDIL::C229_Y: + case AMDIL::C230_Y: + case AMDIL::C231_Y: + case AMDIL::C232_Y: + case AMDIL::C233_Y: + case AMDIL::C234_Y: + case AMDIL::C235_Y: + case AMDIL::C236_Y: + case AMDIL::C237_Y: + case AMDIL::C238_Y: + case AMDIL::C239_Y: + case AMDIL::C240_Y: + case AMDIL::C241_Y: + case AMDIL::C242_Y: + case AMDIL::C243_Y: + case AMDIL::C244_Y: + case AMDIL::C245_Y: + case AMDIL::C246_Y: + case AMDIL::C247_Y: + case AMDIL::C248_Y: + case AMDIL::C249_Y: + case AMDIL::C250_Y: + case AMDIL::C251_Y: + case AMDIL::C252_Y: + case AMDIL::C253_Y: + case AMDIL::C254_Y: + case AMDIL::C255_Y: + case AMDIL::T0_Y: + case AMDIL::T1_Y: + case AMDIL::T2_Y: + case AMDIL::T3_Y: + case AMDIL::T4_Y: + case AMDIL::T5_Y: + case AMDIL::T6_Y: + case AMDIL::T7_Y: + case AMDIL::T8_Y: + case AMDIL::T9_Y: + case AMDIL::T10_Y: + case AMDIL::T11_Y: + case AMDIL::T12_Y: + case AMDIL::T13_Y: + case AMDIL::T14_Y: + case AMDIL::T15_Y: + case AMDIL::T16_Y: + case AMDIL::T17_Y: + case AMDIL::T18_Y: + case AMDIL::T19_Y: + case AMDIL::T20_Y: + case AMDIL::T21_Y: + case AMDIL::T22_Y: + case AMDIL::T23_Y: + case AMDIL::T24_Y: + case AMDIL::T25_Y: + case AMDIL::T26_Y: + case AMDIL::T27_Y: + case AMDIL::T28_Y: + case AMDIL::T29_Y: + case AMDIL::T30_Y: + case AMDIL::T31_Y: + case AMDIL::T32_Y: + case AMDIL::T33_Y: + case AMDIL::T34_Y: + case AMDIL::T35_Y: + case AMDIL::T36_Y: + case AMDIL::T37_Y: + case AMDIL::T38_Y: + case AMDIL::T39_Y: + case AMDIL::T40_Y: + case AMDIL::T41_Y: + case AMDIL::T42_Y: + case AMDIL::T43_Y: + case AMDIL::T44_Y: + case AMDIL::T45_Y: + case AMDIL::T46_Y: + case AMDIL::T47_Y: + case AMDIL::T48_Y: + case AMDIL::T49_Y: + case AMDIL::T50_Y: + case AMDIL::T51_Y: + case AMDIL::T52_Y: + case AMDIL::T53_Y: + case AMDIL::T54_Y: + case AMDIL::T55_Y: + case AMDIL::T56_Y: + case AMDIL::T57_Y: + case AMDIL::T58_Y: + case AMDIL::T59_Y: + case AMDIL::T60_Y: + case AMDIL::T61_Y: + case AMDIL::T62_Y: + case AMDIL::T63_Y: + case AMDIL::T64_Y: + case AMDIL::T65_Y: + case AMDIL::T66_Y: + case AMDIL::T67_Y: + case AMDIL::T68_Y: + case AMDIL::T69_Y: + case AMDIL::T70_Y: + case AMDIL::T71_Y: + case AMDIL::T72_Y: + case AMDIL::T73_Y: + case AMDIL::T74_Y: + case AMDIL::T75_Y: + case AMDIL::T76_Y: + case AMDIL::T77_Y: + case AMDIL::T78_Y: + case AMDIL::T79_Y: + case AMDIL::T80_Y: + case AMDIL::T81_Y: + case AMDIL::T82_Y: + case AMDIL::T83_Y: + case AMDIL::T84_Y: + case AMDIL::T85_Y: + case AMDIL::T86_Y: + case AMDIL::T87_Y: + case AMDIL::T88_Y: + case AMDIL::T89_Y: + case AMDIL::T90_Y: + case AMDIL::T91_Y: + case AMDIL::T92_Y: + case AMDIL::T93_Y: + case AMDIL::T94_Y: + case AMDIL::T95_Y: + case AMDIL::T96_Y: + case AMDIL::T97_Y: + case AMDIL::T98_Y: + case AMDIL::T99_Y: + case AMDIL::T100_Y: + case AMDIL::T101_Y: + case AMDIL::T102_Y: + case AMDIL::T103_Y: + case AMDIL::T104_Y: + case AMDIL::T105_Y: + case AMDIL::T106_Y: + case AMDIL::T107_Y: + case AMDIL::T108_Y: + case AMDIL::T109_Y: + case AMDIL::T110_Y: + case AMDIL::T111_Y: + case AMDIL::T112_Y: + case AMDIL::T113_Y: + case AMDIL::T114_Y: + case AMDIL::T115_Y: + case AMDIL::T116_Y: + case AMDIL::T117_Y: + case AMDIL::T118_Y: + case AMDIL::T119_Y: + case AMDIL::T120_Y: + case AMDIL::T121_Y: + case AMDIL::T122_Y: + case AMDIL::T123_Y: + case AMDIL::T124_Y: + case AMDIL::T125_Y: + case AMDIL::T126_Y: + case AMDIL::T127_Y: + return 1; + + } +} + diff --git a/lib/Target/AMDIL/R600Instructions.td b/lib/Target/AMDIL/R600Instructions.td new file mode 100644 index 00000000000..9b59171de43 --- /dev/null +++ b/lib/Target/AMDIL/R600Instructions.td @@ -0,0 +1,1050 @@ +//===-- R600Instructions.td - R600 Instruction defs -------*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// R600 Tablegen instruction definitions +// +//===----------------------------------------------------------------------===// + +include "R600Intrinsics.td" + +class InstR600 inst, dag outs, dag ins, string asm, list pattern, + InstrItinClass itin> + : AMDGPUInst { + + field bits<32> Inst; + bit Trig = 0; + bit Op3 = 0; + + let Inst = inst; + let Namespace = "AMDIL"; + let OutOperandList = outs; + let InOperandList = ins; + let AsmString = asm; + let Pattern = pattern; + let Itinerary = itin; + + let TSFlags{4} = Trig; + let TSFlags{5} = Op3; +} + +class InstR600ISA pattern> : + AMDGPUInst +{ + field bits<64> Inst; + + let Namespace = "AMDIL"; +} + +def MEMri : Operand { + let MIOperandInfo = (ops R600_Reg32:$ptr, R600_Reg32:$index); +} + +def ADDRParam : ComplexPattern; + +class R600_ALU { + + bits<7> DST_GPR = 0; + bits<9> SRC0_SEL = 0; + bits<1> SRC0_NEG = 0; + bits<9> SRC1_SEL = 0; + bits<1> SRC1_NEG = 0; + bits<1> CLAMP = 0; + +} + + +class R600_1OP inst, string opName, list pattern, + InstrItinClass itin = AnyALU> : + InstR600 ; + +class R600_2OP inst, string opName, list pattern, + InstrItinClass itin = AnyALU> : + InstR600 ; + +class R600_3OP inst, string opName, list pattern, + InstrItinClass itin = AnyALU> : + InstR600 { + + let Op3 = 1; + } + +class R600_REDUCTION inst, dag ins, string asm, list pattern, + InstrItinClass itin = VecALU> : + InstR600 ; + +class R600_TEX inst, string opName, list pattern, + InstrItinClass itin = AnyALU> : + InstR600 ; + +def TEX_SHADOW : PatLeaf< + (imm), + [{uint32_t TType = (uint32_t)N->getZExtValue(); + return (TType >= 6 && TType <= 8) || TType == 11 || TType == 12; + }] +>; + +class EG_CF_RAT cf_inst, bits <6> rat_inst, dag outs, dag ins, + string asm> : + InstR600ISA +{ + bits<7> RW_GPR; + bits<7> INDEX_GPR; + bits<4> RAT_ID; + + bits<2> RIM; + bits<2> TYPE; + bits<1> RW_REL; + bits<2> ELEM_SIZE; + + bits<12> ARRAY_SIZE; + bits<4> COMP_MASK; + bits<4> BURST_COUNT; + bits<1> VPM; + bits<1> EOP; + bits<1> MARK; + bits<1> BARRIER; + + /* CF_ALLOC_EXPORT_WORD0_RAT */ + let Inst{3-0} = RAT_ID; + let Inst{9-4} = rat_inst; + let Inst{10} = 0; /* Reserved */ + let Inst{12-11} = RIM; + let Inst{14-13} = TYPE; + let Inst{21-15} = RW_GPR; + let Inst{22} = RW_REL; + let Inst{29-23} = INDEX_GPR; + let Inst{31-30} = ELEM_SIZE; + + /* CF_ALLOC_EXPORT_WORD1_BUF */ + let Inst{43-32} = ARRAY_SIZE; + let Inst{47-44} = COMP_MASK; + let Inst{51-48} = BURST_COUNT; + let Inst{52} = VPM; + let Inst{53} = EOP; + let Inst{61-54} = cf_inst; + let Inst{62} = MARK; + let Inst{63} = BARRIER; +} + +/* +def store_global : PatFrag<(ops node:$value, node:$ptr), + (store node:$value, node:$ptr), + [{ + const Value *Src; + const PointerType *Type; + if ((src = cast(N)->getSrcValue() && + PT = dyn_cast(Src->getType()))) { + return PT->getAddressSpace() == 1; + } + return false; + }]>; + +*/ + +def load_param : PatFrag<(ops node:$ptr), + (load node:$ptr), + [{ + return true; + const Value *Src = cast(N)->getSrcValue(); + if (Src) { + PointerType * PT = dyn_cast(Src->getType()); + return PT && PT->getAddressSpace() == AMDILAS::PARAM_I_ADDRESS; + } + return false; + }]>; + +//class EG_CF inst, string asm> : +// InstR600 ; + +/* XXX: We will use this when we emit the real ISA. + bits<24> ADDR = 0; + bits<3> JTS = 0; + + bits<3> PC = 0; + bits<5> CF_CONS = 0; + bits<2> COND = 0; + bits<6> COUNT = 0; + bits<1> VPM = 0; + bits<1> EOP = 0; + bits<8> CF_INST = 0; + bits<1> WQM = 0; + bits<1> B = 0; + + let Inst{23-0} = ADDR; + let Inst{26-24} = JTS; + let Inst{34-32} = PC; + let Inst{39-35} = CF_CONST; + let Inst{41-40} = COND; + let Inst{47-42} = COUNT; + let Inst{52} = VPM; + let Inst{53} = EOP; + let Inst{61-54} = CF_INST; + let Inst{62} = WQM; + let Inst{63} = B; +//} +*/ +def isR600 : Predicate<"Subtarget.device()" + "->getGeneration() == AMDILDeviceInfo::HD4XXX">; +def isEG : Predicate<"Subtarget.device()" + "->getGeneration() >= AMDILDeviceInfo::HD5XXX && " + "Subtarget.device()->getDeviceFlag() != OCL_DEVICE_CAYMAN">; +def isCayman : Predicate<"Subtarget.device()" + "->getDeviceFlag() == OCL_DEVICE_CAYMAN">; +def isEGorCayman : Predicate<"Subtarget.device()" + "->getGeneration() == AMDILDeviceInfo::HD5XXX" + "|| Subtarget.device()->getGeneration() ==" + "AMDILDeviceInfo::HD6XXX">; + +def isR600toCayman : Predicate< + "Subtarget.device()->getGeneration() <= AMDILDeviceInfo::HD6XXX">; + + +let Predicates = [isR600toCayman] in { + +/* ------------------------------------------- */ +/* Common Instructions R600, R700, Evergreen, Cayman */ +/* ------------------------------------------- */ +let Gen = AMDGPUGen.R600_CAYMAN in { + +def ADD : R600_2OP < + 0x0, "ADD", + [(set R600_Reg32:$dst, (fadd R600_Reg32:$src0, R600_Reg32:$src1))] > { + let AMDILOp = AMDILInst.ADD_f32; +} +// Non-IEEE MUL: 0 * anything = 0 +def MUL : R600_2OP < + 0x1, "MUL NON-IEEE", + [(set R600_Reg32:$dst, (int_AMDGPU_mul R600_Reg32:$src0, R600_Reg32:$src1))] +>; + +def MUL_IEEE : R600_2OP < + 0x2, "MUL_IEEE", + [(set R600_Reg32:$dst, (fmul R600_Reg32:$src0, R600_Reg32:$src1))]> { + let AMDILOp = AMDILInst.MUL_IEEE_f32; +} + +def MAX : R600_2OP < + 0x3, "MAX", + [(set R600_Reg32:$dst, (int_AMDIL_max R600_Reg32:$src0, R600_Reg32:$src1))]> { + let AMDILOp = AMDILInst.MAX_f32; +} + +def MIN : R600_2OP < + 0x4, "MIN", + [(set R600_Reg32:$dst, (int_AMDIL_min R600_Reg32:$src0, R600_Reg32:$src1))]> { + let AMDILOp = AMDILInst.MIN_f32; +} + +/* For the SET* instructions there is a naming conflict in TargetSelectionDAG.td, + * so some of the instruction names don't match the asm string. + * XXX: Use the defs in TargetSelectionDAG.td instead of intrinsics. + */ + +def SETE : R600_2OP < + 0x08, "SETE", + [(set R600_Reg32:$dst, (int_AMDGPU_seq R600_Reg32:$src0, R600_Reg32:$src1))]> { + let AMDILOp = AMDILInst.FEQ; +} + +def SGT : R600_2OP < + 0x09, "SETGT", + [(set R600_Reg32:$dst, (int_AMDGPU_sgt R600_Reg32:$src0, R600_Reg32:$src1))] +>; + +def SGE : R600_2OP < + 0xA, "SETGE", + [(set R600_Reg32:$dst, (int_AMDGPU_sge R600_Reg32:$src0, R600_Reg32:$src1))]> { + let AMDILOp = AMDILInst.FGE; +} + +def SNE : R600_2OP < + 0xB, "SETNE", + [(set R600_Reg32:$dst, (int_AMDGPU_sne R600_Reg32:$src0, R600_Reg32:$src1))]> { + let AMDILOp = AMDILInst.FNE; +} + +def FRACT : R600_1OP < + 0x10, "FRACT", + []> { + let AMDILOp = AMDILInst.FRAC_f32; +} + +def TRUNC : R600_1OP < + 0x11, "TRUNC", + [(set R600_Reg32:$dst, (int_AMDGPU_trunc R600_Reg32:$src))] +>; + +def CEIL : R600_1OP < + 0x12, "CEIL", + [(set R600_Reg32:$dst, (int_AMDIL_round_neginf R600_Reg32:$src))]> { + let AMDILOp = AMDILInst.ROUND_NEGINF_f32; +} + +def RNDNE : R600_1OP < + 0x13, "RNDNE", + [(set R600_Reg32:$dst, (int_AMDIL_round_nearest R600_Reg32:$src))]> { + let AMDILOp = AMDILInst.ROUND_NEAREST_f32; +} + +def FLOOR : R600_1OP < + 0x14, "FLOOR", + [(set R600_Reg32:$dst, (int_AMDGPU_floor R600_Reg32:$src))] +>; + +def MOV : R600_1OP <0x19, "MOV", []>; + +def KILLGT : R600_2OP < + 0x2D, "KILLGT", + [] +>; + +def AND_INT : R600_2OP < + 0x30, "AND_INT", + []> { + let AMDILOp = AMDILInst.AND_i32; +} + +def OR_INT : R600_2OP < + 0x31, "OR_INT", + []>{ + let AMDILOp = AMDILInst.BINARY_OR_i32; +} + +def XOR_INT : R600_2OP < + 0x32, "XOR_INT", + [] +>; + +def NOT_INT : R600_1OP < + 0x33, "NOT_INT", + []>{ + let AMDILOp = AMDILInst.BINARY_NOT_i32; +} + +def ADD_INT : R600_2OP < + 0x34, "ADD_INT", + []>{ + let AMDILOp = AMDILInst.ADD_i32; +} + +def SUB_INT : R600_2OP < + 0x35, "SUB_INT", + [] +>; + +def MAX_INT : R600_2OP < + 0x36, "MAX_INT", + [(set R600_Reg32:$dst, (int_AMDGPU_imax R600_Reg32:$src0, R600_Reg32:$src1))]>; + +def MIN_INT : R600_2OP < + 0x37, "MIN_INT", + [(set R600_Reg32:$dst, (int_AMDGPU_imin R600_Reg32:$src0, R600_Reg32:$src1))]>; + +def MAX_UINT : R600_2OP < + 0x38, "MAX_UINT", + [(set R600_Reg32:$dst, (int_AMDGPU_umax R600_Reg32:$src0, R600_Reg32:$src1))]>; + +def MIN_UINT : R600_2OP < + 0x39, "MIN_UINT", + [(set R600_Reg32:$dst, (int_AMDGPU_umin R600_Reg32:$src0, R600_Reg32:$src1))]>; + + +def SETE_INT : R600_2OP < + 0x3A, "SETE_INT", + []>{ + let AMDILOp = AMDILInst.IEQ; +} + +def SETGT_INT : R600_2OP < + 0x3B, "SGT_INT", + [] +>; + +def SETGE_INT : R600_2OP < + 0x3C, "SETGE_INT", + []>{ + let AMDILOp = AMDILInst.IGE; +} + +def SETNE_INT : R600_2OP < + 0x3D, "SETNE_INT", + []>{ + let AMDILOp = AMDILInst.INE; +} + +def SETGT_UINT : R600_2OP < + 0x3E, "SETGT_UINT", + []>{ + let AMDILOp = AMDILInst.UGT; +} + +def SETGE_UINT : R600_2OP < + 0x3F, "SETGE_UINT", + []>{ + let AMDILOp = AMDILInst.UGE; +} + +def CNDE_INT : R600_3OP < + 0x1C, "CNDE_INT", + [] +>; + +/* Texture instructions */ + + +def TEX_LD : R600_TEX < + 0x03, "TEX_LD", + [(set R600_Reg128:$dst, (int_AMDGPU_txf R600_Reg128:$src0, imm:$src1, imm:$src2))] +>; + +def TEX_GET_TEXTURE_RESINFO : R600_TEX < + 0x04, "TEX_GET_TEXTURE_RESINFO", + [(set R600_Reg128:$dst, (int_AMDGPU_txq R600_Reg128:$src0, imm:$src1, imm:$src2))] +>; + +def TEX_GET_GRADIENTS_H : R600_TEX < + 0x07, "TEX_GET_GRADIENTS_H", + [(set R600_Reg128:$dst, (int_AMDGPU_ddx R600_Reg128:$src0, imm:$src1, imm:$src2))] +>; + +def TEX_GET_GRADIENTS_V : R600_TEX < + 0x08, "TEX_GET_GRADIENTS_V", + [(set R600_Reg128:$dst, (int_AMDGPU_ddy R600_Reg128:$src0, imm:$src1, imm:$src2))] +>; + +def TEX_SAMPLE : R600_TEX < + 0x10, "TEX_SAMPLE", + [(set R600_Reg128:$dst, (int_AMDGPU_tex R600_Reg128:$src0, imm:$src1, imm:$src2))] +>; + +def TEX_SAMPLE_C : R600_TEX < + 0x18, "TEX_SAMPLE_C", + [(set R600_Reg128:$dst, (int_AMDGPU_tex R600_Reg128:$src0, imm:$src1, TEX_SHADOW:$src2))] +>; + +def TEX_SAMPLE_L : R600_TEX < + 0x11, "TEX_SAMPLE_L", + [(set R600_Reg128:$dst, (int_AMDGPU_txl R600_Reg128:$src0, imm:$src1, imm:$src2))] +>; + +def TEX_SAMPLE_C_L : R600_TEX < + 0x19, "TEX_SAMPLE_C_L", + [(set R600_Reg128:$dst, (int_AMDGPU_txl R600_Reg128:$src0, imm:$src1, TEX_SHADOW:$src2))] +>; + +def TEX_SAMPLE_LB : R600_TEX < + 0x12, "TEX_SAMPLE_LB", + [(set R600_Reg128:$dst, (int_AMDGPU_txb R600_Reg128:$src0, imm:$src1, imm:$src2))] +>; + +def TEX_SAMPLE_C_LB : R600_TEX < + 0x1A, "TEX_SAMPLE_C_LB", + [(set R600_Reg128:$dst, (int_AMDGPU_txb R600_Reg128:$src0, imm:$src1, TEX_SHADOW:$src2))] +>; + +def TEX_SAMPLE_G : R600_TEX < + 0x14, "TEX_SAMPLE_G", + [(set R600_Reg128:$dst, (int_AMDGPU_txd R600_Reg128:$src0, imm:$src1, imm:$src2))] +>; + +def TEX_SAMPLE_C_G : R600_TEX < + 0x1C, "TEX_SAMPLE_C_G", + [(set R600_Reg128:$dst, (int_AMDGPU_txd R600_Reg128:$src0, imm:$src1, TEX_SHADOW:$src2))] +>; + +} // End Gen R600_CAYMAN + +def KILP : Pat < + (int_AMDGPU_kilp), + (MASK_WRITE (KILLGT (f32 ONE), (f32 ZERO))) +>; + +def KIL : Pat < + (int_AMDGPU_kill R600_Reg32:$src0), + (MASK_WRITE (KILLGT (f32 ZERO), (f32 R600_Reg32:$src0))) +>; + +/* Helper classes for common instructions */ + +class MUL_LIT_Common inst> : R600_3OP < + inst, "MUL_LIT", + [] +>; + +class MULADD_Common inst> : R600_3OP < + inst, "MULADD", + []> { + let AMDILOp = AMDILInst.MAD_f32; +} + +class CNDE_Common inst> : R600_3OP < + inst, "CNDE", + []> { + let AMDILOp = AMDILInst.CMOVLOG_f32; +} + +class CNDGT_Common inst> : R600_3OP < + inst, "CNDGT", + [] +>; + +class CNDGE_Common inst> : R600_3OP < + inst, "CNDGE", + [(set R600_Reg32:$dst, (int_AMDGPU_cndlt R600_Reg32:$src0, R600_Reg32:$src2, R600_Reg32:$src1))] +>; + +class DOT4_Common inst> : R600_REDUCTION < + inst, + (ins R600_Reg128:$src0, R600_Reg128:$src1), + "DOT4 $dst $src0, $src1", + [(set R600_Reg32:$dst, (int_AMDGPU_dp4 R600_Reg128:$src0, R600_Reg128:$src1))] +>; + +class CUBE_Common inst> : InstR600 < + inst, + (outs R600_Reg128:$dst), + (ins R600_Reg128:$src), + "CUBE $dst $src", + [(set R600_Reg128:$dst, (int_AMDGPU_cube R600_Reg128:$src))], + VecALU +>; + +class EXP_IEEE_Common inst> : R600_1OP < + inst, "EXP_IEEE", + []> { + let AMDILOp = AMDILInst.EXP_f32; +} + +class FLT_TO_INT_Common inst> : R600_1OP < + inst, "FLT_TO_INT", []> { + let AMDILOp = AMDILInst.FTOI; +} + +class INT_TO_FLT_Common inst> : R600_1OP < + inst, "INT_TO_FLT", []> { + let AMDILOp = AMDILInst.ITOF; +} + +class LOG_CLAMPED_Common inst> : R600_1OP < + inst, "LOG_CLAMPED", + [] +>; + +class LOG_IEEE_Common inst> : R600_1OP < + inst, "LOG_IEEE", + []> { + let AMDILOp = AMDILInst.LOG_f32; +} + +class LSHL_Common inst> : R600_2OP < + inst, "LSHL $dst, $src0, $src1", + [] >{ + let AMDILOp = AMDILInst.SHL_i32; +} + +class LSHR_Common inst> : R600_2OP < + inst, "LSHR $dst, $src0, $src1", + [] >{ + let AMDILOp = AMDILInst.USHR_i32; +} + +class ASHR_Common inst> : R600_2OP < + inst, "ASHR $dst, $src0, $src1", + [] >{ + let AMDILOp = AMDILInst.SHR_i32; +} + +class MULHI_INT_Common inst> : R600_2OP < + inst, "MULHI_INT $dst, $src0, $src1", + [] >{ + let AMDILOp = AMDILInst.SMULHI_i32; +} + +class MULHI_UINT_Common inst> : R600_2OP < + inst, "MULHI $dst, $src0, $src1", + [] +>; + +class MULLO_INT_Common inst> : R600_2OP < + inst, "MULLO_INT $dst, $src0, $src1", + [] >{ + let AMDILOp = AMDILInst.SMUL_i32; +} + +class MULLO_UINT_Common inst> : R600_2OP < + inst, "MULLO_UINT $dst, $src0, $src1", + [] +>; + +class RECIP_CLAMPED_Common inst> : R600_1OP < + inst, "RECIP_CLAMPED", + [] +>; + +class RECIP_IEEE_Common inst> : R600_1OP < + inst, "RECIP_IEEE", + [(set R600_Reg32:$dst, (int_AMDGPU_rcp R600_Reg32:$src))]> { + let AMDILOp = AMDILInst.RSQ_f32; +} + +class RECIP_UINT_Common inst> : R600_1OP < + inst, "RECIP_INT $dst, $src", + [] +>; + +class RECIPSQRT_CLAMPED_Common inst> : R600_1OP < + inst, "RECIPSQRT_CLAMPED", + [(set R600_Reg32:$dst, (int_AMDGPU_rsq R600_Reg32:$src))] +>; + +class RECIPSQRT_IEEE_Common inst> : R600_1OP < + inst, "RECIPSQRT_IEEE", + [] +>; + +class SIN_Common inst> : R600_1OP < + inst, "SIN", + []>{ + let AMDILOp = AMDILInst.SIN_f32; + let Trig = 1; +} + +class COS_Common inst> : R600_1OP < + inst, "COS", + []> { + let AMDILOp = AMDILInst.COS_f32; + let Trig = 1; +} + +/* Helper patterns for complex intrinsics */ +/* -------------------------------------- */ + +class DIV_Common : Pat< + (int_AMDGPU_div R600_Reg32:$src0, R600_Reg32:$src1), + (MUL R600_Reg32:$src0, (recip_ieee R600_Reg32:$src1)) +>; + +class LRP_Common : Pat < + (int_AMDGPU_lrp R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2), + (muladd R600_Reg32:$src0, R600_Reg32:$src1, (MUL (SUB_f32 ONE, R600_Reg32:$src0), R600_Reg32:$src2)) +>; + +class SSG_Common : Pat < + (int_AMDGPU_ssg R600_Reg32:$src), + (cndgt R600_Reg32:$src, (f32 ONE), (cndge R600_Reg32:$src, (f32 ZERO), (f32 NEG_ONE))) +>; + +class TGSI_LIT_Z_Common : Pat < + (int_TGSI_lit_z R600_Reg32:$src_x, R600_Reg32:$src_y, R600_Reg32:$src_w), + (exp_ieee (mul_lit (log_clamped (MAX R600_Reg32:$src_y, (f32 ZERO))), R600_Reg32:$src_w, R600_Reg32:$src_x)) +>; + +/* ---------------------- */ +/* R600 / R700 Only Instructions */ +/* ---------------------- */ + +let Predicates = [isR600] in { + +let Gen = AMDGPUGen.R600 in { + + def MUL_LIT_r600 : MUL_LIT_Common<0x0C>; + def MULADD_r600 : MULADD_Common<0x10>; + def CNDE_r600 : CNDE_Common<0x18>; + def CNDGT_r600 : CNDGT_Common<0x19>; + def CNDGE_r600 : CNDGE_Common<0x1A>; + def DOT4_r600 : DOT4_Common<0x50>; + def CUBE_r600 : CUBE_Common<0x52>; + def EXP_IEEE_r600 : EXP_IEEE_Common<0x61>; + def LOG_CLAMPED_r600 : LOG_CLAMPED_Common<0x62>; + def LOG_IEEE_r600 : LOG_IEEE_Common<0x63>; + def RECIP_CLAMPED_r600 : RECIP_CLAMPED_Common<0x64>; + def RECIP_IEEE_r600 : RECIP_IEEE_Common<0x66>; + def RECIPSQRT_CLAMPED_r600 : RECIPSQRT_CLAMPED_Common<0x67>; + def RECIPSQRT_IEEE_r600 : RECIPSQRT_IEEE_Common<0x69>; + def FLT_TO_INT_r600 : FLT_TO_INT_Common<0x6b>; + def INT_TO_FLT_r600 : INT_TO_FLT_Common<0x6c>; + def SIN_r600 : SIN_Common<0x6E>; + def COS_r600 : COS_Common<0x6F>; + def ASHR_r600 : ASHR_Common<0x70>; + def LSHR_r600 : LSHR_Common<0x71>; + def LSHL_r600 : LSHL_Common<0x72>; + def MULLO_INT_r600 : MULLO_INT_Common<0x73>; + def MULHI_INT_r600 : MULHI_INT_Common<0x74>; + def MULLO_UINT_r600 : MULLO_UINT_Common<0x75>; + def MULHI_UINT_r600 : MULHI_UINT_Common<0x76>; + def RECIP_UINT_r600 : RECIP_UINT_Common <0x77>; + +} // End AMDGPUGen.R600 + + def DIV_r600 : DIV_Common; + def LRP_r600 : LRP_Common; + def POW_r600 : POW_Common; + def SSG_r600 : SSG_Common; + def TGSI_LIT_Z_r600 : TGSI_LIT_Z_Common; + +} + +/* ----------------- */ +/* R700+ Trig helper */ +/* ----------------- */ + +/* +class TRIG_HELPER_r700 : Pat < + (trig_inst R600_Reg32:$src), + (trig_inst (fmul R600_Reg32:$src, (PI)))) +>; +*/ + +/* ---------------------- */ +/* Evergreen Instructions */ +/* ---------------------- */ + + +let Predicates = [isEG] in { + +let Gen = AMDGPUGen.EG in { + +def RAT_WRITE_CACHELESS_eg : + EG_CF_RAT <0x57, 0x2, (outs), (ins R600_TReg32_X:$rw_gpr, + R600_TReg32_X:$index_gpr, i32imm:$rat_id), ""> +{ + let RIM = 0; + /* XXX: Have a separate instruction for non-indexed writes. */ + let TYPE = 1; + let RW_REL = 0; + let ELEM_SIZE = 0; + + let ARRAY_SIZE = 0; + let COMP_MASK = 1; + let BURST_COUNT = 0; + let VPM = 0; + let EOP = 0; + let MARK = 0; + let BARRIER = 1; +} + +def VTX_READ_eg : InstR600ISA < (outs R600_TReg32_X:$dst), + (ins R600_TReg32_X:$src, i32imm:$buffer_id), + "VTX_READ_eg $dst, $src", []> +{ +/* + bits<7> DST_GPR; + bits<7> SRC_GPR; + bits<8> BUFFER_ID; +*/ + /* If any of these field below need to be calculated at compile time, and + * a ins operand for them and move them to the list of operands above. */ + + /* XXX: This instruction is manual encoded, so none of these values are used. + */ +/* + bits<5> VC_INST = 0; //VC_INST_FETCH + bits<2> FETCH_TYPE = 2; + bits<1> FETCH_WHOLE_QUAD = 1; + bits<1> SRC_REL = 0; + bits<2> SRC_SEL_X = 0; + bits<6> MEGA_FETCH_COUNT = 4; +*/ +/* + + bits<1> DST_REL = 0; + bits<3> DST_SEL_X = 0; + bits<3> DST_SEL_Y = 7; //Masked + bits<3> DST_SEL_Z = 7; //Masked + bits<3> DST_SEL_W = 7; //Masked + bits<1> USE_CONST_FIELDS = 1; //Masked + bits<6> DATA_FORMAT = 0; + bits<2> NUM_FORMAT_ALL = 0; + bits<1> FORMAT_COMP_ALL = 0; + bits<1> SRF_MODE_ALL = 0; +*/ + +/* + let Inst{4-0} = VC_INST; + let Inst{6-5} = FETCH_TYPE; + let Inst{7} = FETCH_WHOLE_QUAD; + let Inst{15-8} = BUFFER_ID; + let Inst{22-16} = SRC_GPR; + let Inst{23} = SRC_REL; + let Inst{25-24} = SRC_SEL_X; + let Inst{31-26} = MEGA_FETCH_COUNT; +*/ + /* DST_GPR is OK to leave uncommented, because LLVM 3.0 only prevents you + * from statically setting bits > 31. This field will be set by + * getMachineValueOp which can set bits > 31. + */ +// let Inst{32-38} = DST_GPR; + + /* XXX: Uncomment for LLVM 3.1 which supports 64-bit instructions */ + +/* + let Inst{39} = DST_REL; + let Inst{40} = 0; //Reserved + let Inst{43-41} = DST_SEL_X; + let Inst{46-44} = DST_SEL_Y; + let Inst{49-47} = DST_SEL_Z; + let Inst{52-50} = DST_SEL_W; + let Inst{53} = USE_CONST_FIELDS; + let Inst{59-54} = DATA_FORMAT; + let Inst{61-60} = NUM_FORMAT_ALL; + let Inst{62} = FORMAT_COMP_ALL; + let Inst{63} = SRF_MODE_ALL; +*/ +} + + + +} // End AMDGPUGen.EG +/* XXX: Need to convert PTR to rat_id */ +/* +def : Pat <(store_global (f32 R600_Reg32:$value), node:$ptr), + (RAT_WRITE_CACHELESS_eg (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), + (f32 R600_Reg32:$value), + sel_x), + (f32 ZERO), 0, R600_Reg32:$ptr)>; +*/ + +class VTX_Param_Read_Pattern : Pat < + (vt (load_param ADDRParam:$mem)), + (VTX_READ_eg (i32 R600_Reg32:$mem), 0)>; + +def : VTX_Param_Read_Pattern ; +def : VTX_Param_Read_Pattern ; + +} // End isEG Predicate + +/* ------------------------------- */ +/* Evergreen / Cayman Instructions */ +/* ------------------------------- */ + +let Predicates = [isEGorCayman] in { + +class TRIG_eg : Pat< + (intr R600_Reg32:$src), + (trig (MUL (MOV (LOADCONST_i32 CONST.TWO_PI_INV)), R600_Reg32:$src)) +>; + +let Gen = AMDGPUGen.EG_CAYMAN in { + + def MULADD_eg : MULADD_Common<0x14>; + def ASHR_eg : ASHR_Common<0x15>; + def LSHR_eg : LSHR_Common<0x16>; + def LSHL_eg : LSHL_Common<0x17>; + def CNDE_eg : CNDE_Common<0x19>; + def CNDGT_eg : CNDGT_Common<0x1A>; + def CNDGE_eg : CNDGE_Common<0x1B>; + def MUL_LIT_eg : MUL_LIT_Common<0x1F>; + def FLT_TO_INT_eg : FLT_TO_INT_Common<0x50>; + def EXP_IEEE_eg : EXP_IEEE_Common<0x81>; + def LOG_CLAMPED_eg : LOG_CLAMPED_Common<0x82>; + def LOG_IEEE_eg : LOG_IEEE_Common<0x83>; + def RECIP_CLAMPED_eg : RECIP_CLAMPED_Common<0x84>; + def RECIP_IEEE_eg : RECIP_IEEE_Common<0x86>; + def RECIPSQRT_CLAMPED_eg : RECIPSQRT_CLAMPED_Common<0x87>; + def RECIPSQRT_IEEE_eg : RECIPSQRT_IEEE_Common<0x89>; + def SIN_eg : SIN_Common<0x8D>; + def COS_eg : COS_Common<0x8E>; + def MULLO_INT_eg : MULLO_INT_Common<0x8F>; + def MULHI_INT_eg : MULHI_INT_Common<0x90>; + def MULLO_UINT_eg : MULLO_UINT_Common<0x91>; + def MULHI_UINT_eg : MULHI_UINT_Common<0x92>; + def RECIP_UINT_eg : RECIP_UINT_Common<0x94>; + def INT_TO_FLT_eg : INT_TO_FLT_Common<0x9B>; + def DOT4_eg : DOT4_Common<0xBE>; + def CUBE_eg : CUBE_Common<0xC0>; + +} // End AMDGPUGen.EG_CAYMAN + + def DIV_eg : DIV_Common; + def LRP_eg : LRP_Common; + def POW_eg : POW_Common; + def SSG_eg : SSG_Common; + def TGSI_LIT_Z_eg : TGSI_LIT_Z_Common; + + def : TRIG_eg ; + def : TRIG_eg ; + +} + +let Predicates = [isCayman] in { + +let Gen = AMDGPUGen.CAYMAN in { + + /* XXX: I'm not sure if this opcode is correct. */ + def RECIP_UINT_cm : RECIP_UINT_Common<0x77>; + +} // End AMDGPUGen.CAYMAN + +} // End isCayman + +/* Other Instructions */ + +let isCodeGenOnly = 1 in { +/* + def SWIZZLE : AMDGPUShaderInst < + (outs GPRV4F32:$dst), + (ins GPRV4F32:$src0, i32imm:$src1), + "SWIZZLE $dst, $src0, $src1", + [(set GPRV4F32:$dst, (int_AMDGPU_swizzle GPRV4F32:$src0, imm:$src1))] + >; +*/ + + def LAST : AMDGPUShaderInst < + (outs), + (ins), + "LAST", + [] + >; + + def GET_CHAN : AMDGPUShaderInst < + (outs R600_Reg32:$dst), + (ins R600_Reg128:$src0, i32imm:$src1), + "GET_CHAN $dst, $src0, $src1", + [] + >; + + def MULLIT : AMDGPUShaderInst < + (outs R600_Reg128:$dst), + (ins R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2), + "MULLIT $dst, $src0, $src1", + [(set R600_Reg128:$dst, (int_AMDGPU_mullit R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2))] + >; + +let usesCustomInserter = 1, isPseudo = 1 in { + +class R600PreloadInst : AMDGPUInst < + (outs R600_TReg32:$dst), + (ins), + asm, + [(set R600_TReg32:$dst, (intr))] +>; + +def TGID_X : R600PreloadInst <"TGID_X", int_r600_read_tgid_x>; +def TGID_Y : R600PreloadInst <"TGID_Y", int_r600_read_tgid_y>; +def TGID_Z : R600PreloadInst <"TGID_Z", int_r600_read_tgid_z>; + +def TIDIG_X : R600PreloadInst <"TIDIG_X", int_r600_read_tidig_x>; +def TIDIG_Y : R600PreloadInst <"TIDIG_Y", int_r600_read_tidig_y>; +def TIDIG_Z : R600PreloadInst <"TIDIG_Z", int_r600_read_tidig_z>; + +def NGROUPS_X : R600PreloadInst <"NGROUPS_X", int_r600_read_ngroups_x>; +def NGROUPS_Y : R600PreloadInst <"NGROUPS_Y", int_r600_read_ngroups_y>; +def NGROUPS_Z : R600PreloadInst <"NGROUPS_Z", int_r600_read_ngroups_z>; + +def GLOBAL_SIZE_X : R600PreloadInst <"GLOBAL_SIZE_X", + int_r600_read_global_size_x>; +def GLOBAL_SIZE_Y : R600PreloadInst <"GLOBAL_SIZE_Y", + int_r600_read_global_size_y>; +def GLOBAL_SIZE_Z : R600PreloadInst <"GLOBAL_SIZE_Z", + int_r600_read_global_size_z>; + +def LOCAL_SIZE_X : R600PreloadInst <"LOCAL_SIZE_X", + int_r600_read_local_size_x>; +def LOCAL_SIZE_Y : R600PreloadInst <"LOCAL_SIZE_Y", + int_r600_read_local_size_y>; +def LOCAL_SIZE_Z : R600PreloadInst <"LOCAL_SIZE_Z", + int_r600_read_local_size_z>; + +def R600_LOAD_CONST : AMDGPUShaderInst < + (outs R600_Reg32:$dst), + (ins i32imm:$src0), + "R600_LOAD_CONST $dst, $src0", + [(set R600_Reg32:$dst, (int_AMDGPU_load_const imm:$src0))] +>; + +def LOAD_INPUT : AMDGPUShaderInst < + (outs R600_Reg32:$dst), + (ins i32imm:$src), + "LOAD_INPUT $dst, $src", + [(set R600_Reg32:$dst, (int_R600_load_input imm:$src))] +>; + +def RESERVE_REG : AMDGPUShaderInst < + (outs), + (ins i32imm:$src), + "RESERVE_REG $src", + [(int_AMDGPU_reserve_reg imm:$src)] +>; + +def STORE_OUTPUT: AMDGPUShaderInst < + (outs), + (ins R600_Reg32:$src0, i32imm:$src1), + "STORE_OUTPUT $src0, $src1", + [(int_AMDGPU_store_output R600_Reg32:$src0, imm:$src1)] +>; + +} // End usesCustomInserter = 1, isPseudo = 1 + +} // End isCodeGenOnly = 1 + + + +let isPseudo = 1 in { + +def LOAD_VTX : AMDGPUShaderInst < + (outs R600_Reg32:$dst), + (ins MEMri:$mem), + "LOAD_VTX", + [(set (i32 R600_Reg32:$dst), (load_param ADDRParam:$mem))] +>; + + +} //End isPseudo + +def : Extract_Element ; +def : Extract_Element ; +def : Extract_Element ; +def : Extract_Element ; + +def : Insert_Element ; +def : Insert_Element ; +def : Insert_Element ; +def : Insert_Element ; + +def : Extract_Element ; +def : Extract_Element ; +def : Extract_Element ; +def : Extract_Element ; + +def : Insert_Element ; +def : Insert_Element ; +def : Insert_Element ; +def : Insert_Element ; + +} // End isR600toCayman Predicate diff --git a/lib/Target/AMDIL/R600Intrinsics.td b/lib/Target/AMDIL/R600Intrinsics.td new file mode 100644 index 00000000000..96b9ae808a2 --- /dev/null +++ b/lib/Target/AMDIL/R600Intrinsics.td @@ -0,0 +1,16 @@ +//===-- R600Intrinsics.td - R600 Instrinsic defs -------*- tablegen -*-----===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// R600 Intrinsic Definitions +// +//===----------------------------------------------------------------------===// + +let TargetPrefix = "R600", isTarget = 1 in { + def int_R600_load_input : Intrinsic<[llvm_float_ty], [llvm_i32_ty], [IntrReadWriteArgMem]>; +} diff --git a/lib/Target/AMDIL/R600RegisterInfo.td b/lib/Target/AMDIL/R600RegisterInfo.td new file mode 100644 index 00000000000..fac85367515 --- /dev/null +++ b/lib/Target/AMDIL/R600RegisterInfo.td @@ -0,0 +1,1889 @@ + +class R600Reg : Register { + let Namespace = "AMDIL"; +} + +class R600Reg_128 subregs> : RegisterWithSubRegs { + let Namespace = "AMDIL"; + let SubRegIndices = [sel_x, sel_y, sel_z, sel_w]; +} + +def C0_X : R600Reg <"C0.X">; +def C0_Y : R600Reg <"C0.Y">; +def C0_Z : R600Reg <"C0.Z">; +def C0_W : R600Reg <"C0.W">; +def C1_X : R600Reg <"C1.X">; +def C1_Y : R600Reg <"C1.Y">; +def C1_Z : R600Reg <"C1.Z">; +def C1_W : R600Reg <"C1.W">; +def C2_X : R600Reg <"C2.X">; +def C2_Y : R600Reg <"C2.Y">; +def C2_Z : R600Reg <"C2.Z">; +def C2_W : R600Reg <"C2.W">; +def C3_X : R600Reg <"C3.X">; +def C3_Y : R600Reg <"C3.Y">; +def C3_Z : R600Reg <"C3.Z">; +def C3_W : R600Reg <"C3.W">; +def C4_X : R600Reg <"C4.X">; +def C4_Y : R600Reg <"C4.Y">; +def C4_Z : R600Reg <"C4.Z">; +def C4_W : R600Reg <"C4.W">; +def C5_X : R600Reg <"C5.X">; +def C5_Y : R600Reg <"C5.Y">; +def C5_Z : R600Reg <"C5.Z">; +def C5_W : R600Reg <"C5.W">; +def C6_X : R600Reg <"C6.X">; +def C6_Y : R600Reg <"C6.Y">; +def C6_Z : R600Reg <"C6.Z">; +def C6_W : R600Reg <"C6.W">; +def C7_X : R600Reg <"C7.X">; +def C7_Y : R600Reg <"C7.Y">; +def C7_Z : R600Reg <"C7.Z">; +def C7_W : R600Reg <"C7.W">; +def C8_X : R600Reg <"C8.X">; +def C8_Y : R600Reg <"C8.Y">; +def C8_Z : R600Reg <"C8.Z">; +def C8_W : R600Reg <"C8.W">; +def C9_X : R600Reg <"C9.X">; +def C9_Y : R600Reg <"C9.Y">; +def C9_Z : R600Reg <"C9.Z">; +def C9_W : R600Reg <"C9.W">; +def C10_X : R600Reg <"C10.X">; +def C10_Y : R600Reg <"C10.Y">; +def C10_Z : R600Reg <"C10.Z">; +def C10_W : R600Reg <"C10.W">; +def C11_X : R600Reg <"C11.X">; +def C11_Y : R600Reg <"C11.Y">; +def C11_Z : R600Reg <"C11.Z">; +def C11_W : R600Reg <"C11.W">; +def C12_X : R600Reg <"C12.X">; +def C12_Y : R600Reg <"C12.Y">; +def C12_Z : R600Reg <"C12.Z">; +def C12_W : R600Reg <"C12.W">; +def C13_X : R600Reg <"C13.X">; +def C13_Y : R600Reg <"C13.Y">; +def C13_Z : R600Reg <"C13.Z">; +def C13_W : R600Reg <"C13.W">; +def C14_X : R600Reg <"C14.X">; +def C14_Y : R600Reg <"C14.Y">; +def C14_Z : R600Reg <"C14.Z">; +def C14_W : R600Reg <"C14.W">; +def C15_X : R600Reg <"C15.X">; +def C15_Y : R600Reg <"C15.Y">; +def C15_Z : R600Reg <"C15.Z">; +def C15_W : R600Reg <"C15.W">; +def C16_X : R600Reg <"C16.X">; +def C16_Y : R600Reg <"C16.Y">; +def C16_Z : R600Reg <"C16.Z">; +def C16_W : R600Reg <"C16.W">; +def C17_X : R600Reg <"C17.X">; +def C17_Y : R600Reg <"C17.Y">; +def C17_Z : R600Reg <"C17.Z">; +def C17_W : R600Reg <"C17.W">; +def C18_X : R600Reg <"C18.X">; +def C18_Y : R600Reg <"C18.Y">; +def C18_Z : R600Reg <"C18.Z">; +def C18_W : R600Reg <"C18.W">; +def C19_X : R600Reg <"C19.X">; +def C19_Y : R600Reg <"C19.Y">; +def C19_Z : R600Reg <"C19.Z">; +def C19_W : R600Reg <"C19.W">; +def C20_X : R600Reg <"C20.X">; +def C20_Y : R600Reg <"C20.Y">; +def C20_Z : R600Reg <"C20.Z">; +def C20_W : R600Reg <"C20.W">; +def C21_X : R600Reg <"C21.X">; +def C21_Y : R600Reg <"C21.Y">; +def C21_Z : R600Reg <"C21.Z">; +def C21_W : R600Reg <"C21.W">; +def C22_X : R600Reg <"C22.X">; +def C22_Y : R600Reg <"C22.Y">; +def C22_Z : R600Reg <"C22.Z">; +def C22_W : R600Reg <"C22.W">; +def C23_X : R600Reg <"C23.X">; +def C23_Y : R600Reg <"C23.Y">; +def C23_Z : R600Reg <"C23.Z">; +def C23_W : R600Reg <"C23.W">; +def C24_X : R600Reg <"C24.X">; +def C24_Y : R600Reg <"C24.Y">; +def C24_Z : R600Reg <"C24.Z">; +def C24_W : R600Reg <"C24.W">; +def C25_X : R600Reg <"C25.X">; +def C25_Y : R600Reg <"C25.Y">; +def C25_Z : R600Reg <"C25.Z">; +def C25_W : R600Reg <"C25.W">; +def C26_X : R600Reg <"C26.X">; +def C26_Y : R600Reg <"C26.Y">; +def C26_Z : R600Reg <"C26.Z">; +def C26_W : R600Reg <"C26.W">; +def C27_X : R600Reg <"C27.X">; +def C27_Y : R600Reg <"C27.Y">; +def C27_Z : R600Reg <"C27.Z">; +def C27_W : R600Reg <"C27.W">; +def C28_X : R600Reg <"C28.X">; +def C28_Y : R600Reg <"C28.Y">; +def C28_Z : R600Reg <"C28.Z">; +def C28_W : R600Reg <"C28.W">; +def C29_X : R600Reg <"C29.X">; +def C29_Y : R600Reg <"C29.Y">; +def C29_Z : R600Reg <"C29.Z">; +def C29_W : R600Reg <"C29.W">; +def C30_X : R600Reg <"C30.X">; +def C30_Y : R600Reg <"C30.Y">; +def C30_Z : R600Reg <"C30.Z">; +def C30_W : R600Reg <"C30.W">; +def C31_X : R600Reg <"C31.X">; +def C31_Y : R600Reg <"C31.Y">; +def C31_Z : R600Reg <"C31.Z">; +def C31_W : R600Reg <"C31.W">; +def C32_X : R600Reg <"C32.X">; +def C32_Y : R600Reg <"C32.Y">; +def C32_Z : R600Reg <"C32.Z">; +def C32_W : R600Reg <"C32.W">; +def C33_X : R600Reg <"C33.X">; +def C33_Y : R600Reg <"C33.Y">; +def C33_Z : R600Reg <"C33.Z">; +def C33_W : R600Reg <"C33.W">; +def C34_X : R600Reg <"C34.X">; +def C34_Y : R600Reg <"C34.Y">; +def C34_Z : R600Reg <"C34.Z">; +def C34_W : R600Reg <"C34.W">; +def C35_X : R600Reg <"C35.X">; +def C35_Y : R600Reg <"C35.Y">; +def C35_Z : R600Reg <"C35.Z">; +def C35_W : R600Reg <"C35.W">; +def C36_X : R600Reg <"C36.X">; +def C36_Y : R600Reg <"C36.Y">; +def C36_Z : R600Reg <"C36.Z">; +def C36_W : R600Reg <"C36.W">; +def C37_X : R600Reg <"C37.X">; +def C37_Y : R600Reg <"C37.Y">; +def C37_Z : R600Reg <"C37.Z">; +def C37_W : R600Reg <"C37.W">; +def C38_X : R600Reg <"C38.X">; +def C38_Y : R600Reg <"C38.Y">; +def C38_Z : R600Reg <"C38.Z">; +def C38_W : R600Reg <"C38.W">; +def C39_X : R600Reg <"C39.X">; +def C39_Y : R600Reg <"C39.Y">; +def C39_Z : R600Reg <"C39.Z">; +def C39_W : R600Reg <"C39.W">; +def C40_X : R600Reg <"C40.X">; +def C40_Y : R600Reg <"C40.Y">; +def C40_Z : R600Reg <"C40.Z">; +def C40_W : R600Reg <"C40.W">; +def C41_X : R600Reg <"C41.X">; +def C41_Y : R600Reg <"C41.Y">; +def C41_Z : R600Reg <"C41.Z">; +def C41_W : R600Reg <"C41.W">; +def C42_X : R600Reg <"C42.X">; +def C42_Y : R600Reg <"C42.Y">; +def C42_Z : R600Reg <"C42.Z">; +def C42_W : R600Reg <"C42.W">; +def C43_X : R600Reg <"C43.X">; +def C43_Y : R600Reg <"C43.Y">; +def C43_Z : R600Reg <"C43.Z">; +def C43_W : R600Reg <"C43.W">; +def C44_X : R600Reg <"C44.X">; +def C44_Y : R600Reg <"C44.Y">; +def C44_Z : R600Reg <"C44.Z">; +def C44_W : R600Reg <"C44.W">; +def C45_X : R600Reg <"C45.X">; +def C45_Y : R600Reg <"C45.Y">; +def C45_Z : R600Reg <"C45.Z">; +def C45_W : R600Reg <"C45.W">; +def C46_X : R600Reg <"C46.X">; +def C46_Y : R600Reg <"C46.Y">; +def C46_Z : R600Reg <"C46.Z">; +def C46_W : R600Reg <"C46.W">; +def C47_X : R600Reg <"C47.X">; +def C47_Y : R600Reg <"C47.Y">; +def C47_Z : R600Reg <"C47.Z">; +def C47_W : R600Reg <"C47.W">; +def C48_X : R600Reg <"C48.X">; +def C48_Y : R600Reg <"C48.Y">; +def C48_Z : R600Reg <"C48.Z">; +def C48_W : R600Reg <"C48.W">; +def C49_X : R600Reg <"C49.X">; +def C49_Y : R600Reg <"C49.Y">; +def C49_Z : R600Reg <"C49.Z">; +def C49_W : R600Reg <"C49.W">; +def C50_X : R600Reg <"C50.X">; +def C50_Y : R600Reg <"C50.Y">; +def C50_Z : R600Reg <"C50.Z">; +def C50_W : R600Reg <"C50.W">; +def C51_X : R600Reg <"C51.X">; +def C51_Y : R600Reg <"C51.Y">; +def C51_Z : R600Reg <"C51.Z">; +def C51_W : R600Reg <"C51.W">; +def C52_X : R600Reg <"C52.X">; +def C52_Y : R600Reg <"C52.Y">; +def C52_Z : R600Reg <"C52.Z">; +def C52_W : R600Reg <"C52.W">; +def C53_X : R600Reg <"C53.X">; +def C53_Y : R600Reg <"C53.Y">; +def C53_Z : R600Reg <"C53.Z">; +def C53_W : R600Reg <"C53.W">; +def C54_X : R600Reg <"C54.X">; +def C54_Y : R600Reg <"C54.Y">; +def C54_Z : R600Reg <"C54.Z">; +def C54_W : R600Reg <"C54.W">; +def C55_X : R600Reg <"C55.X">; +def C55_Y : R600Reg <"C55.Y">; +def C55_Z : R600Reg <"C55.Z">; +def C55_W : R600Reg <"C55.W">; +def C56_X : R600Reg <"C56.X">; +def C56_Y : R600Reg <"C56.Y">; +def C56_Z : R600Reg <"C56.Z">; +def C56_W : R600Reg <"C56.W">; +def C57_X : R600Reg <"C57.X">; +def C57_Y : R600Reg <"C57.Y">; +def C57_Z : R600Reg <"C57.Z">; +def C57_W : R600Reg <"C57.W">; +def C58_X : R600Reg <"C58.X">; +def C58_Y : R600Reg <"C58.Y">; +def C58_Z : R600Reg <"C58.Z">; +def C58_W : R600Reg <"C58.W">; +def C59_X : R600Reg <"C59.X">; +def C59_Y : R600Reg <"C59.Y">; +def C59_Z : R600Reg <"C59.Z">; +def C59_W : R600Reg <"C59.W">; +def C60_X : R600Reg <"C60.X">; +def C60_Y : R600Reg <"C60.Y">; +def C60_Z : R600Reg <"C60.Z">; +def C60_W : R600Reg <"C60.W">; +def C61_X : R600Reg <"C61.X">; +def C61_Y : R600Reg <"C61.Y">; +def C61_Z : R600Reg <"C61.Z">; +def C61_W : R600Reg <"C61.W">; +def C62_X : R600Reg <"C62.X">; +def C62_Y : R600Reg <"C62.Y">; +def C62_Z : R600Reg <"C62.Z">; +def C62_W : R600Reg <"C62.W">; +def C63_X : R600Reg <"C63.X">; +def C63_Y : R600Reg <"C63.Y">; +def C63_Z : R600Reg <"C63.Z">; +def C63_W : R600Reg <"C63.W">; +def C64_X : R600Reg <"C64.X">; +def C64_Y : R600Reg <"C64.Y">; +def C64_Z : R600Reg <"C64.Z">; +def C64_W : R600Reg <"C64.W">; +def C65_X : R600Reg <"C65.X">; +def C65_Y : R600Reg <"C65.Y">; +def C65_Z : R600Reg <"C65.Z">; +def C65_W : R600Reg <"C65.W">; +def C66_X : R600Reg <"C66.X">; +def C66_Y : R600Reg <"C66.Y">; +def C66_Z : R600Reg <"C66.Z">; +def C66_W : R600Reg <"C66.W">; +def C67_X : R600Reg <"C67.X">; +def C67_Y : R600Reg <"C67.Y">; +def C67_Z : R600Reg <"C67.Z">; +def C67_W : R600Reg <"C67.W">; +def C68_X : R600Reg <"C68.X">; +def C68_Y : R600Reg <"C68.Y">; +def C68_Z : R600Reg <"C68.Z">; +def C68_W : R600Reg <"C68.W">; +def C69_X : R600Reg <"C69.X">; +def C69_Y : R600Reg <"C69.Y">; +def C69_Z : R600Reg <"C69.Z">; +def C69_W : R600Reg <"C69.W">; +def C70_X : R600Reg <"C70.X">; +def C70_Y : R600Reg <"C70.Y">; +def C70_Z : R600Reg <"C70.Z">; +def C70_W : R600Reg <"C70.W">; +def C71_X : R600Reg <"C71.X">; +def C71_Y : R600Reg <"C71.Y">; +def C71_Z : R600Reg <"C71.Z">; +def C71_W : R600Reg <"C71.W">; +def C72_X : R600Reg <"C72.X">; +def C72_Y : R600Reg <"C72.Y">; +def C72_Z : R600Reg <"C72.Z">; +def C72_W : R600Reg <"C72.W">; +def C73_X : R600Reg <"C73.X">; +def C73_Y : R600Reg <"C73.Y">; +def C73_Z : R600Reg <"C73.Z">; +def C73_W : R600Reg <"C73.W">; +def C74_X : R600Reg <"C74.X">; +def C74_Y : R600Reg <"C74.Y">; +def C74_Z : R600Reg <"C74.Z">; +def C74_W : R600Reg <"C74.W">; +def C75_X : R600Reg <"C75.X">; +def C75_Y : R600Reg <"C75.Y">; +def C75_Z : R600Reg <"C75.Z">; +def C75_W : R600Reg <"C75.W">; +def C76_X : R600Reg <"C76.X">; +def C76_Y : R600Reg <"C76.Y">; +def C76_Z : R600Reg <"C76.Z">; +def C76_W : R600Reg <"C76.W">; +def C77_X : R600Reg <"C77.X">; +def C77_Y : R600Reg <"C77.Y">; +def C77_Z : R600Reg <"C77.Z">; +def C77_W : R600Reg <"C77.W">; +def C78_X : R600Reg <"C78.X">; +def C78_Y : R600Reg <"C78.Y">; +def C78_Z : R600Reg <"C78.Z">; +def C78_W : R600Reg <"C78.W">; +def C79_X : R600Reg <"C79.X">; +def C79_Y : R600Reg <"C79.Y">; +def C79_Z : R600Reg <"C79.Z">; +def C79_W : R600Reg <"C79.W">; +def C80_X : R600Reg <"C80.X">; +def C80_Y : R600Reg <"C80.Y">; +def C80_Z : R600Reg <"C80.Z">; +def C80_W : R600Reg <"C80.W">; +def C81_X : R600Reg <"C81.X">; +def C81_Y : R600Reg <"C81.Y">; +def C81_Z : R600Reg <"C81.Z">; +def C81_W : R600Reg <"C81.W">; +def C82_X : R600Reg <"C82.X">; +def C82_Y : R600Reg <"C82.Y">; +def C82_Z : R600Reg <"C82.Z">; +def C82_W : R600Reg <"C82.W">; +def C83_X : R600Reg <"C83.X">; +def C83_Y : R600Reg <"C83.Y">; +def C83_Z : R600Reg <"C83.Z">; +def C83_W : R600Reg <"C83.W">; +def C84_X : R600Reg <"C84.X">; +def C84_Y : R600Reg <"C84.Y">; +def C84_Z : R600Reg <"C84.Z">; +def C84_W : R600Reg <"C84.W">; +def C85_X : R600Reg <"C85.X">; +def C85_Y : R600Reg <"C85.Y">; +def C85_Z : R600Reg <"C85.Z">; +def C85_W : R600Reg <"C85.W">; +def C86_X : R600Reg <"C86.X">; +def C86_Y : R600Reg <"C86.Y">; +def C86_Z : R600Reg <"C86.Z">; +def C86_W : R600Reg <"C86.W">; +def C87_X : R600Reg <"C87.X">; +def C87_Y : R600Reg <"C87.Y">; +def C87_Z : R600Reg <"C87.Z">; +def C87_W : R600Reg <"C87.W">; +def C88_X : R600Reg <"C88.X">; +def C88_Y : R600Reg <"C88.Y">; +def C88_Z : R600Reg <"C88.Z">; +def C88_W : R600Reg <"C88.W">; +def C89_X : R600Reg <"C89.X">; +def C89_Y : R600Reg <"C89.Y">; +def C89_Z : R600Reg <"C89.Z">; +def C89_W : R600Reg <"C89.W">; +def C90_X : R600Reg <"C90.X">; +def C90_Y : R600Reg <"C90.Y">; +def C90_Z : R600Reg <"C90.Z">; +def C90_W : R600Reg <"C90.W">; +def C91_X : R600Reg <"C91.X">; +def C91_Y : R600Reg <"C91.Y">; +def C91_Z : R600Reg <"C91.Z">; +def C91_W : R600Reg <"C91.W">; +def C92_X : R600Reg <"C92.X">; +def C92_Y : R600Reg <"C92.Y">; +def C92_Z : R600Reg <"C92.Z">; +def C92_W : R600Reg <"C92.W">; +def C93_X : R600Reg <"C93.X">; +def C93_Y : R600Reg <"C93.Y">; +def C93_Z : R600Reg <"C93.Z">; +def C93_W : R600Reg <"C93.W">; +def C94_X : R600Reg <"C94.X">; +def C94_Y : R600Reg <"C94.Y">; +def C94_Z : R600Reg <"C94.Z">; +def C94_W : R600Reg <"C94.W">; +def C95_X : R600Reg <"C95.X">; +def C95_Y : R600Reg <"C95.Y">; +def C95_Z : R600Reg <"C95.Z">; +def C95_W : R600Reg <"C95.W">; +def C96_X : R600Reg <"C96.X">; +def C96_Y : R600Reg <"C96.Y">; +def C96_Z : R600Reg <"C96.Z">; +def C96_W : R600Reg <"C96.W">; +def C97_X : R600Reg <"C97.X">; +def C97_Y : R600Reg <"C97.Y">; +def C97_Z : R600Reg <"C97.Z">; +def C97_W : R600Reg <"C97.W">; +def C98_X : R600Reg <"C98.X">; +def C98_Y : R600Reg <"C98.Y">; +def C98_Z : R600Reg <"C98.Z">; +def C98_W : R600Reg <"C98.W">; +def C99_X : R600Reg <"C99.X">; +def C99_Y : R600Reg <"C99.Y">; +def C99_Z : R600Reg <"C99.Z">; +def C99_W : R600Reg <"C99.W">; +def C100_X : R600Reg <"C100.X">; +def C100_Y : R600Reg <"C100.Y">; +def C100_Z : R600Reg <"C100.Z">; +def C100_W : R600Reg <"C100.W">; +def C101_X : R600Reg <"C101.X">; +def C101_Y : R600Reg <"C101.Y">; +def C101_Z : R600Reg <"C101.Z">; +def C101_W : R600Reg <"C101.W">; +def C102_X : R600Reg <"C102.X">; +def C102_Y : R600Reg <"C102.Y">; +def C102_Z : R600Reg <"C102.Z">; +def C102_W : R600Reg <"C102.W">; +def C103_X : R600Reg <"C103.X">; +def C103_Y : R600Reg <"C103.Y">; +def C103_Z : R600Reg <"C103.Z">; +def C103_W : R600Reg <"C103.W">; +def C104_X : R600Reg <"C104.X">; +def C104_Y : R600Reg <"C104.Y">; +def C104_Z : R600Reg <"C104.Z">; +def C104_W : R600Reg <"C104.W">; +def C105_X : R600Reg <"C105.X">; +def C105_Y : R600Reg <"C105.Y">; +def C105_Z : R600Reg <"C105.Z">; +def C105_W : R600Reg <"C105.W">; +def C106_X : R600Reg <"C106.X">; +def C106_Y : R600Reg <"C106.Y">; +def C106_Z : R600Reg <"C106.Z">; +def C106_W : R600Reg <"C106.W">; +def C107_X : R600Reg <"C107.X">; +def C107_Y : R600Reg <"C107.Y">; +def C107_Z : R600Reg <"C107.Z">; +def C107_W : R600Reg <"C107.W">; +def C108_X : R600Reg <"C108.X">; +def C108_Y : R600Reg <"C108.Y">; +def C108_Z : R600Reg <"C108.Z">; +def C108_W : R600Reg <"C108.W">; +def C109_X : R600Reg <"C109.X">; +def C109_Y : R600Reg <"C109.Y">; +def C109_Z : R600Reg <"C109.Z">; +def C109_W : R600Reg <"C109.W">; +def C110_X : R600Reg <"C110.X">; +def C110_Y : R600Reg <"C110.Y">; +def C110_Z : R600Reg <"C110.Z">; +def C110_W : R600Reg <"C110.W">; +def C111_X : R600Reg <"C111.X">; +def C111_Y : R600Reg <"C111.Y">; +def C111_Z : R600Reg <"C111.Z">; +def C111_W : R600Reg <"C111.W">; +def C112_X : R600Reg <"C112.X">; +def C112_Y : R600Reg <"C112.Y">; +def C112_Z : R600Reg <"C112.Z">; +def C112_W : R600Reg <"C112.W">; +def C113_X : R600Reg <"C113.X">; +def C113_Y : R600Reg <"C113.Y">; +def C113_Z : R600Reg <"C113.Z">; +def C113_W : R600Reg <"C113.W">; +def C114_X : R600Reg <"C114.X">; +def C114_Y : R600Reg <"C114.Y">; +def C114_Z : R600Reg <"C114.Z">; +def C114_W : R600Reg <"C114.W">; +def C115_X : R600Reg <"C115.X">; +def C115_Y : R600Reg <"C115.Y">; +def C115_Z : R600Reg <"C115.Z">; +def C115_W : R600Reg <"C115.W">; +def C116_X : R600Reg <"C116.X">; +def C116_Y : R600Reg <"C116.Y">; +def C116_Z : R600Reg <"C116.Z">; +def C116_W : R600Reg <"C116.W">; +def C117_X : R600Reg <"C117.X">; +def C117_Y : R600Reg <"C117.Y">; +def C117_Z : R600Reg <"C117.Z">; +def C117_W : R600Reg <"C117.W">; +def C118_X : R600Reg <"C118.X">; +def C118_Y : R600Reg <"C118.Y">; +def C118_Z : R600Reg <"C118.Z">; +def C118_W : R600Reg <"C118.W">; +def C119_X : R600Reg <"C119.X">; +def C119_Y : R600Reg <"C119.Y">; +def C119_Z : R600Reg <"C119.Z">; +def C119_W : R600Reg <"C119.W">; +def C120_X : R600Reg <"C120.X">; +def C120_Y : R600Reg <"C120.Y">; +def C120_Z : R600Reg <"C120.Z">; +def C120_W : R600Reg <"C120.W">; +def C121_X : R600Reg <"C121.X">; +def C121_Y : R600Reg <"C121.Y">; +def C121_Z : R600Reg <"C121.Z">; +def C121_W : R600Reg <"C121.W">; +def C122_X : R600Reg <"C122.X">; +def C122_Y : R600Reg <"C122.Y">; +def C122_Z : R600Reg <"C122.Z">; +def C122_W : R600Reg <"C122.W">; +def C123_X : R600Reg <"C123.X">; +def C123_Y : R600Reg <"C123.Y">; +def C123_Z : R600Reg <"C123.Z">; +def C123_W : R600Reg <"C123.W">; +def C124_X : R600Reg <"C124.X">; +def C124_Y : R600Reg <"C124.Y">; +def C124_Z : R600Reg <"C124.Z">; +def C124_W : R600Reg <"C124.W">; +def C125_X : R600Reg <"C125.X">; +def C125_Y : R600Reg <"C125.Y">; +def C125_Z : R600Reg <"C125.Z">; +def C125_W : R600Reg <"C125.W">; +def C126_X : R600Reg <"C126.X">; +def C126_Y : R600Reg <"C126.Y">; +def C126_Z : R600Reg <"C126.Z">; +def C126_W : R600Reg <"C126.W">; +def C127_X : R600Reg <"C127.X">; +def C127_Y : R600Reg <"C127.Y">; +def C127_Z : R600Reg <"C127.Z">; +def C127_W : R600Reg <"C127.W">; +def C128_X : R600Reg <"C128.X">; +def C128_Y : R600Reg <"C128.Y">; +def C128_Z : R600Reg <"C128.Z">; +def C128_W : R600Reg <"C128.W">; +def C129_X : R600Reg <"C129.X">; +def C129_Y : R600Reg <"C129.Y">; +def C129_Z : R600Reg <"C129.Z">; +def C129_W : R600Reg <"C129.W">; +def C130_X : R600Reg <"C130.X">; +def C130_Y : R600Reg <"C130.Y">; +def C130_Z : R600Reg <"C130.Z">; +def C130_W : R600Reg <"C130.W">; +def C131_X : R600Reg <"C131.X">; +def C131_Y : R600Reg <"C131.Y">; +def C131_Z : R600Reg <"C131.Z">; +def C131_W : R600Reg <"C131.W">; +def C132_X : R600Reg <"C132.X">; +def C132_Y : R600Reg <"C132.Y">; +def C132_Z : R600Reg <"C132.Z">; +def C132_W : R600Reg <"C132.W">; +def C133_X : R600Reg <"C133.X">; +def C133_Y : R600Reg <"C133.Y">; +def C133_Z : R600Reg <"C133.Z">; +def C133_W : R600Reg <"C133.W">; +def C134_X : R600Reg <"C134.X">; +def C134_Y : R600Reg <"C134.Y">; +def C134_Z : R600Reg <"C134.Z">; +def C134_W : R600Reg <"C134.W">; +def C135_X : R600Reg <"C135.X">; +def C135_Y : R600Reg <"C135.Y">; +def C135_Z : R600Reg <"C135.Z">; +def C135_W : R600Reg <"C135.W">; +def C136_X : R600Reg <"C136.X">; +def C136_Y : R600Reg <"C136.Y">; +def C136_Z : R600Reg <"C136.Z">; +def C136_W : R600Reg <"C136.W">; +def C137_X : R600Reg <"C137.X">; +def C137_Y : R600Reg <"C137.Y">; +def C137_Z : R600Reg <"C137.Z">; +def C137_W : R600Reg <"C137.W">; +def C138_X : R600Reg <"C138.X">; +def C138_Y : R600Reg <"C138.Y">; +def C138_Z : R600Reg <"C138.Z">; +def C138_W : R600Reg <"C138.W">; +def C139_X : R600Reg <"C139.X">; +def C139_Y : R600Reg <"C139.Y">; +def C139_Z : R600Reg <"C139.Z">; +def C139_W : R600Reg <"C139.W">; +def C140_X : R600Reg <"C140.X">; +def C140_Y : R600Reg <"C140.Y">; +def C140_Z : R600Reg <"C140.Z">; +def C140_W : R600Reg <"C140.W">; +def C141_X : R600Reg <"C141.X">; +def C141_Y : R600Reg <"C141.Y">; +def C141_Z : R600Reg <"C141.Z">; +def C141_W : R600Reg <"C141.W">; +def C142_X : R600Reg <"C142.X">; +def C142_Y : R600Reg <"C142.Y">; +def C142_Z : R600Reg <"C142.Z">; +def C142_W : R600Reg <"C142.W">; +def C143_X : R600Reg <"C143.X">; +def C143_Y : R600Reg <"C143.Y">; +def C143_Z : R600Reg <"C143.Z">; +def C143_W : R600Reg <"C143.W">; +def C144_X : R600Reg <"C144.X">; +def C144_Y : R600Reg <"C144.Y">; +def C144_Z : R600Reg <"C144.Z">; +def C144_W : R600Reg <"C144.W">; +def C145_X : R600Reg <"C145.X">; +def C145_Y : R600Reg <"C145.Y">; +def C145_Z : R600Reg <"C145.Z">; +def C145_W : R600Reg <"C145.W">; +def C146_X : R600Reg <"C146.X">; +def C146_Y : R600Reg <"C146.Y">; +def C146_Z : R600Reg <"C146.Z">; +def C146_W : R600Reg <"C146.W">; +def C147_X : R600Reg <"C147.X">; +def C147_Y : R600Reg <"C147.Y">; +def C147_Z : R600Reg <"C147.Z">; +def C147_W : R600Reg <"C147.W">; +def C148_X : R600Reg <"C148.X">; +def C148_Y : R600Reg <"C148.Y">; +def C148_Z : R600Reg <"C148.Z">; +def C148_W : R600Reg <"C148.W">; +def C149_X : R600Reg <"C149.X">; +def C149_Y : R600Reg <"C149.Y">; +def C149_Z : R600Reg <"C149.Z">; +def C149_W : R600Reg <"C149.W">; +def C150_X : R600Reg <"C150.X">; +def C150_Y : R600Reg <"C150.Y">; +def C150_Z : R600Reg <"C150.Z">; +def C150_W : R600Reg <"C150.W">; +def C151_X : R600Reg <"C151.X">; +def C151_Y : R600Reg <"C151.Y">; +def C151_Z : R600Reg <"C151.Z">; +def C151_W : R600Reg <"C151.W">; +def C152_X : R600Reg <"C152.X">; +def C152_Y : R600Reg <"C152.Y">; +def C152_Z : R600Reg <"C152.Z">; +def C152_W : R600Reg <"C152.W">; +def C153_X : R600Reg <"C153.X">; +def C153_Y : R600Reg <"C153.Y">; +def C153_Z : R600Reg <"C153.Z">; +def C153_W : R600Reg <"C153.W">; +def C154_X : R600Reg <"C154.X">; +def C154_Y : R600Reg <"C154.Y">; +def C154_Z : R600Reg <"C154.Z">; +def C154_W : R600Reg <"C154.W">; +def C155_X : R600Reg <"C155.X">; +def C155_Y : R600Reg <"C155.Y">; +def C155_Z : R600Reg <"C155.Z">; +def C155_W : R600Reg <"C155.W">; +def C156_X : R600Reg <"C156.X">; +def C156_Y : R600Reg <"C156.Y">; +def C156_Z : R600Reg <"C156.Z">; +def C156_W : R600Reg <"C156.W">; +def C157_X : R600Reg <"C157.X">; +def C157_Y : R600Reg <"C157.Y">; +def C157_Z : R600Reg <"C157.Z">; +def C157_W : R600Reg <"C157.W">; +def C158_X : R600Reg <"C158.X">; +def C158_Y : R600Reg <"C158.Y">; +def C158_Z : R600Reg <"C158.Z">; +def C158_W : R600Reg <"C158.W">; +def C159_X : R600Reg <"C159.X">; +def C159_Y : R600Reg <"C159.Y">; +def C159_Z : R600Reg <"C159.Z">; +def C159_W : R600Reg <"C159.W">; +def C160_X : R600Reg <"C160.X">; +def C160_Y : R600Reg <"C160.Y">; +def C160_Z : R600Reg <"C160.Z">; +def C160_W : R600Reg <"C160.W">; +def C161_X : R600Reg <"C161.X">; +def C161_Y : R600Reg <"C161.Y">; +def C161_Z : R600Reg <"C161.Z">; +def C161_W : R600Reg <"C161.W">; +def C162_X : R600Reg <"C162.X">; +def C162_Y : R600Reg <"C162.Y">; +def C162_Z : R600Reg <"C162.Z">; +def C162_W : R600Reg <"C162.W">; +def C163_X : R600Reg <"C163.X">; +def C163_Y : R600Reg <"C163.Y">; +def C163_Z : R600Reg <"C163.Z">; +def C163_W : R600Reg <"C163.W">; +def C164_X : R600Reg <"C164.X">; +def C164_Y : R600Reg <"C164.Y">; +def C164_Z : R600Reg <"C164.Z">; +def C164_W : R600Reg <"C164.W">; +def C165_X : R600Reg <"C165.X">; +def C165_Y : R600Reg <"C165.Y">; +def C165_Z : R600Reg <"C165.Z">; +def C165_W : R600Reg <"C165.W">; +def C166_X : R600Reg <"C166.X">; +def C166_Y : R600Reg <"C166.Y">; +def C166_Z : R600Reg <"C166.Z">; +def C166_W : R600Reg <"C166.W">; +def C167_X : R600Reg <"C167.X">; +def C167_Y : R600Reg <"C167.Y">; +def C167_Z : R600Reg <"C167.Z">; +def C167_W : R600Reg <"C167.W">; +def C168_X : R600Reg <"C168.X">; +def C168_Y : R600Reg <"C168.Y">; +def C168_Z : R600Reg <"C168.Z">; +def C168_W : R600Reg <"C168.W">; +def C169_X : R600Reg <"C169.X">; +def C169_Y : R600Reg <"C169.Y">; +def C169_Z : R600Reg <"C169.Z">; +def C169_W : R600Reg <"C169.W">; +def C170_X : R600Reg <"C170.X">; +def C170_Y : R600Reg <"C170.Y">; +def C170_Z : R600Reg <"C170.Z">; +def C170_W : R600Reg <"C170.W">; +def C171_X : R600Reg <"C171.X">; +def C171_Y : R600Reg <"C171.Y">; +def C171_Z : R600Reg <"C171.Z">; +def C171_W : R600Reg <"C171.W">; +def C172_X : R600Reg <"C172.X">; +def C172_Y : R600Reg <"C172.Y">; +def C172_Z : R600Reg <"C172.Z">; +def C172_W : R600Reg <"C172.W">; +def C173_X : R600Reg <"C173.X">; +def C173_Y : R600Reg <"C173.Y">; +def C173_Z : R600Reg <"C173.Z">; +def C173_W : R600Reg <"C173.W">; +def C174_X : R600Reg <"C174.X">; +def C174_Y : R600Reg <"C174.Y">; +def C174_Z : R600Reg <"C174.Z">; +def C174_W : R600Reg <"C174.W">; +def C175_X : R600Reg <"C175.X">; +def C175_Y : R600Reg <"C175.Y">; +def C175_Z : R600Reg <"C175.Z">; +def C175_W : R600Reg <"C175.W">; +def C176_X : R600Reg <"C176.X">; +def C176_Y : R600Reg <"C176.Y">; +def C176_Z : R600Reg <"C176.Z">; +def C176_W : R600Reg <"C176.W">; +def C177_X : R600Reg <"C177.X">; +def C177_Y : R600Reg <"C177.Y">; +def C177_Z : R600Reg <"C177.Z">; +def C177_W : R600Reg <"C177.W">; +def C178_X : R600Reg <"C178.X">; +def C178_Y : R600Reg <"C178.Y">; +def C178_Z : R600Reg <"C178.Z">; +def C178_W : R600Reg <"C178.W">; +def C179_X : R600Reg <"C179.X">; +def C179_Y : R600Reg <"C179.Y">; +def C179_Z : R600Reg <"C179.Z">; +def C179_W : R600Reg <"C179.W">; +def C180_X : R600Reg <"C180.X">; +def C180_Y : R600Reg <"C180.Y">; +def C180_Z : R600Reg <"C180.Z">; +def C180_W : R600Reg <"C180.W">; +def C181_X : R600Reg <"C181.X">; +def C181_Y : R600Reg <"C181.Y">; +def C181_Z : R600Reg <"C181.Z">; +def C181_W : R600Reg <"C181.W">; +def C182_X : R600Reg <"C182.X">; +def C182_Y : R600Reg <"C182.Y">; +def C182_Z : R600Reg <"C182.Z">; +def C182_W : R600Reg <"C182.W">; +def C183_X : R600Reg <"C183.X">; +def C183_Y : R600Reg <"C183.Y">; +def C183_Z : R600Reg <"C183.Z">; +def C183_W : R600Reg <"C183.W">; +def C184_X : R600Reg <"C184.X">; +def C184_Y : R600Reg <"C184.Y">; +def C184_Z : R600Reg <"C184.Z">; +def C184_W : R600Reg <"C184.W">; +def C185_X : R600Reg <"C185.X">; +def C185_Y : R600Reg <"C185.Y">; +def C185_Z : R600Reg <"C185.Z">; +def C185_W : R600Reg <"C185.W">; +def C186_X : R600Reg <"C186.X">; +def C186_Y : R600Reg <"C186.Y">; +def C186_Z : R600Reg <"C186.Z">; +def C186_W : R600Reg <"C186.W">; +def C187_X : R600Reg <"C187.X">; +def C187_Y : R600Reg <"C187.Y">; +def C187_Z : R600Reg <"C187.Z">; +def C187_W : R600Reg <"C187.W">; +def C188_X : R600Reg <"C188.X">; +def C188_Y : R600Reg <"C188.Y">; +def C188_Z : R600Reg <"C188.Z">; +def C188_W : R600Reg <"C188.W">; +def C189_X : R600Reg <"C189.X">; +def C189_Y : R600Reg <"C189.Y">; +def C189_Z : R600Reg <"C189.Z">; +def C189_W : R600Reg <"C189.W">; +def C190_X : R600Reg <"C190.X">; +def C190_Y : R600Reg <"C190.Y">; +def C190_Z : R600Reg <"C190.Z">; +def C190_W : R600Reg <"C190.W">; +def C191_X : R600Reg <"C191.X">; +def C191_Y : R600Reg <"C191.Y">; +def C191_Z : R600Reg <"C191.Z">; +def C191_W : R600Reg <"C191.W">; +def C192_X : R600Reg <"C192.X">; +def C192_Y : R600Reg <"C192.Y">; +def C192_Z : R600Reg <"C192.Z">; +def C192_W : R600Reg <"C192.W">; +def C193_X : R600Reg <"C193.X">; +def C193_Y : R600Reg <"C193.Y">; +def C193_Z : R600Reg <"C193.Z">; +def C193_W : R600Reg <"C193.W">; +def C194_X : R600Reg <"C194.X">; +def C194_Y : R600Reg <"C194.Y">; +def C194_Z : R600Reg <"C194.Z">; +def C194_W : R600Reg <"C194.W">; +def C195_X : R600Reg <"C195.X">; +def C195_Y : R600Reg <"C195.Y">; +def C195_Z : R600Reg <"C195.Z">; +def C195_W : R600Reg <"C195.W">; +def C196_X : R600Reg <"C196.X">; +def C196_Y : R600Reg <"C196.Y">; +def C196_Z : R600Reg <"C196.Z">; +def C196_W : R600Reg <"C196.W">; +def C197_X : R600Reg <"C197.X">; +def C197_Y : R600Reg <"C197.Y">; +def C197_Z : R600Reg <"C197.Z">; +def C197_W : R600Reg <"C197.W">; +def C198_X : R600Reg <"C198.X">; +def C198_Y : R600Reg <"C198.Y">; +def C198_Z : R600Reg <"C198.Z">; +def C198_W : R600Reg <"C198.W">; +def C199_X : R600Reg <"C199.X">; +def C199_Y : R600Reg <"C199.Y">; +def C199_Z : R600Reg <"C199.Z">; +def C199_W : R600Reg <"C199.W">; +def C200_X : R600Reg <"C200.X">; +def C200_Y : R600Reg <"C200.Y">; +def C200_Z : R600Reg <"C200.Z">; +def C200_W : R600Reg <"C200.W">; +def C201_X : R600Reg <"C201.X">; +def C201_Y : R600Reg <"C201.Y">; +def C201_Z : R600Reg <"C201.Z">; +def C201_W : R600Reg <"C201.W">; +def C202_X : R600Reg <"C202.X">; +def C202_Y : R600Reg <"C202.Y">; +def C202_Z : R600Reg <"C202.Z">; +def C202_W : R600Reg <"C202.W">; +def C203_X : R600Reg <"C203.X">; +def C203_Y : R600Reg <"C203.Y">; +def C203_Z : R600Reg <"C203.Z">; +def C203_W : R600Reg <"C203.W">; +def C204_X : R600Reg <"C204.X">; +def C204_Y : R600Reg <"C204.Y">; +def C204_Z : R600Reg <"C204.Z">; +def C204_W : R600Reg <"C204.W">; +def C205_X : R600Reg <"C205.X">; +def C205_Y : R600Reg <"C205.Y">; +def C205_Z : R600Reg <"C205.Z">; +def C205_W : R600Reg <"C205.W">; +def C206_X : R600Reg <"C206.X">; +def C206_Y : R600Reg <"C206.Y">; +def C206_Z : R600Reg <"C206.Z">; +def C206_W : R600Reg <"C206.W">; +def C207_X : R600Reg <"C207.X">; +def C207_Y : R600Reg <"C207.Y">; +def C207_Z : R600Reg <"C207.Z">; +def C207_W : R600Reg <"C207.W">; +def C208_X : R600Reg <"C208.X">; +def C208_Y : R600Reg <"C208.Y">; +def C208_Z : R600Reg <"C208.Z">; +def C208_W : R600Reg <"C208.W">; +def C209_X : R600Reg <"C209.X">; +def C209_Y : R600Reg <"C209.Y">; +def C209_Z : R600Reg <"C209.Z">; +def C209_W : R600Reg <"C209.W">; +def C210_X : R600Reg <"C210.X">; +def C210_Y : R600Reg <"C210.Y">; +def C210_Z : R600Reg <"C210.Z">; +def C210_W : R600Reg <"C210.W">; +def C211_X : R600Reg <"C211.X">; +def C211_Y : R600Reg <"C211.Y">; +def C211_Z : R600Reg <"C211.Z">; +def C211_W : R600Reg <"C211.W">; +def C212_X : R600Reg <"C212.X">; +def C212_Y : R600Reg <"C212.Y">; +def C212_Z : R600Reg <"C212.Z">; +def C212_W : R600Reg <"C212.W">; +def C213_X : R600Reg <"C213.X">; +def C213_Y : R600Reg <"C213.Y">; +def C213_Z : R600Reg <"C213.Z">; +def C213_W : R600Reg <"C213.W">; +def C214_X : R600Reg <"C214.X">; +def C214_Y : R600Reg <"C214.Y">; +def C214_Z : R600Reg <"C214.Z">; +def C214_W : R600Reg <"C214.W">; +def C215_X : R600Reg <"C215.X">; +def C215_Y : R600Reg <"C215.Y">; +def C215_Z : R600Reg <"C215.Z">; +def C215_W : R600Reg <"C215.W">; +def C216_X : R600Reg <"C216.X">; +def C216_Y : R600Reg <"C216.Y">; +def C216_Z : R600Reg <"C216.Z">; +def C216_W : R600Reg <"C216.W">; +def C217_X : R600Reg <"C217.X">; +def C217_Y : R600Reg <"C217.Y">; +def C217_Z : R600Reg <"C217.Z">; +def C217_W : R600Reg <"C217.W">; +def C218_X : R600Reg <"C218.X">; +def C218_Y : R600Reg <"C218.Y">; +def C218_Z : R600Reg <"C218.Z">; +def C218_W : R600Reg <"C218.W">; +def C219_X : R600Reg <"C219.X">; +def C219_Y : R600Reg <"C219.Y">; +def C219_Z : R600Reg <"C219.Z">; +def C219_W : R600Reg <"C219.W">; +def C220_X : R600Reg <"C220.X">; +def C220_Y : R600Reg <"C220.Y">; +def C220_Z : R600Reg <"C220.Z">; +def C220_W : R600Reg <"C220.W">; +def C221_X : R600Reg <"C221.X">; +def C221_Y : R600Reg <"C221.Y">; +def C221_Z : R600Reg <"C221.Z">; +def C221_W : R600Reg <"C221.W">; +def C222_X : R600Reg <"C222.X">; +def C222_Y : R600Reg <"C222.Y">; +def C222_Z : R600Reg <"C222.Z">; +def C222_W : R600Reg <"C222.W">; +def C223_X : R600Reg <"C223.X">; +def C223_Y : R600Reg <"C223.Y">; +def C223_Z : R600Reg <"C223.Z">; +def C223_W : R600Reg <"C223.W">; +def C224_X : R600Reg <"C224.X">; +def C224_Y : R600Reg <"C224.Y">; +def C224_Z : R600Reg <"C224.Z">; +def C224_W : R600Reg <"C224.W">; +def C225_X : R600Reg <"C225.X">; +def C225_Y : R600Reg <"C225.Y">; +def C225_Z : R600Reg <"C225.Z">; +def C225_W : R600Reg <"C225.W">; +def C226_X : R600Reg <"C226.X">; +def C226_Y : R600Reg <"C226.Y">; +def C226_Z : R600Reg <"C226.Z">; +def C226_W : R600Reg <"C226.W">; +def C227_X : R600Reg <"C227.X">; +def C227_Y : R600Reg <"C227.Y">; +def C227_Z : R600Reg <"C227.Z">; +def C227_W : R600Reg <"C227.W">; +def C228_X : R600Reg <"C228.X">; +def C228_Y : R600Reg <"C228.Y">; +def C228_Z : R600Reg <"C228.Z">; +def C228_W : R600Reg <"C228.W">; +def C229_X : R600Reg <"C229.X">; +def C229_Y : R600Reg <"C229.Y">; +def C229_Z : R600Reg <"C229.Z">; +def C229_W : R600Reg <"C229.W">; +def C230_X : R600Reg <"C230.X">; +def C230_Y : R600Reg <"C230.Y">; +def C230_Z : R600Reg <"C230.Z">; +def C230_W : R600Reg <"C230.W">; +def C231_X : R600Reg <"C231.X">; +def C231_Y : R600Reg <"C231.Y">; +def C231_Z : R600Reg <"C231.Z">; +def C231_W : R600Reg <"C231.W">; +def C232_X : R600Reg <"C232.X">; +def C232_Y : R600Reg <"C232.Y">; +def C232_Z : R600Reg <"C232.Z">; +def C232_W : R600Reg <"C232.W">; +def C233_X : R600Reg <"C233.X">; +def C233_Y : R600Reg <"C233.Y">; +def C233_Z : R600Reg <"C233.Z">; +def C233_W : R600Reg <"C233.W">; +def C234_X : R600Reg <"C234.X">; +def C234_Y : R600Reg <"C234.Y">; +def C234_Z : R600Reg <"C234.Z">; +def C234_W : R600Reg <"C234.W">; +def C235_X : R600Reg <"C235.X">; +def C235_Y : R600Reg <"C235.Y">; +def C235_Z : R600Reg <"C235.Z">; +def C235_W : R600Reg <"C235.W">; +def C236_X : R600Reg <"C236.X">; +def C236_Y : R600Reg <"C236.Y">; +def C236_Z : R600Reg <"C236.Z">; +def C236_W : R600Reg <"C236.W">; +def C237_X : R600Reg <"C237.X">; +def C237_Y : R600Reg <"C237.Y">; +def C237_Z : R600Reg <"C237.Z">; +def C237_W : R600Reg <"C237.W">; +def C238_X : R600Reg <"C238.X">; +def C238_Y : R600Reg <"C238.Y">; +def C238_Z : R600Reg <"C238.Z">; +def C238_W : R600Reg <"C238.W">; +def C239_X : R600Reg <"C239.X">; +def C239_Y : R600Reg <"C239.Y">; +def C239_Z : R600Reg <"C239.Z">; +def C239_W : R600Reg <"C239.W">; +def C240_X : R600Reg <"C240.X">; +def C240_Y : R600Reg <"C240.Y">; +def C240_Z : R600Reg <"C240.Z">; +def C240_W : R600Reg <"C240.W">; +def C241_X : R600Reg <"C241.X">; +def C241_Y : R600Reg <"C241.Y">; +def C241_Z : R600Reg <"C241.Z">; +def C241_W : R600Reg <"C241.W">; +def C242_X : R600Reg <"C242.X">; +def C242_Y : R600Reg <"C242.Y">; +def C242_Z : R600Reg <"C242.Z">; +def C242_W : R600Reg <"C242.W">; +def C243_X : R600Reg <"C243.X">; +def C243_Y : R600Reg <"C243.Y">; +def C243_Z : R600Reg <"C243.Z">; +def C243_W : R600Reg <"C243.W">; +def C244_X : R600Reg <"C244.X">; +def C244_Y : R600Reg <"C244.Y">; +def C244_Z : R600Reg <"C244.Z">; +def C244_W : R600Reg <"C244.W">; +def C245_X : R600Reg <"C245.X">; +def C245_Y : R600Reg <"C245.Y">; +def C245_Z : R600Reg <"C245.Z">; +def C245_W : R600Reg <"C245.W">; +def C246_X : R600Reg <"C246.X">; +def C246_Y : R600Reg <"C246.Y">; +def C246_Z : R600Reg <"C246.Z">; +def C246_W : R600Reg <"C246.W">; +def C247_X : R600Reg <"C247.X">; +def C247_Y : R600Reg <"C247.Y">; +def C247_Z : R600Reg <"C247.Z">; +def C247_W : R600Reg <"C247.W">; +def C248_X : R600Reg <"C248.X">; +def C248_Y : R600Reg <"C248.Y">; +def C248_Z : R600Reg <"C248.Z">; +def C248_W : R600Reg <"C248.W">; +def C249_X : R600Reg <"C249.X">; +def C249_Y : R600Reg <"C249.Y">; +def C249_Z : R600Reg <"C249.Z">; +def C249_W : R600Reg <"C249.W">; +def C250_X : R600Reg <"C250.X">; +def C250_Y : R600Reg <"C250.Y">; +def C250_Z : R600Reg <"C250.Z">; +def C250_W : R600Reg <"C250.W">; +def C251_X : R600Reg <"C251.X">; +def C251_Y : R600Reg <"C251.Y">; +def C251_Z : R600Reg <"C251.Z">; +def C251_W : R600Reg <"C251.W">; +def C252_X : R600Reg <"C252.X">; +def C252_Y : R600Reg <"C252.Y">; +def C252_Z : R600Reg <"C252.Z">; +def C252_W : R600Reg <"C252.W">; +def C253_X : R600Reg <"C253.X">; +def C253_Y : R600Reg <"C253.Y">; +def C253_Z : R600Reg <"C253.Z">; +def C253_W : R600Reg <"C253.W">; +def C254_X : R600Reg <"C254.X">; +def C254_Y : R600Reg <"C254.Y">; +def C254_Z : R600Reg <"C254.Z">; +def C254_W : R600Reg <"C254.W">; +def C255_X : R600Reg <"C255.X">; +def C255_Y : R600Reg <"C255.Y">; +def C255_Z : R600Reg <"C255.Z">; +def C255_W : R600Reg <"C255.W">; +def T0_X : R600Reg <"T0.X">; +def T0_Y : R600Reg <"T0.Y">; +def T0_Z : R600Reg <"T0.Z">; +def T0_W : R600Reg <"T0.W">; +def T1_X : R600Reg <"T1.X">; +def T1_Y : R600Reg <"T1.Y">; +def T1_Z : R600Reg <"T1.Z">; +def T1_W : R600Reg <"T1.W">; +def T2_X : R600Reg <"T2.X">; +def T2_Y : R600Reg <"T2.Y">; +def T2_Z : R600Reg <"T2.Z">; +def T2_W : R600Reg <"T2.W">; +def T3_X : R600Reg <"T3.X">; +def T3_Y : R600Reg <"T3.Y">; +def T3_Z : R600Reg <"T3.Z">; +def T3_W : R600Reg <"T3.W">; +def T4_X : R600Reg <"T4.X">; +def T4_Y : R600Reg <"T4.Y">; +def T4_Z : R600Reg <"T4.Z">; +def T4_W : R600Reg <"T4.W">; +def T5_X : R600Reg <"T5.X">; +def T5_Y : R600Reg <"T5.Y">; +def T5_Z : R600Reg <"T5.Z">; +def T5_W : R600Reg <"T5.W">; +def T6_X : R600Reg <"T6.X">; +def T6_Y : R600Reg <"T6.Y">; +def T6_Z : R600Reg <"T6.Z">; +def T6_W : R600Reg <"T6.W">; +def T7_X : R600Reg <"T7.X">; +def T7_Y : R600Reg <"T7.Y">; +def T7_Z : R600Reg <"T7.Z">; +def T7_W : R600Reg <"T7.W">; +def T8_X : R600Reg <"T8.X">; +def T8_Y : R600Reg <"T8.Y">; +def T8_Z : R600Reg <"T8.Z">; +def T8_W : R600Reg <"T8.W">; +def T9_X : R600Reg <"T9.X">; +def T9_Y : R600Reg <"T9.Y">; +def T9_Z : R600Reg <"T9.Z">; +def T9_W : R600Reg <"T9.W">; +def T10_X : R600Reg <"T10.X">; +def T10_Y : R600Reg <"T10.Y">; +def T10_Z : R600Reg <"T10.Z">; +def T10_W : R600Reg <"T10.W">; +def T11_X : R600Reg <"T11.X">; +def T11_Y : R600Reg <"T11.Y">; +def T11_Z : R600Reg <"T11.Z">; +def T11_W : R600Reg <"T11.W">; +def T12_X : R600Reg <"T12.X">; +def T12_Y : R600Reg <"T12.Y">; +def T12_Z : R600Reg <"T12.Z">; +def T12_W : R600Reg <"T12.W">; +def T13_X : R600Reg <"T13.X">; +def T13_Y : R600Reg <"T13.Y">; +def T13_Z : R600Reg <"T13.Z">; +def T13_W : R600Reg <"T13.W">; +def T14_X : R600Reg <"T14.X">; +def T14_Y : R600Reg <"T14.Y">; +def T14_Z : R600Reg <"T14.Z">; +def T14_W : R600Reg <"T14.W">; +def T15_X : R600Reg <"T15.X">; +def T15_Y : R600Reg <"T15.Y">; +def T15_Z : R600Reg <"T15.Z">; +def T15_W : R600Reg <"T15.W">; +def T16_X : R600Reg <"T16.X">; +def T16_Y : R600Reg <"T16.Y">; +def T16_Z : R600Reg <"T16.Z">; +def T16_W : R600Reg <"T16.W">; +def T17_X : R600Reg <"T17.X">; +def T17_Y : R600Reg <"T17.Y">; +def T17_Z : R600Reg <"T17.Z">; +def T17_W : R600Reg <"T17.W">; +def T18_X : R600Reg <"T18.X">; +def T18_Y : R600Reg <"T18.Y">; +def T18_Z : R600Reg <"T18.Z">; +def T18_W : R600Reg <"T18.W">; +def T19_X : R600Reg <"T19.X">; +def T19_Y : R600Reg <"T19.Y">; +def T19_Z : R600Reg <"T19.Z">; +def T19_W : R600Reg <"T19.W">; +def T20_X : R600Reg <"T20.X">; +def T20_Y : R600Reg <"T20.Y">; +def T20_Z : R600Reg <"T20.Z">; +def T20_W : R600Reg <"T20.W">; +def T21_X : R600Reg <"T21.X">; +def T21_Y : R600Reg <"T21.Y">; +def T21_Z : R600Reg <"T21.Z">; +def T21_W : R600Reg <"T21.W">; +def T22_X : R600Reg <"T22.X">; +def T22_Y : R600Reg <"T22.Y">; +def T22_Z : R600Reg <"T22.Z">; +def T22_W : R600Reg <"T22.W">; +def T23_X : R600Reg <"T23.X">; +def T23_Y : R600Reg <"T23.Y">; +def T23_Z : R600Reg <"T23.Z">; +def T23_W : R600Reg <"T23.W">; +def T24_X : R600Reg <"T24.X">; +def T24_Y : R600Reg <"T24.Y">; +def T24_Z : R600Reg <"T24.Z">; +def T24_W : R600Reg <"T24.W">; +def T25_X : R600Reg <"T25.X">; +def T25_Y : R600Reg <"T25.Y">; +def T25_Z : R600Reg <"T25.Z">; +def T25_W : R600Reg <"T25.W">; +def T26_X : R600Reg <"T26.X">; +def T26_Y : R600Reg <"T26.Y">; +def T26_Z : R600Reg <"T26.Z">; +def T26_W : R600Reg <"T26.W">; +def T27_X : R600Reg <"T27.X">; +def T27_Y : R600Reg <"T27.Y">; +def T27_Z : R600Reg <"T27.Z">; +def T27_W : R600Reg <"T27.W">; +def T28_X : R600Reg <"T28.X">; +def T28_Y : R600Reg <"T28.Y">; +def T28_Z : R600Reg <"T28.Z">; +def T28_W : R600Reg <"T28.W">; +def T29_X : R600Reg <"T29.X">; +def T29_Y : R600Reg <"T29.Y">; +def T29_Z : R600Reg <"T29.Z">; +def T29_W : R600Reg <"T29.W">; +def T30_X : R600Reg <"T30.X">; +def T30_Y : R600Reg <"T30.Y">; +def T30_Z : R600Reg <"T30.Z">; +def T30_W : R600Reg <"T30.W">; +def T31_X : R600Reg <"T31.X">; +def T31_Y : R600Reg <"T31.Y">; +def T31_Z : R600Reg <"T31.Z">; +def T31_W : R600Reg <"T31.W">; +def T32_X : R600Reg <"T32.X">; +def T32_Y : R600Reg <"T32.Y">; +def T32_Z : R600Reg <"T32.Z">; +def T32_W : R600Reg <"T32.W">; +def T33_X : R600Reg <"T33.X">; +def T33_Y : R600Reg <"T33.Y">; +def T33_Z : R600Reg <"T33.Z">; +def T33_W : R600Reg <"T33.W">; +def T34_X : R600Reg <"T34.X">; +def T34_Y : R600Reg <"T34.Y">; +def T34_Z : R600Reg <"T34.Z">; +def T34_W : R600Reg <"T34.W">; +def T35_X : R600Reg <"T35.X">; +def T35_Y : R600Reg <"T35.Y">; +def T35_Z : R600Reg <"T35.Z">; +def T35_W : R600Reg <"T35.W">; +def T36_X : R600Reg <"T36.X">; +def T36_Y : R600Reg <"T36.Y">; +def T36_Z : R600Reg <"T36.Z">; +def T36_W : R600Reg <"T36.W">; +def T37_X : R600Reg <"T37.X">; +def T37_Y : R600Reg <"T37.Y">; +def T37_Z : R600Reg <"T37.Z">; +def T37_W : R600Reg <"T37.W">; +def T38_X : R600Reg <"T38.X">; +def T38_Y : R600Reg <"T38.Y">; +def T38_Z : R600Reg <"T38.Z">; +def T38_W : R600Reg <"T38.W">; +def T39_X : R600Reg <"T39.X">; +def T39_Y : R600Reg <"T39.Y">; +def T39_Z : R600Reg <"T39.Z">; +def T39_W : R600Reg <"T39.W">; +def T40_X : R600Reg <"T40.X">; +def T40_Y : R600Reg <"T40.Y">; +def T40_Z : R600Reg <"T40.Z">; +def T40_W : R600Reg <"T40.W">; +def T41_X : R600Reg <"T41.X">; +def T41_Y : R600Reg <"T41.Y">; +def T41_Z : R600Reg <"T41.Z">; +def T41_W : R600Reg <"T41.W">; +def T42_X : R600Reg <"T42.X">; +def T42_Y : R600Reg <"T42.Y">; +def T42_Z : R600Reg <"T42.Z">; +def T42_W : R600Reg <"T42.W">; +def T43_X : R600Reg <"T43.X">; +def T43_Y : R600Reg <"T43.Y">; +def T43_Z : R600Reg <"T43.Z">; +def T43_W : R600Reg <"T43.W">; +def T44_X : R600Reg <"T44.X">; +def T44_Y : R600Reg <"T44.Y">; +def T44_Z : R600Reg <"T44.Z">; +def T44_W : R600Reg <"T44.W">; +def T45_X : R600Reg <"T45.X">; +def T45_Y : R600Reg <"T45.Y">; +def T45_Z : R600Reg <"T45.Z">; +def T45_W : R600Reg <"T45.W">; +def T46_X : R600Reg <"T46.X">; +def T46_Y : R600Reg <"T46.Y">; +def T46_Z : R600Reg <"T46.Z">; +def T46_W : R600Reg <"T46.W">; +def T47_X : R600Reg <"T47.X">; +def T47_Y : R600Reg <"T47.Y">; +def T47_Z : R600Reg <"T47.Z">; +def T47_W : R600Reg <"T47.W">; +def T48_X : R600Reg <"T48.X">; +def T48_Y : R600Reg <"T48.Y">; +def T48_Z : R600Reg <"T48.Z">; +def T48_W : R600Reg <"T48.W">; +def T49_X : R600Reg <"T49.X">; +def T49_Y : R600Reg <"T49.Y">; +def T49_Z : R600Reg <"T49.Z">; +def T49_W : R600Reg <"T49.W">; +def T50_X : R600Reg <"T50.X">; +def T50_Y : R600Reg <"T50.Y">; +def T50_Z : R600Reg <"T50.Z">; +def T50_W : R600Reg <"T50.W">; +def T51_X : R600Reg <"T51.X">; +def T51_Y : R600Reg <"T51.Y">; +def T51_Z : R600Reg <"T51.Z">; +def T51_W : R600Reg <"T51.W">; +def T52_X : R600Reg <"T52.X">; +def T52_Y : R600Reg <"T52.Y">; +def T52_Z : R600Reg <"T52.Z">; +def T52_W : R600Reg <"T52.W">; +def T53_X : R600Reg <"T53.X">; +def T53_Y : R600Reg <"T53.Y">; +def T53_Z : R600Reg <"T53.Z">; +def T53_W : R600Reg <"T53.W">; +def T54_X : R600Reg <"T54.X">; +def T54_Y : R600Reg <"T54.Y">; +def T54_Z : R600Reg <"T54.Z">; +def T54_W : R600Reg <"T54.W">; +def T55_X : R600Reg <"T55.X">; +def T55_Y : R600Reg <"T55.Y">; +def T55_Z : R600Reg <"T55.Z">; +def T55_W : R600Reg <"T55.W">; +def T56_X : R600Reg <"T56.X">; +def T56_Y : R600Reg <"T56.Y">; +def T56_Z : R600Reg <"T56.Z">; +def T56_W : R600Reg <"T56.W">; +def T57_X : R600Reg <"T57.X">; +def T57_Y : R600Reg <"T57.Y">; +def T57_Z : R600Reg <"T57.Z">; +def T57_W : R600Reg <"T57.W">; +def T58_X : R600Reg <"T58.X">; +def T58_Y : R600Reg <"T58.Y">; +def T58_Z : R600Reg <"T58.Z">; +def T58_W : R600Reg <"T58.W">; +def T59_X : R600Reg <"T59.X">; +def T59_Y : R600Reg <"T59.Y">; +def T59_Z : R600Reg <"T59.Z">; +def T59_W : R600Reg <"T59.W">; +def T60_X : R600Reg <"T60.X">; +def T60_Y : R600Reg <"T60.Y">; +def T60_Z : R600Reg <"T60.Z">; +def T60_W : R600Reg <"T60.W">; +def T61_X : R600Reg <"T61.X">; +def T61_Y : R600Reg <"T61.Y">; +def T61_Z : R600Reg <"T61.Z">; +def T61_W : R600Reg <"T61.W">; +def T62_X : R600Reg <"T62.X">; +def T62_Y : R600Reg <"T62.Y">; +def T62_Z : R600Reg <"T62.Z">; +def T62_W : R600Reg <"T62.W">; +def T63_X : R600Reg <"T63.X">; +def T63_Y : R600Reg <"T63.Y">; +def T63_Z : R600Reg <"T63.Z">; +def T63_W : R600Reg <"T63.W">; +def T64_X : R600Reg <"T64.X">; +def T64_Y : R600Reg <"T64.Y">; +def T64_Z : R600Reg <"T64.Z">; +def T64_W : R600Reg <"T64.W">; +def T65_X : R600Reg <"T65.X">; +def T65_Y : R600Reg <"T65.Y">; +def T65_Z : R600Reg <"T65.Z">; +def T65_W : R600Reg <"T65.W">; +def T66_X : R600Reg <"T66.X">; +def T66_Y : R600Reg <"T66.Y">; +def T66_Z : R600Reg <"T66.Z">; +def T66_W : R600Reg <"T66.W">; +def T67_X : R600Reg <"T67.X">; +def T67_Y : R600Reg <"T67.Y">; +def T67_Z : R600Reg <"T67.Z">; +def T67_W : R600Reg <"T67.W">; +def T68_X : R600Reg <"T68.X">; +def T68_Y : R600Reg <"T68.Y">; +def T68_Z : R600Reg <"T68.Z">; +def T68_W : R600Reg <"T68.W">; +def T69_X : R600Reg <"T69.X">; +def T69_Y : R600Reg <"T69.Y">; +def T69_Z : R600Reg <"T69.Z">; +def T69_W : R600Reg <"T69.W">; +def T70_X : R600Reg <"T70.X">; +def T70_Y : R600Reg <"T70.Y">; +def T70_Z : R600Reg <"T70.Z">; +def T70_W : R600Reg <"T70.W">; +def T71_X : R600Reg <"T71.X">; +def T71_Y : R600Reg <"T71.Y">; +def T71_Z : R600Reg <"T71.Z">; +def T71_W : R600Reg <"T71.W">; +def T72_X : R600Reg <"T72.X">; +def T72_Y : R600Reg <"T72.Y">; +def T72_Z : R600Reg <"T72.Z">; +def T72_W : R600Reg <"T72.W">; +def T73_X : R600Reg <"T73.X">; +def T73_Y : R600Reg <"T73.Y">; +def T73_Z : R600Reg <"T73.Z">; +def T73_W : R600Reg <"T73.W">; +def T74_X : R600Reg <"T74.X">; +def T74_Y : R600Reg <"T74.Y">; +def T74_Z : R600Reg <"T74.Z">; +def T74_W : R600Reg <"T74.W">; +def T75_X : R600Reg <"T75.X">; +def T75_Y : R600Reg <"T75.Y">; +def T75_Z : R600Reg <"T75.Z">; +def T75_W : R600Reg <"T75.W">; +def T76_X : R600Reg <"T76.X">; +def T76_Y : R600Reg <"T76.Y">; +def T76_Z : R600Reg <"T76.Z">; +def T76_W : R600Reg <"T76.W">; +def T77_X : R600Reg <"T77.X">; +def T77_Y : R600Reg <"T77.Y">; +def T77_Z : R600Reg <"T77.Z">; +def T77_W : R600Reg <"T77.W">; +def T78_X : R600Reg <"T78.X">; +def T78_Y : R600Reg <"T78.Y">; +def T78_Z : R600Reg <"T78.Z">; +def T78_W : R600Reg <"T78.W">; +def T79_X : R600Reg <"T79.X">; +def T79_Y : R600Reg <"T79.Y">; +def T79_Z : R600Reg <"T79.Z">; +def T79_W : R600Reg <"T79.W">; +def T80_X : R600Reg <"T80.X">; +def T80_Y : R600Reg <"T80.Y">; +def T80_Z : R600Reg <"T80.Z">; +def T80_W : R600Reg <"T80.W">; +def T81_X : R600Reg <"T81.X">; +def T81_Y : R600Reg <"T81.Y">; +def T81_Z : R600Reg <"T81.Z">; +def T81_W : R600Reg <"T81.W">; +def T82_X : R600Reg <"T82.X">; +def T82_Y : R600Reg <"T82.Y">; +def T82_Z : R600Reg <"T82.Z">; +def T82_W : R600Reg <"T82.W">; +def T83_X : R600Reg <"T83.X">; +def T83_Y : R600Reg <"T83.Y">; +def T83_Z : R600Reg <"T83.Z">; +def T83_W : R600Reg <"T83.W">; +def T84_X : R600Reg <"T84.X">; +def T84_Y : R600Reg <"T84.Y">; +def T84_Z : R600Reg <"T84.Z">; +def T84_W : R600Reg <"T84.W">; +def T85_X : R600Reg <"T85.X">; +def T85_Y : R600Reg <"T85.Y">; +def T85_Z : R600Reg <"T85.Z">; +def T85_W : R600Reg <"T85.W">; +def T86_X : R600Reg <"T86.X">; +def T86_Y : R600Reg <"T86.Y">; +def T86_Z : R600Reg <"T86.Z">; +def T86_W : R600Reg <"T86.W">; +def T87_X : R600Reg <"T87.X">; +def T87_Y : R600Reg <"T87.Y">; +def T87_Z : R600Reg <"T87.Z">; +def T87_W : R600Reg <"T87.W">; +def T88_X : R600Reg <"T88.X">; +def T88_Y : R600Reg <"T88.Y">; +def T88_Z : R600Reg <"T88.Z">; +def T88_W : R600Reg <"T88.W">; +def T89_X : R600Reg <"T89.X">; +def T89_Y : R600Reg <"T89.Y">; +def T89_Z : R600Reg <"T89.Z">; +def T89_W : R600Reg <"T89.W">; +def T90_X : R600Reg <"T90.X">; +def T90_Y : R600Reg <"T90.Y">; +def T90_Z : R600Reg <"T90.Z">; +def T90_W : R600Reg <"T90.W">; +def T91_X : R600Reg <"T91.X">; +def T91_Y : R600Reg <"T91.Y">; +def T91_Z : R600Reg <"T91.Z">; +def T91_W : R600Reg <"T91.W">; +def T92_X : R600Reg <"T92.X">; +def T92_Y : R600Reg <"T92.Y">; +def T92_Z : R600Reg <"T92.Z">; +def T92_W : R600Reg <"T92.W">; +def T93_X : R600Reg <"T93.X">; +def T93_Y : R600Reg <"T93.Y">; +def T93_Z : R600Reg <"T93.Z">; +def T93_W : R600Reg <"T93.W">; +def T94_X : R600Reg <"T94.X">; +def T94_Y : R600Reg <"T94.Y">; +def T94_Z : R600Reg <"T94.Z">; +def T94_W : R600Reg <"T94.W">; +def T95_X : R600Reg <"T95.X">; +def T95_Y : R600Reg <"T95.Y">; +def T95_Z : R600Reg <"T95.Z">; +def T95_W : R600Reg <"T95.W">; +def T96_X : R600Reg <"T96.X">; +def T96_Y : R600Reg <"T96.Y">; +def T96_Z : R600Reg <"T96.Z">; +def T96_W : R600Reg <"T96.W">; +def T97_X : R600Reg <"T97.X">; +def T97_Y : R600Reg <"T97.Y">; +def T97_Z : R600Reg <"T97.Z">; +def T97_W : R600Reg <"T97.W">; +def T98_X : R600Reg <"T98.X">; +def T98_Y : R600Reg <"T98.Y">; +def T98_Z : R600Reg <"T98.Z">; +def T98_W : R600Reg <"T98.W">; +def T99_X : R600Reg <"T99.X">; +def T99_Y : R600Reg <"T99.Y">; +def T99_Z : R600Reg <"T99.Z">; +def T99_W : R600Reg <"T99.W">; +def T100_X : R600Reg <"T100.X">; +def T100_Y : R600Reg <"T100.Y">; +def T100_Z : R600Reg <"T100.Z">; +def T100_W : R600Reg <"T100.W">; +def T101_X : R600Reg <"T101.X">; +def T101_Y : R600Reg <"T101.Y">; +def T101_Z : R600Reg <"T101.Z">; +def T101_W : R600Reg <"T101.W">; +def T102_X : R600Reg <"T102.X">; +def T102_Y : R600Reg <"T102.Y">; +def T102_Z : R600Reg <"T102.Z">; +def T102_W : R600Reg <"T102.W">; +def T103_X : R600Reg <"T103.X">; +def T103_Y : R600Reg <"T103.Y">; +def T103_Z : R600Reg <"T103.Z">; +def T103_W : R600Reg <"T103.W">; +def T104_X : R600Reg <"T104.X">; +def T104_Y : R600Reg <"T104.Y">; +def T104_Z : R600Reg <"T104.Z">; +def T104_W : R600Reg <"T104.W">; +def T105_X : R600Reg <"T105.X">; +def T105_Y : R600Reg <"T105.Y">; +def T105_Z : R600Reg <"T105.Z">; +def T105_W : R600Reg <"T105.W">; +def T106_X : R600Reg <"T106.X">; +def T106_Y : R600Reg <"T106.Y">; +def T106_Z : R600Reg <"T106.Z">; +def T106_W : R600Reg <"T106.W">; +def T107_X : R600Reg <"T107.X">; +def T107_Y : R600Reg <"T107.Y">; +def T107_Z : R600Reg <"T107.Z">; +def T107_W : R600Reg <"T107.W">; +def T108_X : R600Reg <"T108.X">; +def T108_Y : R600Reg <"T108.Y">; +def T108_Z : R600Reg <"T108.Z">; +def T108_W : R600Reg <"T108.W">; +def T109_X : R600Reg <"T109.X">; +def T109_Y : R600Reg <"T109.Y">; +def T109_Z : R600Reg <"T109.Z">; +def T109_W : R600Reg <"T109.W">; +def T110_X : R600Reg <"T110.X">; +def T110_Y : R600Reg <"T110.Y">; +def T110_Z : R600Reg <"T110.Z">; +def T110_W : R600Reg <"T110.W">; +def T111_X : R600Reg <"T111.X">; +def T111_Y : R600Reg <"T111.Y">; +def T111_Z : R600Reg <"T111.Z">; +def T111_W : R600Reg <"T111.W">; +def T112_X : R600Reg <"T112.X">; +def T112_Y : R600Reg <"T112.Y">; +def T112_Z : R600Reg <"T112.Z">; +def T112_W : R600Reg <"T112.W">; +def T113_X : R600Reg <"T113.X">; +def T113_Y : R600Reg <"T113.Y">; +def T113_Z : R600Reg <"T113.Z">; +def T113_W : R600Reg <"T113.W">; +def T114_X : R600Reg <"T114.X">; +def T114_Y : R600Reg <"T114.Y">; +def T114_Z : R600Reg <"T114.Z">; +def T114_W : R600Reg <"T114.W">; +def T115_X : R600Reg <"T115.X">; +def T115_Y : R600Reg <"T115.Y">; +def T115_Z : R600Reg <"T115.Z">; +def T115_W : R600Reg <"T115.W">; +def T116_X : R600Reg <"T116.X">; +def T116_Y : R600Reg <"T116.Y">; +def T116_Z : R600Reg <"T116.Z">; +def T116_W : R600Reg <"T116.W">; +def T117_X : R600Reg <"T117.X">; +def T117_Y : R600Reg <"T117.Y">; +def T117_Z : R600Reg <"T117.Z">; +def T117_W : R600Reg <"T117.W">; +def T118_X : R600Reg <"T118.X">; +def T118_Y : R600Reg <"T118.Y">; +def T118_Z : R600Reg <"T118.Z">; +def T118_W : R600Reg <"T118.W">; +def T119_X : R600Reg <"T119.X">; +def T119_Y : R600Reg <"T119.Y">; +def T119_Z : R600Reg <"T119.Z">; +def T119_W : R600Reg <"T119.W">; +def T120_X : R600Reg <"T120.X">; +def T120_Y : R600Reg <"T120.Y">; +def T120_Z : R600Reg <"T120.Z">; +def T120_W : R600Reg <"T120.W">; +def T121_X : R600Reg <"T121.X">; +def T121_Y : R600Reg <"T121.Y">; +def T121_Z : R600Reg <"T121.Z">; +def T121_W : R600Reg <"T121.W">; +def T122_X : R600Reg <"T122.X">; +def T122_Y : R600Reg <"T122.Y">; +def T122_Z : R600Reg <"T122.Z">; +def T122_W : R600Reg <"T122.W">; +def T123_X : R600Reg <"T123.X">; +def T123_Y : R600Reg <"T123.Y">; +def T123_Z : R600Reg <"T123.Z">; +def T123_W : R600Reg <"T123.W">; +def T124_X : R600Reg <"T124.X">; +def T124_Y : R600Reg <"T124.Y">; +def T124_Z : R600Reg <"T124.Z">; +def T124_W : R600Reg <"T124.W">; +def T125_X : R600Reg <"T125.X">; +def T125_Y : R600Reg <"T125.Y">; +def T125_Z : R600Reg <"T125.Z">; +def T125_W : R600Reg <"T125.W">; +def T126_X : R600Reg <"T126.X">; +def T126_Y : R600Reg <"T126.Y">; +def T126_Z : R600Reg <"T126.Z">; +def T126_W : R600Reg <"T126.W">; +def T127_X : R600Reg <"T127.X">; +def T127_Y : R600Reg <"T127.Y">; +def T127_Z : R600Reg <"T127.Z">; +def T127_W : R600Reg <"T127.W">; +def T0_XYZW : R600Reg_128 <"T0.XYZW", [T0_X, T0_Y, T0_Z, T0_W] >; +def T1_XYZW : R600Reg_128 <"T1.XYZW", [T1_X, T1_Y, T1_Z, T1_W] >; +def T2_XYZW : R600Reg_128 <"T2.XYZW", [T2_X, T2_Y, T2_Z, T2_W] >; +def T3_XYZW : R600Reg_128 <"T3.XYZW", [T3_X, T3_Y, T3_Z, T3_W] >; +def T4_XYZW : R600Reg_128 <"T4.XYZW", [T4_X, T4_Y, T4_Z, T4_W] >; +def T5_XYZW : R600Reg_128 <"T5.XYZW", [T5_X, T5_Y, T5_Z, T5_W] >; +def T6_XYZW : R600Reg_128 <"T6.XYZW", [T6_X, T6_Y, T6_Z, T6_W] >; +def T7_XYZW : R600Reg_128 <"T7.XYZW", [T7_X, T7_Y, T7_Z, T7_W] >; +def T8_XYZW : R600Reg_128 <"T8.XYZW", [T8_X, T8_Y, T8_Z, T8_W] >; +def T9_XYZW : R600Reg_128 <"T9.XYZW", [T9_X, T9_Y, T9_Z, T9_W] >; +def T10_XYZW : R600Reg_128 <"T10.XYZW", [T10_X, T10_Y, T10_Z, T10_W] >; +def T11_XYZW : R600Reg_128 <"T11.XYZW", [T11_X, T11_Y, T11_Z, T11_W] >; +def T12_XYZW : R600Reg_128 <"T12.XYZW", [T12_X, T12_Y, T12_Z, T12_W] >; +def T13_XYZW : R600Reg_128 <"T13.XYZW", [T13_X, T13_Y, T13_Z, T13_W] >; +def T14_XYZW : R600Reg_128 <"T14.XYZW", [T14_X, T14_Y, T14_Z, T14_W] >; +def T15_XYZW : R600Reg_128 <"T15.XYZW", [T15_X, T15_Y, T15_Z, T15_W] >; +def T16_XYZW : R600Reg_128 <"T16.XYZW", [T16_X, T16_Y, T16_Z, T16_W] >; +def T17_XYZW : R600Reg_128 <"T17.XYZW", [T17_X, T17_Y, T17_Z, T17_W] >; +def T18_XYZW : R600Reg_128 <"T18.XYZW", [T18_X, T18_Y, T18_Z, T18_W] >; +def T19_XYZW : R600Reg_128 <"T19.XYZW", [T19_X, T19_Y, T19_Z, T19_W] >; +def T20_XYZW : R600Reg_128 <"T20.XYZW", [T20_X, T20_Y, T20_Z, T20_W] >; +def T21_XYZW : R600Reg_128 <"T21.XYZW", [T21_X, T21_Y, T21_Z, T21_W] >; +def T22_XYZW : R600Reg_128 <"T22.XYZW", [T22_X, T22_Y, T22_Z, T22_W] >; +def T23_XYZW : R600Reg_128 <"T23.XYZW", [T23_X, T23_Y, T23_Z, T23_W] >; +def T24_XYZW : R600Reg_128 <"T24.XYZW", [T24_X, T24_Y, T24_Z, T24_W] >; +def T25_XYZW : R600Reg_128 <"T25.XYZW", [T25_X, T25_Y, T25_Z, T25_W] >; +def T26_XYZW : R600Reg_128 <"T26.XYZW", [T26_X, T26_Y, T26_Z, T26_W] >; +def T27_XYZW : R600Reg_128 <"T27.XYZW", [T27_X, T27_Y, T27_Z, T27_W] >; +def T28_XYZW : R600Reg_128 <"T28.XYZW", [T28_X, T28_Y, T28_Z, T28_W] >; +def T29_XYZW : R600Reg_128 <"T29.XYZW", [T29_X, T29_Y, T29_Z, T29_W] >; +def T30_XYZW : R600Reg_128 <"T30.XYZW", [T30_X, T30_Y, T30_Z, T30_W] >; +def T31_XYZW : R600Reg_128 <"T31.XYZW", [T31_X, T31_Y, T31_Z, T31_W] >; +def T32_XYZW : R600Reg_128 <"T32.XYZW", [T32_X, T32_Y, T32_Z, T32_W] >; +def T33_XYZW : R600Reg_128 <"T33.XYZW", [T33_X, T33_Y, T33_Z, T33_W] >; +def T34_XYZW : R600Reg_128 <"T34.XYZW", [T34_X, T34_Y, T34_Z, T34_W] >; +def T35_XYZW : R600Reg_128 <"T35.XYZW", [T35_X, T35_Y, T35_Z, T35_W] >; +def T36_XYZW : R600Reg_128 <"T36.XYZW", [T36_X, T36_Y, T36_Z, T36_W] >; +def T37_XYZW : R600Reg_128 <"T37.XYZW", [T37_X, T37_Y, T37_Z, T37_W] >; +def T38_XYZW : R600Reg_128 <"T38.XYZW", [T38_X, T38_Y, T38_Z, T38_W] >; +def T39_XYZW : R600Reg_128 <"T39.XYZW", [T39_X, T39_Y, T39_Z, T39_W] >; +def T40_XYZW : R600Reg_128 <"T40.XYZW", [T40_X, T40_Y, T40_Z, T40_W] >; +def T41_XYZW : R600Reg_128 <"T41.XYZW", [T41_X, T41_Y, T41_Z, T41_W] >; +def T42_XYZW : R600Reg_128 <"T42.XYZW", [T42_X, T42_Y, T42_Z, T42_W] >; +def T43_XYZW : R600Reg_128 <"T43.XYZW", [T43_X, T43_Y, T43_Z, T43_W] >; +def T44_XYZW : R600Reg_128 <"T44.XYZW", [T44_X, T44_Y, T44_Z, T44_W] >; +def T45_XYZW : R600Reg_128 <"T45.XYZW", [T45_X, T45_Y, T45_Z, T45_W] >; +def T46_XYZW : R600Reg_128 <"T46.XYZW", [T46_X, T46_Y, T46_Z, T46_W] >; +def T47_XYZW : R600Reg_128 <"T47.XYZW", [T47_X, T47_Y, T47_Z, T47_W] >; +def T48_XYZW : R600Reg_128 <"T48.XYZW", [T48_X, T48_Y, T48_Z, T48_W] >; +def T49_XYZW : R600Reg_128 <"T49.XYZW", [T49_X, T49_Y, T49_Z, T49_W] >; +def T50_XYZW : R600Reg_128 <"T50.XYZW", [T50_X, T50_Y, T50_Z, T50_W] >; +def T51_XYZW : R600Reg_128 <"T51.XYZW", [T51_X, T51_Y, T51_Z, T51_W] >; +def T52_XYZW : R600Reg_128 <"T52.XYZW", [T52_X, T52_Y, T52_Z, T52_W] >; +def T53_XYZW : R600Reg_128 <"T53.XYZW", [T53_X, T53_Y, T53_Z, T53_W] >; +def T54_XYZW : R600Reg_128 <"T54.XYZW", [T54_X, T54_Y, T54_Z, T54_W] >; +def T55_XYZW : R600Reg_128 <"T55.XYZW", [T55_X, T55_Y, T55_Z, T55_W] >; +def T56_XYZW : R600Reg_128 <"T56.XYZW", [T56_X, T56_Y, T56_Z, T56_W] >; +def T57_XYZW : R600Reg_128 <"T57.XYZW", [T57_X, T57_Y, T57_Z, T57_W] >; +def T58_XYZW : R600Reg_128 <"T58.XYZW", [T58_X, T58_Y, T58_Z, T58_W] >; +def T59_XYZW : R600Reg_128 <"T59.XYZW", [T59_X, T59_Y, T59_Z, T59_W] >; +def T60_XYZW : R600Reg_128 <"T60.XYZW", [T60_X, T60_Y, T60_Z, T60_W] >; +def T61_XYZW : R600Reg_128 <"T61.XYZW", [T61_X, T61_Y, T61_Z, T61_W] >; +def T62_XYZW : R600Reg_128 <"T62.XYZW", [T62_X, T62_Y, T62_Z, T62_W] >; +def T63_XYZW : R600Reg_128 <"T63.XYZW", [T63_X, T63_Y, T63_Z, T63_W] >; +def T64_XYZW : R600Reg_128 <"T64.XYZW", [T64_X, T64_Y, T64_Z, T64_W] >; +def T65_XYZW : R600Reg_128 <"T65.XYZW", [T65_X, T65_Y, T65_Z, T65_W] >; +def T66_XYZW : R600Reg_128 <"T66.XYZW", [T66_X, T66_Y, T66_Z, T66_W] >; +def T67_XYZW : R600Reg_128 <"T67.XYZW", [T67_X, T67_Y, T67_Z, T67_W] >; +def T68_XYZW : R600Reg_128 <"T68.XYZW", [T68_X, T68_Y, T68_Z, T68_W] >; +def T69_XYZW : R600Reg_128 <"T69.XYZW", [T69_X, T69_Y, T69_Z, T69_W] >; +def T70_XYZW : R600Reg_128 <"T70.XYZW", [T70_X, T70_Y, T70_Z, T70_W] >; +def T71_XYZW : R600Reg_128 <"T71.XYZW", [T71_X, T71_Y, T71_Z, T71_W] >; +def T72_XYZW : R600Reg_128 <"T72.XYZW", [T72_X, T72_Y, T72_Z, T72_W] >; +def T73_XYZW : R600Reg_128 <"T73.XYZW", [T73_X, T73_Y, T73_Z, T73_W] >; +def T74_XYZW : R600Reg_128 <"T74.XYZW", [T74_X, T74_Y, T74_Z, T74_W] >; +def T75_XYZW : R600Reg_128 <"T75.XYZW", [T75_X, T75_Y, T75_Z, T75_W] >; +def T76_XYZW : R600Reg_128 <"T76.XYZW", [T76_X, T76_Y, T76_Z, T76_W] >; +def T77_XYZW : R600Reg_128 <"T77.XYZW", [T77_X, T77_Y, T77_Z, T77_W] >; +def T78_XYZW : R600Reg_128 <"T78.XYZW", [T78_X, T78_Y, T78_Z, T78_W] >; +def T79_XYZW : R600Reg_128 <"T79.XYZW", [T79_X, T79_Y, T79_Z, T79_W] >; +def T80_XYZW : R600Reg_128 <"T80.XYZW", [T80_X, T80_Y, T80_Z, T80_W] >; +def T81_XYZW : R600Reg_128 <"T81.XYZW", [T81_X, T81_Y, T81_Z, T81_W] >; +def T82_XYZW : R600Reg_128 <"T82.XYZW", [T82_X, T82_Y, T82_Z, T82_W] >; +def T83_XYZW : R600Reg_128 <"T83.XYZW", [T83_X, T83_Y, T83_Z, T83_W] >; +def T84_XYZW : R600Reg_128 <"T84.XYZW", [T84_X, T84_Y, T84_Z, T84_W] >; +def T85_XYZW : R600Reg_128 <"T85.XYZW", [T85_X, T85_Y, T85_Z, T85_W] >; +def T86_XYZW : R600Reg_128 <"T86.XYZW", [T86_X, T86_Y, T86_Z, T86_W] >; +def T87_XYZW : R600Reg_128 <"T87.XYZW", [T87_X, T87_Y, T87_Z, T87_W] >; +def T88_XYZW : R600Reg_128 <"T88.XYZW", [T88_X, T88_Y, T88_Z, T88_W] >; +def T89_XYZW : R600Reg_128 <"T89.XYZW", [T89_X, T89_Y, T89_Z, T89_W] >; +def T90_XYZW : R600Reg_128 <"T90.XYZW", [T90_X, T90_Y, T90_Z, T90_W] >; +def T91_XYZW : R600Reg_128 <"T91.XYZW", [T91_X, T91_Y, T91_Z, T91_W] >; +def T92_XYZW : R600Reg_128 <"T92.XYZW", [T92_X, T92_Y, T92_Z, T92_W] >; +def T93_XYZW : R600Reg_128 <"T93.XYZW", [T93_X, T93_Y, T93_Z, T93_W] >; +def T94_XYZW : R600Reg_128 <"T94.XYZW", [T94_X, T94_Y, T94_Z, T94_W] >; +def T95_XYZW : R600Reg_128 <"T95.XYZW", [T95_X, T95_Y, T95_Z, T95_W] >; +def T96_XYZW : R600Reg_128 <"T96.XYZW", [T96_X, T96_Y, T96_Z, T96_W] >; +def T97_XYZW : R600Reg_128 <"T97.XYZW", [T97_X, T97_Y, T97_Z, T97_W] >; +def T98_XYZW : R600Reg_128 <"T98.XYZW", [T98_X, T98_Y, T98_Z, T98_W] >; +def T99_XYZW : R600Reg_128 <"T99.XYZW", [T99_X, T99_Y, T99_Z, T99_W] >; +def T100_XYZW : R600Reg_128 <"T100.XYZW", [T100_X, T100_Y, T100_Z, T100_W] >; +def T101_XYZW : R600Reg_128 <"T101.XYZW", [T101_X, T101_Y, T101_Z, T101_W] >; +def T102_XYZW : R600Reg_128 <"T102.XYZW", [T102_X, T102_Y, T102_Z, T102_W] >; +def T103_XYZW : R600Reg_128 <"T103.XYZW", [T103_X, T103_Y, T103_Z, T103_W] >; +def T104_XYZW : R600Reg_128 <"T104.XYZW", [T104_X, T104_Y, T104_Z, T104_W] >; +def T105_XYZW : R600Reg_128 <"T105.XYZW", [T105_X, T105_Y, T105_Z, T105_W] >; +def T106_XYZW : R600Reg_128 <"T106.XYZW", [T106_X, T106_Y, T106_Z, T106_W] >; +def T107_XYZW : R600Reg_128 <"T107.XYZW", [T107_X, T107_Y, T107_Z, T107_W] >; +def T108_XYZW : R600Reg_128 <"T108.XYZW", [T108_X, T108_Y, T108_Z, T108_W] >; +def T109_XYZW : R600Reg_128 <"T109.XYZW", [T109_X, T109_Y, T109_Z, T109_W] >; +def T110_XYZW : R600Reg_128 <"T110.XYZW", [T110_X, T110_Y, T110_Z, T110_W] >; +def T111_XYZW : R600Reg_128 <"T111.XYZW", [T111_X, T111_Y, T111_Z, T111_W] >; +def T112_XYZW : R600Reg_128 <"T112.XYZW", [T112_X, T112_Y, T112_Z, T112_W] >; +def T113_XYZW : R600Reg_128 <"T113.XYZW", [T113_X, T113_Y, T113_Z, T113_W] >; +def T114_XYZW : R600Reg_128 <"T114.XYZW", [T114_X, T114_Y, T114_Z, T114_W] >; +def T115_XYZW : R600Reg_128 <"T115.XYZW", [T115_X, T115_Y, T115_Z, T115_W] >; +def T116_XYZW : R600Reg_128 <"T116.XYZW", [T116_X, T116_Y, T116_Z, T116_W] >; +def T117_XYZW : R600Reg_128 <"T117.XYZW", [T117_X, T117_Y, T117_Z, T117_W] >; +def T118_XYZW : R600Reg_128 <"T118.XYZW", [T118_X, T118_Y, T118_Z, T118_W] >; +def T119_XYZW : R600Reg_128 <"T119.XYZW", [T119_X, T119_Y, T119_Z, T119_W] >; +def T120_XYZW : R600Reg_128 <"T120.XYZW", [T120_X, T120_Y, T120_Z, T120_W] >; +def T121_XYZW : R600Reg_128 <"T121.XYZW", [T121_X, T121_Y, T121_Z, T121_W] >; +def T122_XYZW : R600Reg_128 <"T122.XYZW", [T122_X, T122_Y, T122_Z, T122_W] >; +def T123_XYZW : R600Reg_128 <"T123.XYZW", [T123_X, T123_Y, T123_Z, T123_W] >; +def T124_XYZW : R600Reg_128 <"T124.XYZW", [T124_X, T124_Y, T124_Z, T124_W] >; +def T125_XYZW : R600Reg_128 <"T125.XYZW", [T125_X, T125_Y, T125_Z, T125_W] >; +def T126_XYZW : R600Reg_128 <"T126.XYZW", [T126_X, T126_Y, T126_Z, T126_W] >; +def T127_XYZW : R600Reg_128 <"T127.XYZW", [T127_X, T127_Y, T127_Z, T127_W] >; + +class RegSet { + dag set = s; +} + +def ZERO : R600Reg<"0.0">; +def HALF : R600Reg<"0.5">; +def ONE : R600Reg<"1.0">; +def ONE_INT : R600Reg<"1">; +def NEG_HALF : R600Reg<"-0.5">; +def NEG_ONE : R600Reg<"-1.0">; +def PV_X : R600Reg<"pv.x">; +def ALU_LITERAL_X : R600Reg<"literal.x">; + +def R600_CReg32 : RegisterClass <"AMDIL", [f32, i32], 32, (add + C0_X +,C0_Y,C0_Z,C0_W,C1_X,C1_Y,C1_Z,C1_W,C2_X,C2_Y,C2_Z +,C2_W,C3_X,C3_Y,C3_Z,C3_W,C4_X,C4_Y,C4_Z,C4_W,C5_X +,C5_Y,C5_Z,C5_W,C6_X,C6_Y,C6_Z,C6_W,C7_X,C7_Y,C7_Z +,C7_W,C8_X,C8_Y,C8_Z,C8_W,C9_X,C9_Y,C9_Z,C9_W,C10_X +,C10_Y,C10_Z,C10_W,C11_X,C11_Y,C11_Z,C11_W,C12_X,C12_Y,C12_Z +,C12_W,C13_X,C13_Y,C13_Z,C13_W,C14_X,C14_Y,C14_Z,C14_W,C15_X +,C15_Y,C15_Z,C15_W,C16_X,C16_Y,C16_Z,C16_W,C17_X,C17_Y,C17_Z +,C17_W,C18_X,C18_Y,C18_Z,C18_W,C19_X,C19_Y,C19_Z,C19_W,C20_X +,C20_Y,C20_Z,C20_W,C21_X,C21_Y,C21_Z,C21_W,C22_X,C22_Y,C22_Z +,C22_W,C23_X,C23_Y,C23_Z,C23_W,C24_X,C24_Y,C24_Z,C24_W,C25_X +,C25_Y,C25_Z,C25_W,C26_X,C26_Y,C26_Z,C26_W,C27_X,C27_Y,C27_Z +,C27_W,C28_X,C28_Y,C28_Z,C28_W,C29_X,C29_Y,C29_Z,C29_W,C30_X +,C30_Y,C30_Z,C30_W,C31_X,C31_Y,C31_Z,C31_W,C32_X,C32_Y,C32_Z +,C32_W,C33_X,C33_Y,C33_Z,C33_W,C34_X,C34_Y,C34_Z,C34_W,C35_X +,C35_Y,C35_Z,C35_W,C36_X,C36_Y,C36_Z,C36_W,C37_X,C37_Y,C37_Z +,C37_W,C38_X,C38_Y,C38_Z,C38_W,C39_X,C39_Y,C39_Z,C39_W,C40_X +,C40_Y,C40_Z,C40_W,C41_X,C41_Y,C41_Z,C41_W,C42_X,C42_Y,C42_Z +,C42_W,C43_X,C43_Y,C43_Z,C43_W,C44_X,C44_Y,C44_Z,C44_W,C45_X +,C45_Y,C45_Z,C45_W,C46_X,C46_Y,C46_Z,C46_W,C47_X,C47_Y,C47_Z +,C47_W,C48_X,C48_Y,C48_Z,C48_W,C49_X,C49_Y,C49_Z,C49_W,C50_X +,C50_Y,C50_Z,C50_W,C51_X,C51_Y,C51_Z,C51_W,C52_X,C52_Y,C52_Z +,C52_W,C53_X,C53_Y,C53_Z,C53_W,C54_X,C54_Y,C54_Z,C54_W,C55_X +,C55_Y,C55_Z,C55_W,C56_X,C56_Y,C56_Z,C56_W,C57_X,C57_Y,C57_Z +,C57_W,C58_X,C58_Y,C58_Z,C58_W,C59_X,C59_Y,C59_Z,C59_W,C60_X +,C60_Y,C60_Z,C60_W,C61_X,C61_Y,C61_Z,C61_W,C62_X,C62_Y,C62_Z +,C62_W,C63_X,C63_Y,C63_Z,C63_W,C64_X,C64_Y,C64_Z,C64_W,C65_X +,C65_Y,C65_Z,C65_W,C66_X,C66_Y,C66_Z,C66_W,C67_X,C67_Y,C67_Z +,C67_W,C68_X,C68_Y,C68_Z,C68_W,C69_X,C69_Y,C69_Z,C69_W,C70_X +,C70_Y,C70_Z,C70_W,C71_X,C71_Y,C71_Z,C71_W,C72_X,C72_Y,C72_Z +,C72_W,C73_X,C73_Y,C73_Z,C73_W,C74_X,C74_Y,C74_Z,C74_W,C75_X +,C75_Y,C75_Z,C75_W,C76_X,C76_Y,C76_Z,C76_W,C77_X,C77_Y,C77_Z +,C77_W,C78_X,C78_Y,C78_Z,C78_W,C79_X,C79_Y,C79_Z,C79_W,C80_X +,C80_Y,C80_Z,C80_W,C81_X,C81_Y,C81_Z,C81_W,C82_X,C82_Y,C82_Z +,C82_W,C83_X,C83_Y,C83_Z,C83_W,C84_X,C84_Y,C84_Z,C84_W,C85_X +,C85_Y,C85_Z,C85_W,C86_X,C86_Y,C86_Z,C86_W,C87_X,C87_Y,C87_Z +,C87_W,C88_X,C88_Y,C88_Z,C88_W,C89_X,C89_Y,C89_Z,C89_W,C90_X +,C90_Y,C90_Z,C90_W,C91_X,C91_Y,C91_Z,C91_W,C92_X,C92_Y,C92_Z +,C92_W,C93_X,C93_Y,C93_Z,C93_W,C94_X,C94_Y,C94_Z,C94_W,C95_X +,C95_Y,C95_Z,C95_W,C96_X,C96_Y,C96_Z,C96_W,C97_X,C97_Y,C97_Z +,C97_W,C98_X,C98_Y,C98_Z,C98_W,C99_X,C99_Y,C99_Z,C99_W,C100_X +,C100_Y,C100_Z,C100_W,C101_X,C101_Y,C101_Z,C101_W,C102_X,C102_Y,C102_Z +,C102_W,C103_X,C103_Y,C103_Z,C103_W,C104_X,C104_Y,C104_Z,C104_W,C105_X +,C105_Y,C105_Z,C105_W,C106_X,C106_Y,C106_Z,C106_W,C107_X,C107_Y,C107_Z +,C107_W,C108_X,C108_Y,C108_Z,C108_W,C109_X,C109_Y,C109_Z,C109_W,C110_X +,C110_Y,C110_Z,C110_W,C111_X,C111_Y,C111_Z,C111_W,C112_X,C112_Y,C112_Z +,C112_W,C113_X,C113_Y,C113_Z,C113_W,C114_X,C114_Y,C114_Z,C114_W,C115_X +,C115_Y,C115_Z,C115_W,C116_X,C116_Y,C116_Z,C116_W,C117_X,C117_Y,C117_Z +,C117_W,C118_X,C118_Y,C118_Z,C118_W,C119_X,C119_Y,C119_Z,C119_W,C120_X +,C120_Y,C120_Z,C120_W,C121_X,C121_Y,C121_Z,C121_W,C122_X,C122_Y,C122_Z +,C122_W,C123_X,C123_Y,C123_Z,C123_W,C124_X,C124_Y,C124_Z,C124_W,C125_X +,C125_Y,C125_Z,C125_W,C126_X,C126_Y,C126_Z,C126_W,C127_X,C127_Y,C127_Z +,C127_W,C128_X,C128_Y,C128_Z,C128_W,C129_X,C129_Y,C129_Z,C129_W,C130_X +,C130_Y,C130_Z,C130_W,C131_X,C131_Y,C131_Z,C131_W,C132_X,C132_Y,C132_Z +,C132_W,C133_X,C133_Y,C133_Z,C133_W,C134_X,C134_Y,C134_Z,C134_W,C135_X +,C135_Y,C135_Z,C135_W,C136_X,C136_Y,C136_Z,C136_W,C137_X,C137_Y,C137_Z +,C137_W,C138_X,C138_Y,C138_Z,C138_W,C139_X,C139_Y,C139_Z,C139_W,C140_X +,C140_Y,C140_Z,C140_W,C141_X,C141_Y,C141_Z,C141_W,C142_X,C142_Y,C142_Z +,C142_W,C143_X,C143_Y,C143_Z,C143_W,C144_X,C144_Y,C144_Z,C144_W,C145_X +,C145_Y,C145_Z,C145_W,C146_X,C146_Y,C146_Z,C146_W,C147_X,C147_Y,C147_Z +,C147_W,C148_X,C148_Y,C148_Z,C148_W,C149_X,C149_Y,C149_Z,C149_W,C150_X +,C150_Y,C150_Z,C150_W,C151_X,C151_Y,C151_Z,C151_W,C152_X,C152_Y,C152_Z +,C152_W,C153_X,C153_Y,C153_Z,C153_W,C154_X,C154_Y,C154_Z,C154_W,C155_X +,C155_Y,C155_Z,C155_W,C156_X,C156_Y,C156_Z,C156_W,C157_X,C157_Y,C157_Z +,C157_W,C158_X,C158_Y,C158_Z,C158_W,C159_X,C159_Y,C159_Z,C159_W,C160_X +,C160_Y,C160_Z,C160_W,C161_X,C161_Y,C161_Z,C161_W,C162_X,C162_Y,C162_Z +,C162_W,C163_X,C163_Y,C163_Z,C163_W,C164_X,C164_Y,C164_Z,C164_W,C165_X +,C165_Y,C165_Z,C165_W,C166_X,C166_Y,C166_Z,C166_W,C167_X,C167_Y,C167_Z +,C167_W,C168_X,C168_Y,C168_Z,C168_W,C169_X,C169_Y,C169_Z,C169_W,C170_X +,C170_Y,C170_Z,C170_W,C171_X,C171_Y,C171_Z,C171_W,C172_X,C172_Y,C172_Z +,C172_W,C173_X,C173_Y,C173_Z,C173_W,C174_X,C174_Y,C174_Z,C174_W,C175_X +,C175_Y,C175_Z,C175_W,C176_X,C176_Y,C176_Z,C176_W,C177_X,C177_Y,C177_Z +,C177_W,C178_X,C178_Y,C178_Z,C178_W,C179_X,C179_Y,C179_Z,C179_W,C180_X +,C180_Y,C180_Z,C180_W,C181_X,C181_Y,C181_Z,C181_W,C182_X,C182_Y,C182_Z +,C182_W,C183_X,C183_Y,C183_Z,C183_W,C184_X,C184_Y,C184_Z,C184_W,C185_X +,C185_Y,C185_Z,C185_W,C186_X,C186_Y,C186_Z,C186_W,C187_X,C187_Y,C187_Z +,C187_W,C188_X,C188_Y,C188_Z,C188_W,C189_X,C189_Y,C189_Z,C189_W,C190_X +,C190_Y,C190_Z,C190_W,C191_X,C191_Y,C191_Z,C191_W,C192_X,C192_Y,C192_Z +,C192_W,C193_X,C193_Y,C193_Z,C193_W,C194_X,C194_Y,C194_Z,C194_W,C195_X +,C195_Y,C195_Z,C195_W,C196_X,C196_Y,C196_Z,C196_W,C197_X,C197_Y,C197_Z +,C197_W,C198_X,C198_Y,C198_Z,C198_W,C199_X,C199_Y,C199_Z,C199_W,C200_X +,C200_Y,C200_Z,C200_W,C201_X,C201_Y,C201_Z,C201_W,C202_X,C202_Y,C202_Z +,C202_W,C203_X,C203_Y,C203_Z,C203_W,C204_X,C204_Y,C204_Z,C204_W,C205_X +,C205_Y,C205_Z,C205_W,C206_X,C206_Y,C206_Z,C206_W,C207_X,C207_Y,C207_Z +,C207_W,C208_X,C208_Y,C208_Z,C208_W,C209_X,C209_Y,C209_Z,C209_W,C210_X +,C210_Y,C210_Z,C210_W,C211_X,C211_Y,C211_Z,C211_W,C212_X,C212_Y,C212_Z +,C212_W,C213_X,C213_Y,C213_Z,C213_W,C214_X,C214_Y,C214_Z,C214_W,C215_X +,C215_Y,C215_Z,C215_W,C216_X,C216_Y,C216_Z,C216_W,C217_X,C217_Y,C217_Z +,C217_W,C218_X,C218_Y,C218_Z,C218_W,C219_X,C219_Y,C219_Z,C219_W,C220_X +,C220_Y,C220_Z,C220_W,C221_X,C221_Y,C221_Z,C221_W,C222_X,C222_Y,C222_Z +,C222_W,C223_X,C223_Y,C223_Z,C223_W,C224_X,C224_Y,C224_Z,C224_W,C225_X +,C225_Y,C225_Z,C225_W,C226_X,C226_Y,C226_Z,C226_W,C227_X,C227_Y,C227_Z +,C227_W,C228_X,C228_Y,C228_Z,C228_W,C229_X,C229_Y,C229_Z,C229_W,C230_X +,C230_Y,C230_Z,C230_W,C231_X,C231_Y,C231_Z,C231_W,C232_X,C232_Y,C232_Z +,C232_W,C233_X,C233_Y,C233_Z,C233_W,C234_X,C234_Y,C234_Z,C234_W,C235_X +,C235_Y,C235_Z,C235_W,C236_X,C236_Y,C236_Z,C236_W,C237_X,C237_Y,C237_Z +,C237_W,C238_X,C238_Y,C238_Z,C238_W,C239_X,C239_Y,C239_Z,C239_W,C240_X +,C240_Y,C240_Z,C240_W,C241_X,C241_Y,C241_Z,C241_W,C242_X,C242_Y,C242_Z +,C242_W,C243_X,C243_Y,C243_Z,C243_W,C244_X,C244_Y,C244_Z,C244_W,C245_X +,C245_Y,C245_Z,C245_W,C246_X,C246_Y,C246_Z,C246_W,C247_X,C247_Y,C247_Z +,C247_W,C248_X,C248_Y,C248_Z,C248_W,C249_X,C249_Y,C249_Z,C249_W,C250_X +,C250_Y,C250_Z,C250_W,C251_X,C251_Y,C251_Z,C251_W,C252_X,C252_Y,C252_Z +,C252_W,C253_X,C253_Y,C253_Z,C253_W,C254_X,C254_Y,C254_Z,C254_W,C255_X +,C255_Y,C255_Z,C255_W)>; + +def R600_TReg32 : RegisterClass <"AMDIL", [f32, i32], 32, (add + T0_X +,T0_Y,T0_Z,T0_W,T1_X,T1_Y,T1_Z,T1_W,T2_X,T2_Y,T2_Z +,T2_W,T3_X,T3_Y,T3_Z,T3_W,T4_X,T4_Y,T4_Z,T4_W,T5_X +,T5_Y,T5_Z,T5_W,T6_X,T6_Y,T6_Z,T6_W,T7_X,T7_Y,T7_Z +,T7_W,T8_X,T8_Y,T8_Z,T8_W,T9_X,T9_Y,T9_Z,T9_W,T10_X +,T10_Y,T10_Z,T10_W,T11_X,T11_Y,T11_Z,T11_W,T12_X,T12_Y,T12_Z +,T12_W,T13_X,T13_Y,T13_Z,T13_W,T14_X,T14_Y,T14_Z,T14_W,T15_X +,T15_Y,T15_Z,T15_W,T16_X,T16_Y,T16_Z,T16_W,T17_X,T17_Y,T17_Z +,T17_W,T18_X,T18_Y,T18_Z,T18_W,T19_X,T19_Y,T19_Z,T19_W,T20_X +,T20_Y,T20_Z,T20_W,T21_X,T21_Y,T21_Z,T21_W,T22_X,T22_Y,T22_Z +,T22_W,T23_X,T23_Y,T23_Z,T23_W,T24_X,T24_Y,T24_Z,T24_W,T25_X +,T25_Y,T25_Z,T25_W,T26_X,T26_Y,T26_Z,T26_W,T27_X,T27_Y,T27_Z +,T27_W,T28_X,T28_Y,T28_Z,T28_W,T29_X,T29_Y,T29_Z,T29_W,T30_X +,T30_Y,T30_Z,T30_W,T31_X,T31_Y,T31_Z,T31_W,T32_X,T32_Y,T32_Z +,T32_W,T33_X,T33_Y,T33_Z,T33_W,T34_X,T34_Y,T34_Z,T34_W,T35_X +,T35_Y,T35_Z,T35_W,T36_X,T36_Y,T36_Z,T36_W,T37_X,T37_Y,T37_Z +,T37_W,T38_X,T38_Y,T38_Z,T38_W,T39_X,T39_Y,T39_Z,T39_W,T40_X +,T40_Y,T40_Z,T40_W,T41_X,T41_Y,T41_Z,T41_W,T42_X,T42_Y,T42_Z +,T42_W,T43_X,T43_Y,T43_Z,T43_W,T44_X,T44_Y,T44_Z,T44_W,T45_X +,T45_Y,T45_Z,T45_W,T46_X,T46_Y,T46_Z,T46_W,T47_X,T47_Y,T47_Z +,T47_W,T48_X,T48_Y,T48_Z,T48_W,T49_X,T49_Y,T49_Z,T49_W,T50_X +,T50_Y,T50_Z,T50_W,T51_X,T51_Y,T51_Z,T51_W,T52_X,T52_Y,T52_Z +,T52_W,T53_X,T53_Y,T53_Z,T53_W,T54_X,T54_Y,T54_Z,T54_W,T55_X +,T55_Y,T55_Z,T55_W,T56_X,T56_Y,T56_Z,T56_W,T57_X,T57_Y,T57_Z +,T57_W,T58_X,T58_Y,T58_Z,T58_W,T59_X,T59_Y,T59_Z,T59_W,T60_X +,T60_Y,T60_Z,T60_W,T61_X,T61_Y,T61_Z,T61_W,T62_X,T62_Y,T62_Z +,T62_W,T63_X,T63_Y,T63_Z,T63_W,T64_X,T64_Y,T64_Z,T64_W,T65_X +,T65_Y,T65_Z,T65_W,T66_X,T66_Y,T66_Z,T66_W,T67_X,T67_Y,T67_Z +,T67_W,T68_X,T68_Y,T68_Z,T68_W,T69_X,T69_Y,T69_Z,T69_W,T70_X +,T70_Y,T70_Z,T70_W,T71_X,T71_Y,T71_Z,T71_W,T72_X,T72_Y,T72_Z +,T72_W,T73_X,T73_Y,T73_Z,T73_W,T74_X,T74_Y,T74_Z,T74_W,T75_X +,T75_Y,T75_Z,T75_W,T76_X,T76_Y,T76_Z,T76_W,T77_X,T77_Y,T77_Z +,T77_W,T78_X,T78_Y,T78_Z,T78_W,T79_X,T79_Y,T79_Z,T79_W,T80_X +,T80_Y,T80_Z,T80_W,T81_X,T81_Y,T81_Z,T81_W,T82_X,T82_Y,T82_Z +,T82_W,T83_X,T83_Y,T83_Z,T83_W,T84_X,T84_Y,T84_Z,T84_W,T85_X +,T85_Y,T85_Z,T85_W,T86_X,T86_Y,T86_Z,T86_W,T87_X,T87_Y,T87_Z +,T87_W,T88_X,T88_Y,T88_Z,T88_W,T89_X,T89_Y,T89_Z,T89_W,T90_X +,T90_Y,T90_Z,T90_W,T91_X,T91_Y,T91_Z,T91_W,T92_X,T92_Y,T92_Z +,T92_W,T93_X,T93_Y,T93_Z,T93_W,T94_X,T94_Y,T94_Z,T94_W,T95_X +,T95_Y,T95_Z,T95_W,T96_X,T96_Y,T96_Z,T96_W,T97_X,T97_Y,T97_Z +,T97_W,T98_X,T98_Y,T98_Z,T98_W,T99_X,T99_Y,T99_Z,T99_W,T100_X +,T100_Y,T100_Z,T100_W,T101_X,T101_Y,T101_Z,T101_W,T102_X,T102_Y,T102_Z +,T102_W,T103_X,T103_Y,T103_Z,T103_W,T104_X,T104_Y,T104_Z,T104_W,T105_X +,T105_Y,T105_Z,T105_W,T106_X,T106_Y,T106_Z,T106_W,T107_X,T107_Y,T107_Z +,T107_W,T108_X,T108_Y,T108_Z,T108_W,T109_X,T109_Y,T109_Z,T109_W,T110_X +,T110_Y,T110_Z,T110_W,T111_X,T111_Y,T111_Z,T111_W,T112_X,T112_Y,T112_Z +,T112_W,T113_X,T113_Y,T113_Z,T113_W,T114_X,T114_Y,T114_Z,T114_W,T115_X +,T115_Y,T115_Z,T115_W,T116_X,T116_Y,T116_Z,T116_W,T117_X,T117_Y,T117_Z +,T117_W,T118_X,T118_Y,T118_Z,T118_W,T119_X,T119_Y,T119_Z,T119_W,T120_X +,T120_Y,T120_Z,T120_W,T121_X,T121_Y,T121_Z,T121_W,T122_X,T122_Y,T122_Z +,T122_W,T123_X,T123_Y,T123_Z,T123_W,T124_X,T124_Y,T124_Z,T124_W,T125_X +,T125_Y,T125_Z,T125_W,T126_X,T126_Y,T126_Z,T126_W,T127_X,T127_Y,T127_Z +,T127_W)>; + +def R600_TReg32_X : RegisterClass <"AMDIL", [f32, i32], 32, (add + T0_X +,T1_X,T2_X,T3_X,T4_X,T5_X,T6_X,T7_X,T8_X,T9_X,T10_X +,T11_X,T12_X,T13_X,T14_X,T15_X,T16_X,T17_X,T18_X,T19_X,T20_X +,T21_X,T22_X,T23_X,T24_X,T25_X,T26_X,T27_X,T28_X,T29_X,T30_X +,T31_X,T32_X,T33_X,T34_X,T35_X,T36_X,T37_X,T38_X,T39_X,T40_X +,T41_X,T42_X,T43_X,T44_X,T45_X,T46_X,T47_X,T48_X,T49_X,T50_X +,T51_X,T52_X,T53_X,T54_X,T55_X,T56_X,T57_X,T58_X,T59_X,T60_X +,T61_X,T62_X,T63_X,T64_X,T65_X,T66_X,T67_X,T68_X,T69_X,T70_X +,T71_X,T72_X,T73_X,T74_X,T75_X,T76_X,T77_X,T78_X,T79_X,T80_X +,T81_X,T82_X,T83_X,T84_X,T85_X,T86_X,T87_X,T88_X,T89_X,T90_X +,T91_X,T92_X,T93_X,T94_X,T95_X,T96_X,T97_X,T98_X,T99_X,T100_X +,T101_X,T102_X,T103_X,T104_X,T105_X,T106_X,T107_X,T108_X,T109_X,T110_X +,T111_X,T112_X,T113_X,T114_X,T115_X,T116_X,T117_X,T118_X,T119_X,T120_X +,T121_X,T122_X,T123_X,T124_X,T125_X,T126_X,T127_X)>; + +def R600_Reg32 : RegisterClass <"AMDIL", [f32, i32], 32, (add + R600_TReg32, + R600_CReg32, + ZERO, HALF, ONE, ONE_INT, PV_X, ALU_LITERAL_X, NEG_ONE, NEG_HALF)>; + +def R600_Reg128 : RegisterClass<"AMDIL", [v4f32, v4i32], 128, (add + T0_XYZW +,T1_XYZW,T2_XYZW,T3_XYZW,T4_XYZW,T5_XYZW,T6_XYZW,T7_XYZW,T8_XYZW,T9_XYZW,T10_XYZW +,T11_XYZW,T12_XYZW,T13_XYZW,T14_XYZW,T15_XYZW,T16_XYZW,T17_XYZW,T18_XYZW,T19_XYZW,T20_XYZW +,T21_XYZW,T22_XYZW,T23_XYZW,T24_XYZW,T25_XYZW,T26_XYZW,T27_XYZW,T28_XYZW,T29_XYZW,T30_XYZW +,T31_XYZW,T32_XYZW,T33_XYZW,T34_XYZW,T35_XYZW,T36_XYZW,T37_XYZW,T38_XYZW,T39_XYZW,T40_XYZW +,T41_XYZW,T42_XYZW,T43_XYZW,T44_XYZW,T45_XYZW,T46_XYZW,T47_XYZW,T48_XYZW,T49_XYZW,T50_XYZW +,T51_XYZW,T52_XYZW,T53_XYZW,T54_XYZW,T55_XYZW,T56_XYZW,T57_XYZW,T58_XYZW,T59_XYZW,T60_XYZW +,T61_XYZW,T62_XYZW,T63_XYZW,T64_XYZW,T65_XYZW,T66_XYZW,T67_XYZW,T68_XYZW,T69_XYZW,T70_XYZW +,T71_XYZW,T72_XYZW,T73_XYZW,T74_XYZW,T75_XYZW,T76_XYZW,T77_XYZW,T78_XYZW,T79_XYZW,T80_XYZW +,T81_XYZW,T82_XYZW,T83_XYZW,T84_XYZW,T85_XYZW,T86_XYZW,T87_XYZW,T88_XYZW,T89_XYZW,T90_XYZW +,T91_XYZW,T92_XYZW,T93_XYZW,T94_XYZW,T95_XYZW,T96_XYZW,T97_XYZW,T98_XYZW,T99_XYZW,T100_XYZW +,T101_XYZW,T102_XYZW,T103_XYZW,T104_XYZW,T105_XYZW,T106_XYZW,T107_XYZW,T108_XYZW,T109_XYZW,T110_XYZW +,T111_XYZW,T112_XYZW,T113_XYZW,T114_XYZW,T115_XYZW,T116_XYZW,T117_XYZW,T118_XYZW,T119_XYZW,T120_XYZW +,T121_XYZW,T122_XYZW,T123_XYZW,T124_XYZW,T125_XYZW,T126_XYZW,T127_XYZW)> +{ + let CopyCost = -1; +} + diff --git a/lib/Target/AMDIL/R600Schedule.td b/lib/Target/AMDIL/R600Schedule.td new file mode 100644 index 00000000000..d1957903d87 --- /dev/null +++ b/lib/Target/AMDIL/R600Schedule.td @@ -0,0 +1,36 @@ +//===-- R600Schedule.td - R600 Scheduling definitions ------*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// R600 has a VLIW architecture. On pre-cayman cards there are 5 instruction +// slots ALU.X, ALU.Y, ALU.Z, ALU.W, and TRANS. For cayman cards, the TRANS +// slot has been removed. +// +//===----------------------------------------------------------------------===// + + +def ALU_X : FuncUnit; +def ALU_Y : FuncUnit; +def ALU_Z : FuncUnit; +def ALU_W : FuncUnit; +def TRANS : FuncUnit; + + +def AnyALU : InstrItinClass; +def VecALU : InstrItinClass; +def TransALU : InstrItinClass; + +def R600_EG_Itin : ProcessorItineraries < + [ALU_X, ALU_Y, ALU_Z, ALU_W, TRANS], + [], + [ + InstrItinData]>, + InstrItinData]>, + InstrItinData]> + ] +>; diff --git a/lib/Target/AMDIL/SIGenRegisterInfo.pl b/lib/Target/AMDIL/SIGenRegisterInfo.pl new file mode 100644 index 00000000000..9f01c076b1a --- /dev/null +++ b/lib/Target/AMDIL/SIGenRegisterInfo.pl @@ -0,0 +1,282 @@ +#===-- SIGenRegisterInfo.pl - Script for generating register info files ----===# +# +# The LLVM Compiler Infrastructure +# +# This file is distributed under the University of Illinois Open Source +# License. See LICENSE.TXT for details. +# +#===------------------------------------------------------------------------===# +# +# This perl script prints to stdout .td code to be used as SIRegisterInfo.td +# it also generates a file called SIHwRegInfo.include, which contains helper +# functions for determining the hw encoding of registers. +# +#===------------------------------------------------------------------------===# + +use strict; +use warnings; + +my $SGPR_COUNT = 104; +my $VGPR_COUNT = 256; + +my $SGPR_MAX_IDX = $SGPR_COUNT - 1; +my $VGPR_MAX_IDX = $VGPR_COUNT - 1; + +my $INDEX_FILE = defined($ARGV[0]) ? $ARGV[0] : ''; + +print < : Register { + let Namespace = "AMDIL"; +} + +class SI_64 subregs> : RegisterWithSubRegs { + let Namespace = "AMDIL"; + let SubRegIndices = [low, high]; +} + +class SI_128 subregs> : RegisterWithSubRegs { + let Namespace = "AMDIL"; + let SubRegIndices = [sel_x, sel_y, sel_z, sel_w]; +} + +class SI_256 subregs> : RegisterWithSubRegs { + let Namespace = "AMDIL"; + let SubRegIndices = [sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7]; +} + +class SGPR_32 num, string name> : SIReg { + field bits<8> Num; + + let Num = num; +} + + +class VGPR_32 num, string name, Register gprf32_alias> : SIReg { + field bits<9> Num; + + let Num = num; + let Aliases = [gprf32_alias]; +} + +class SGPR_64 num, string name, list subregs> : + SI_64 ; + +class VGPR_64 num, string name, list subregs> : + SI_64 ; + +class SGPR_128 num, string name, list subregs> : + SI_128 ; + +class VGPR_128 num, string name, list subregs> : + SI_128 ; + +class SGPR_256 num, string name, list subregs> : + SI_256 ; + +def VCC : SIReg<"VCC">; +def SCC : SIReg<"SCC">; +def SREG_LIT_0 : SIReg <"S LIT 0">; + +def M0 : SIReg <"M0">; + +//Interpolation registers + +def PERSP_SAMPLE_I : SIReg <"PERSP_SAMPLE_I">; +def PERSP_SAMPLE_J : SIReg <"PERSP_SAMPLE_J">; +def PERSP_CENTER_I : SIReg <"PERSP_CENTER_I">; +def PERSP_CENTER_J : SIReg <"PERSP_CENTER_J">; +def PERSP_CENTROID_I : SIReg <"PERSP_CENTROID_I">; +def PERSP_CENTROID_J : SIReg <"PERP_CENTROID_J">; +def PERSP_I_W : SIReg <"PERSP_I_W">; +def PERSP_J_W : SIReg <"PERSP_J_W">; +def PERSP_1_W : SIReg <"PERSP_1_W">; +def LINEAR_SAMPLE_I : SIReg <"LINEAR_SAMPLE_I">; +def LINEAR_SAMPLE_J : SIReg <"LINEAR_SAMPLE_J">; +def LINEAR_CENTER_I : SIReg <"LINEAR_CENTER_I">; +def LINEAR_CENTER_J : SIReg <"LINEAR_CENTER_J">; +def LINEAR_CENTROID_I : SIReg <"LINEAR_CENTROID_I">; +def LINEAR_CENTROID_J : SIReg <"LINEAR_CENTROID_J">; +def LINE_STIPPLE_TEX_COORD : SIReg <"LINE_STIPPLE_TEX_COORD">; +def POS_X_FLOAT : SIReg <"POS_X_FLOAT">; +def POS_Y_FLOAT : SIReg <"POS_Y_FLOAT">; +def POS_Z_FLOAT : SIReg <"POS_Z_FLOAT">; +def POS_W_FLOAT : SIReg <"POS_W_FLOAT">; +def FRONT_FACE : SIReg <"FRONT_FACE">; +def ANCILLARY : SIReg <"ANCILLARY">; +def SAMPLE_COVERAGE : SIReg <"SAMPLE_COVERAGE">; +def POS_FIXED_PT : SIReg <"POS_FIXED_PT">; + +STRING + +#32 bit register + +my @SGPR; +for (my $i = 0; $i < $SGPR_COUNT; $i++) { + print "def SGPR$i : SGPR_32 <$i, \"SGPR$i\">;\n"; + $SGPR[$i] = "SGPR$i"; +} + +my @VGPR; +my @GPRF32; +for (my $i = 0; $i < $VGPR_COUNT; $i++) { + my $gprf32_num = $i + 1; + my $gprf32_name = "R$gprf32_num"; + print "def VGPR$i : VGPR_32 <$i, \"VGPR$i\", $gprf32_name>;\n"; + $VGPR[$i] = "VGPR$i"; + $GPRF32[$i] = $gprf32_name; +} + +print <; + +def VReg_32 : RegisterClass<"AMDIL", [f32, i32], 32, + (add (sequence "VGPR%u", 0, $VGPR_MAX_IDX), + PERSP_SAMPLE_I, PERSP_SAMPLE_J, + PERSP_CENTER_I, PERSP_CENTER_J, + PERSP_CENTROID_I, PERSP_CENTROID_J, + PERSP_I_W, PERSP_J_W, PERSP_1_W, + LINEAR_SAMPLE_I, LINEAR_SAMPLE_J, + LINEAR_CENTER_I, LINEAR_CENTER_J, + LINEAR_CENTROID_I, LINEAR_CENTROID_J, + LINE_STIPPLE_TEX_COORD, + POS_X_FLOAT, + POS_Y_FLOAT, + POS_Z_FLOAT, + POS_W_FLOAT, + FRONT_FACE, + ANCILLARY, + SAMPLE_COVERAGE, + POS_FIXED_PT + ) +>; + +def AllReg_32 : RegisterClass<"AMDIL", [f32, i32], 32, + (add VReg_32, + SReg_32, + (sequence "R%u", 1, $VGPR_COUNT)) +>; + +def CCReg : RegisterClass<"AMDIL", [f32], 32, (add VCC, SCC)>; + +STRING + +my @subregs_64 = ('low', 'high'); +my @subregs_128 = ('sel_x', 'sel_y', 'sel_z', 'sel_w'); +my @subregs_256 = ('sub0', 'sub1', 'sub2', 'sub3', 'sub4', 'sub5', 'sub6', 'sub7'); + +my @SGPR64 = print_sgpr_class(64, \@subregs_64, ('i64', 'iPTRAny')); +my @SGPR128 = print_sgpr_class(128, \@subregs_128, ('v4f32')); +my @SGPR256 = print_sgpr_class(256, \@subregs_256, ('v8i32')); + +my @VGPR64 = print_vgpr_class(64, \@subregs_64, ('i64')); +my @VGPR128 = print_vgpr_class(128, \@subregs_128, ('v4f32')); + + +my $sgpr64_list = join(',', @SGPR64); +my $vgpr64_list = join(',', @VGPR64); +print <; + +STRING + +if ($INDEX_FILE ne '') { + open(my $fh, ">", $INDEX_FILE); + my %hw_values; + + for (my $i = 0; $i <= $#SGPR; $i++) { + push (@{$hw_values{$i}}, $SGPR[$i]); + } + + for (my $i = 0; $i <= $#SGPR64; $i++) { + push (@{$hw_values{$i * 2}}, $SGPR64[$i]) + } + + for (my $i = 0; $i <= $#SGPR128; $i++) { + push (@{$hw_values{$i * 4}}, $SGPR128[$i]); + } + + for (my $i = 0; $i <= $#SGPR256; $i++) { + push (@{$hw_values{$i * 8}}, $SGPR256[$i]); + } + + for (my $i = 0; $i <= $#VGPR; $i++) { + push (@{$hw_values{$i}}, $VGPR[$i]); + } + for (my $i = 0; $i <= $#VGPR64; $i++) { + push (@{$hw_values{$i * 2}}, $VGPR64[$i]); + } + + for (my $i = 0; $i <= $#VGPR128; $i++) { + push (@{$hw_values{$i * 4}}, $VGPR128[$i]); + } + + + print $fh "unsigned SIRegisterInfo::getHWRegNum(unsigned reg) const\n{\n switch(reg) {\n"; + for my $key (keys(%hw_values)) { + my @names = @{$hw_values{$key}}; + for my $regname (@names) { + print $fh " case AMDIL::$regname:\n" + } + print $fh " return $key;\n"; + } + print $fh " default: return 0;\n }\n}\n" +} + + + + +sub print_sgpr_class { + my ($reg_width, $sub_reg_ref, @types) = @_; + return print_reg_class('SReg', 'SGPR', $reg_width, $SGPR_COUNT, $sub_reg_ref, @types); +} + +sub print_vgpr_class { + my ($reg_width, $sub_reg_ref, @types) = @_; + return print_reg_class('VReg', 'VGPR', $reg_width, $VGPR_COUNT, $sub_reg_ref, @types); +} + +sub print_reg_class { + my ($class_prefix, $reg_prefix, $reg_width, $reg_count, $sub_reg_ref, @types) = @_; + my @registers; + my $component_count = $reg_width / 32; + + for (my $i = 0; $i < $reg_count; $i += $component_count) { + my $reg_name = $reg_prefix . $i . '_' . $reg_width; + my @sub_regs; + for (my $idx = 0; $idx < $component_count; $idx++) { + my $sub_idx = $i + $idx; + push(@sub_regs, $reg_prefix . $sub_idx); + } + print "def $reg_name : $reg_prefix\_$reg_width <$i, \"$reg_name\", [ ", join(',', @sub_regs) , "]>;\n"; + if ($i % 10 == 0) { + $reg_name .= "\n"; + } + push (@registers, $reg_name); + } + my $reg_list = join(', ', @registers); + + print "def $class_prefix\_$reg_width : RegisterClass<\"AMDIL\", [" . join (', ', @types) . "], $reg_width,\n (add $reg_list)\n>{\n"; + print "}\n"; + return @registers; +} diff --git a/lib/Target/AMDIL/SIInstrFormats.td b/lib/Target/AMDIL/SIInstrFormats.td new file mode 100644 index 00000000000..de0d4fa39d2 --- /dev/null +++ b/lib/Target/AMDIL/SIInstrFormats.td @@ -0,0 +1,138 @@ +//===-- SIInstrFormats.td - SI Instruction Formats ------------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// SI Instruction format definitions. +// +// Instructions with _32 take 32-bit operands. +// Instructions with _64 take 64-bit operands. +// +// VOP_* instructions can use either a 32-bit or 64-bit encoding. The 32-bit +// encoding is the standard encoding, but instruction that make use of +// any of the instruction modifiers must use the 64-bit encoding. +// +// Instructions with _e32 use the 32-bit encoding. +// Instructions with _e64 use the 64-bit encoding. +// +//===----------------------------------------------------------------------===// + + +class VOP3_32 op, string opName, list pattern> + : VOP3 ; + +class VOP3_64 op, string opName, list pattern> + : VOP3 ; + + +class SOP1_32 op, string opName, list pattern> + : SOP1 ; + +class SOP1_64 op, string opName, list pattern> + : SOP1 ; + +class SOP2_32 op, string opName, list pattern> + : SOP2 ; + +class SOP2_64 op, string opName, list pattern> + : SOP2 ; + +class VOP1_Helper op, RegisterClass vrc, RegisterClass arc, + string opName, list pattern> : + VOP1 < + op, (outs vrc:$dst), (ins arc:$src0), opName, pattern + >; + +multiclass VOP1_32 op, string opName, list pattern, + bits<16> amdil = AMDILInst.NONE> { + + let AMDILOp = amdil in { + def _e32: VOP1_Helper ; + } + + def _e64 : VOP3_32 < + {1, 1, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}}, + opName, [] + >; +} + +multiclass VOP1_64 op, string opName, list pattern> { + + def _e32 : VOP1_Helper ; + + def _e64 : VOP3_64 < + {1, 1, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}}, + opName, [] + >; +} + +class VOP2_Helper op, RegisterClass vrc, RegisterClass arc, + string opName, list pattern> : + VOP2 < + op, (outs vrc:$dst), (ins arc:$src0, vrc:$src1), opName, pattern + >; + +multiclass VOP2_32 op, string opName, list pattern, + bits<16> amdil = AMDILInst.NONE> { + + let AMDILOp = amdil in { + def _e32 : VOP2_Helper ; + } + + def _e64 : VOP3_32 < + {1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}}, + opName, [] + >; +} + +multiclass VOP2_64 op, string opName, list pattern> { + def _e32: VOP2_Helper ; + + def _e64 : VOP3_64 < + {1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}}, + opName, [] + >; +} + +class SOPK_32 op, string opName, list pattern> + : SOPK ; + +class SOPK_64 op, string opName, list pattern> + : SOPK ; + +class VOPC_Helper op, RegisterClass vrc, RegisterClass arc, + string opName, list pattern> : + VOPC < + op, (outs), (ins arc:$src0, vrc:$src1), opName, pattern + >; + +multiclass VOPC_32 op, string opName, list pattern> { + + def _e32 : VOPC_Helper ; + + def _e64 : VOP3_32 < + {0, op{7}, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}}, + opName, [] + >; +} + +multiclass VOPC_64 op, string opName, list pattern> { + + def _e32 : VOPC_Helper ; + + def _e64 : VOP3_64 < + {0, op{7}, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}}, + opName, [] + >; +} + +class SOPC_32 op, string opName, list pattern> + : SOPC ; + +class SOPC_64 op, string opName, list pattern> + : SOPC ; + diff --git a/lib/Target/AMDIL/SIInstrInfo.td b/lib/Target/AMDIL/SIInstrInfo.td new file mode 100644 index 00000000000..435948ff1de --- /dev/null +++ b/lib/Target/AMDIL/SIInstrInfo.td @@ -0,0 +1,463 @@ +//===-- SIInstrInfo.td - SI Instruction Encodings ---------*- tablegen -*--===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + + + +class InstSI pattern> : + AMDGPUInst { + + field bits<4> EncodingType = 0; + field bits<1> NeedWait = 0; + + let TSFlags{3-0} = EncodingType; + let TSFlags{4} = NeedWait; + +} + +class Enc32 pattern> : + InstSI { + + field bits<32> Inst; +} + +class Enc64 pattern> : + InstSI { + + field bits<64> Inst; +} + +class GPR4Align : Operand { + let EncoderMethod = "GPR4AlignEncode"; + let MIOperandInfo = (ops rc:$reg); +} + +class GPR2Align : Operand { + let EncoderMethod = "GPR2AlignEncode"; + let MIOperandInfo = (ops rc:$reg); +} + +def i32Literal : Operand { + let EncoderMethod = "i32LiteralEncode"; +} + +def EXP : Enc64< + (outs), + (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm, + VReg_32:$src0, VReg_32:$src1, VReg_32:$src2, VReg_32:$src3), + "EXP $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3", + [] > { + + bits<4> EN; + bits<6> TGT; + bits<1> COMPR; + bits<1> DONE; + bits<1> VM; + bits<8> VSRC0; + bits<8> VSRC1; + bits<8> VSRC2; + bits<8> VSRC3; + + let Inst{3-0} = EN; + let Inst{9-4} = TGT; + let Inst{10} = COMPR; + let Inst{11} = DONE; + let Inst{12} = VM; + let Inst{31-26} = 0x3e; + let Inst{39-32} = VSRC0; + let Inst{47-40} = VSRC1; + let Inst{55-48} = VSRC2; + let Inst{63-56} = VSRC3; + let EncodingType = 0; //SIInstrEncodingType::EXP + + let NeedWait = 1; + let usesCustomInserter = 1; +} + +class MIMG op, dag outs, dag ins, string asm, list pattern> : + Enc64 { + + bits<8> VDATA; + bits<4> DMASK; + bits<1> UNORM; + bits<1> GLC; + bits<1> DA; + bits<1> R128; + bits<1> TFE; + bits<1> LWE; + bits<1> SLC; + bits<8> VADDR; + bits<5> SRSRC; + bits<5> SSAMP; + + let Inst{11-8} = DMASK; + let Inst{12} = UNORM; + let Inst{13} = GLC; + let Inst{14} = DA; + let Inst{15} = R128; + let Inst{16} = TFE; + let Inst{17} = LWE; + let Inst{24-18} = op; + let Inst{25} = SLC; + let Inst{31-26} = 0x3c; + let Inst{39-32} = VADDR; + let Inst{47-40} = VDATA; + let Inst{52-48} = SRSRC; + let Inst{57-53} = SSAMP; + + let EncodingType = 2; //SIInstrEncodingType::MIMG + + let NeedWait = 1; + let usesCustomInserter = 1; +} + +class MTBUF op, dag outs, dag ins, string asm, list pattern> : + Enc64 { + + bits<8> VDATA; + bits<12> OFFSET; + bits<1> OFFEN; + bits<1> IDXEN; + bits<1> GLC; + bits<1> ADDR64; + bits<4> DFMT; + bits<3> NFMT; + bits<8> VADDR; + bits<5> SRSRC; + bits<1> SLC; + bits<1> TFE; + bits<8> SOFFSET; + + let Inst{11-0} = OFFSET; + let Inst{12} = OFFEN; + let Inst{13} = IDXEN; + let Inst{14} = GLC; + let Inst{15} = ADDR64; + let Inst{18-16} = op; + let Inst{22-19} = DFMT; + let Inst{25-23} = NFMT; + let Inst{31-26} = 0x3a; //encoding + let Inst{39-32} = VADDR; + let Inst{47-40} = VDATA; + let Inst{52-48} = SRSRC; + let Inst{54} = SLC; + let Inst{55} = TFE; + let Inst{63-56} = SOFFSET; + let EncodingType = 3; //SIInstrEncodingType::MTBUF + + let NeedWait = 1; + let usesCustomInserter = 1; + let neverHasSideEffects = 1; +} + +class MUBUF op, dag outs, dag ins, string asm, list pattern> : + Enc64 { + + bits<8> VDATA; + bits<12> OFFSET; + bits<1> OFFEN; + bits<1> IDXEN; + bits<1> GLC; + bits<1> ADDR64; + bits<1> LDS; + bits<8> VADDR; + bits<5> SRSRC; + bits<1> SLC; + bits<1> TFE; + bits<8> SOFFSET; + + let Inst{11-0} = OFFSET; + let Inst{12} = OFFEN; + let Inst{13} = IDXEN; + let Inst{14} = GLC; + let Inst{15} = ADDR64; + let Inst{16} = LDS; + let Inst{24-18} = op; + let Inst{31-26} = 0x38; //encoding + let Inst{39-32} = VADDR; + let Inst{47-40} = VDATA; + let Inst{52-48} = SRSRC; + let Inst{54} = SLC; + let Inst{55} = TFE; + let Inst{63-56} = SOFFSET; + let EncodingType = 4; //SIInstrEncodingType::MUBUF + + let NeedWait = 1; + let usesCustomInserter = 1; + let neverHasSideEffects = 1; +} + +class SMRD op, dag outs, dag ins, string asm, list pattern> : + Enc32 { + + bits<7> SDST; + bits<8> OFFSET; + bits<6> SBASE; + bits<1> IMM = 0; // Determined by subclasses + + let Inst{7-0} = OFFSET; + let Inst{8} = IMM; + let Inst{14-9} = SBASE; + let Inst{21-15} = SDST; + let Inst{26-22} = op; + let Inst{31-27} = 0x18; //encoding + let EncodingType = 5; //SIInstrEncodingType::SMRD + + let NeedWait = 1; + let usesCustomInserter = 1; +} + +class SOP1 op, dag outs, dag ins, string asm, list pattern> : + Enc32 { + + bits<7> SDST; + bits<8> SSRC0; + + let Inst{7-0} = SSRC0; + let Inst{15-8} = op; + let Inst{22-16} = SDST; + let Inst{31-23} = 0x17d; //encoding; + let EncodingType = 6; //SIInstrEncodingType::SOP1 +} + +class SOP2 op, dag outs, dag ins, string asm, list pattern> : + Enc32 { + + bits<7> SDST; + bits<8> SSRC0; + bits<8> SSRC1; + + let Inst{7-0} = SSRC0; + let Inst{15-8} = SSRC1; + let Inst{22-16} = SDST; + let Inst{29-23} = op; + let Inst{31-30} = 0x2; // encoding + let EncodingType = 7; // SIInstrEncodingType::SOP2 +} + +class SOPC op, dag outs, dag ins, string asm, list pattern> : + Enc32 { + + bits<8> SSRC0; + bits<8> SSRC1; + + let Inst{7-0} = SSRC0; + let Inst{15-8} = SSRC1; + let Inst{22-16} = op; + let Inst{31-23} = 0x17e; + let EncodingType = 8; // SIInstrEncodingType::SOPC +} + +class SOPK op, dag outs, dag ins, string asm, list pattern> : + Enc32 { + + bits <7> SDST; + bits <16> SIMM16; + + let Inst{15-0} = SIMM16; + let Inst{22-16} = SDST; + let Inst{27-23} = op; + let Inst{31-28} = 0xb; //encoding + let EncodingType = 9; // SIInstrEncodingType::SOPK +} + +class SOPP op, dag ins, string asm> : Enc32 < + (outs), + ins, + asm, + [] > { + + bits <16> SIMM16; + + let Inst{15-0} = SIMM16; + let Inst{22-16} = op; + let Inst{31-23} = 0x17f; // encoding + let EncodingType = 10; // SIInstrEncodingType::SOPP +} + + +class VINTRP op, dag outs, dag ins, string asm, list pattern> : + Enc32 { + + bits<8> VDST; + bits<8> VSRC; + bits<2> ATTRCHAN; + bits<6> ATTR; + + let Inst{7-0} = VSRC; + let Inst{9-8} = ATTRCHAN; + let Inst{15-10} = ATTR; + let Inst{17-16} = op; + let Inst{25-18} = VDST; + let Inst{31-26} = 0x32; // encoding + let EncodingType = 11; // SIInstrEncodingType::VINTRP + + let Uses = [M0]; +} + +class VOP1 op, dag outs, dag ins, string asm, list pattern> : + Enc32 { + + bits<8> VDST; + bits<9> SRC0; + + let Inst{8-0} = SRC0; + let Inst{16-9} = op; + let Inst{24-17} = VDST; + let Inst{31-25} = 0x3f; //encoding + + let EncodingType = 12; // SIInstrEncodingType::VOP1 + let PostEncoderMethod = "VOPPostEncode"; +} + +class VOP2 op, dag outs, dag ins, string asm, list pattern> : + Enc32 { + + bits<8> VDST; + bits<9> SRC0; + bits<8> VSRC1; + + let Inst{8-0} = SRC0; + let Inst{16-9} = VSRC1; + let Inst{24-17} = VDST; + let Inst{30-25} = op; + let Inst{31} = 0x0; //encoding + + let EncodingType = 13; // SIInstrEncodingType::VOP2 + let PostEncoderMethod = "VOPPostEncode"; +} + +class VOP3 op, dag outs, dag ins, string asm, list pattern> : + Enc64 { + + bits<8> VDST; + bits<9> SRC0; + bits<9> SRC1; + bits<9> SRC2; + bits<3> ABS; + bits<1> CLAMP; + bits<2> OMOD; + bits<3> NEG; + + let Inst{7-0} = VDST; + let Inst{10-8} = ABS; + let Inst{11} = CLAMP; + let Inst{25-17} = op; + let Inst{31-26} = 0x34; //encoding + let Inst{40-32} = SRC0; + let Inst{49-41} = SRC1; + let Inst{58-50} = SRC2; + let Inst{60-59} = OMOD; + let Inst{63-61} = NEG; + + let EncodingType = 14; // SIInstrEncodingType::VOP3 + let PostEncoderMethod = "VOPPostEncode"; +} + +class VOPC op, dag outs, dag ins, string asm, list pattern> : + Enc32 { + + bits<9> SRC0; + bits<8> VSRC1; + + let Inst{8-0} = SRC0; + let Inst{16-9} = VSRC1; + let Inst{24-17} = op; + let Inst{31-25} = 0x3e; + + let EncodingType = 15; //SIInstrEncodingType::VOPC + let PostEncoderMethod = "VOPPostEncode"; + + let Defs = [VCC]; +} + +class MIMG_Load_Helper op, string asm> : MIMG < + op, + (outs VReg_128:$vdata), + (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128, + i1imm:$tfe, i1imm:$lwe, i1imm:$slc, VReg_128:$vaddr, + GPR4Align:$srsrc, GPR4Align:$ssamp), + asm, + [] +>; + +class MUBUF_Load_Helper op, string asm, RegisterClass regClass> : MUBUF < + op, + (outs regClass:$dst), + (ins i16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64, + i1imm:$lds, VReg_32:$vaddr, GPR4Align:$srsrc, i1imm:$slc, + i1imm:$tfe, SReg_32:$soffset), + asm, + []> { + let mayLoad = 1; +} + +class MTBUF_Load_Helper op, string asm, RegisterClass regClass> : MTBUF < + op, + (outs regClass:$dst), + (ins i16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64, + i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr, GPR4Align:$srsrc, + i1imm:$slc, i1imm:$tfe, SReg_32:$soffset), + asm, + []> { + let mayLoad = 1; +} + +class MTBUF_Store_Helper op, string asm, RegisterClass regClass> : MTBUF < + op, + (outs), + (ins regClass:$vdata, i16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, + i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr, + GPR4Align:$srsrc, i1imm:$slc, i1imm:$tfe, SReg_32:$soffset), + asm, + []> { + let mayStore = 1; +} + +/*XXX: We should be able to infer the imm bit based on the arg types */ +multiclass SMRD_Helper op, string asm, RegisterClass dstClass> { + + def _SGPR : SMRD < + op, + (outs dstClass:$dst), + (ins SReg_32:$offset, GPR2Align:$sbase), + asm, + [] + > { + let IMM = 0; + } + + def _IMM : SMRD < + op, + (outs dstClass:$dst), + (ins i32imm:$offset, GPR2Align:$sbase), + asm, + [] + > { + let IMM = 1; + } +} + +class SIOperand : Operand { + let EncoderMethod = "encodeOperand"; + let MIOperandInfo = opInfo; +} + +def IMM8bit : ImmLeaf < + i32, + [{return (int32_t)Imm >= 0 && (int32_t)Imm <= 0xff;}] +>; + +def IMM12bit : ImmLeaf < + i16, + [{return (int16_t)Imm >= 0 && (int16_t)Imm <= 0xfff;}] +>; + +include "SIInstrFormats.td" + +include "SIInstructions.td" diff --git a/lib/Target/AMDIL/SIInstructions.td b/lib/Target/AMDIL/SIInstructions.td new file mode 100644 index 00000000000..57bbc7a5d5a --- /dev/null +++ b/lib/Target/AMDIL/SIInstructions.td @@ -0,0 +1,945 @@ +//===-- SIInstructions.td - SI Instruction Defintions ---------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + + +def isSI : Predicate<"Subtarget.device()" + "->getGeneration() == AMDILDeviceInfo::HD7XXX">; + +let Predicates = [isSI] in { +let Gen = AMDGPUGen.SI in { + +def S_MOV_B32 : SOP1_32 <0x00000003, "S_MOV_B32", []>; +def S_MOV_B64 : SOP1_64 <0x00000004, "S_MOV_B64", []>; +def S_CMOV_B32 : SOP1_32 <0x00000005, "S_CMOV_B32", []>; +def S_CMOV_B64 : SOP1_64 <0x00000006, "S_CMOV_B64", []>; +def S_NOT_B32 : SOP1_32 <0x00000007, "S_NOT_B32", []>; +def S_NOT_B64 : SOP1_64 <0x00000008, "S_NOT_B64", []>; +def S_WQM_B32 : SOP1_32 <0x00000009, "S_WQM_B32", []>; +def S_WQM_B64 : SOP1_64 <0x0000000a, "S_WQM_B64", []>; +def S_BREV_B32 : SOP1_32 <0x0000000b, "S_BREV_B32", []>; +def S_BREV_B64 : SOP1_64 <0x0000000c, "S_BREV_B64", []>; +////def S_BCNT0_I32_B32 : SOP1_BCNT0 <0x0000000d, "S_BCNT0_I32_B32", []>; +////def S_BCNT0_I32_B64 : SOP1_BCNT0 <0x0000000e, "S_BCNT0_I32_B64", []>; +////def S_BCNT1_I32_B32 : SOP1_BCNT1 <0x0000000f, "S_BCNT1_I32_B32", []>; +////def S_BCNT1_I32_B64 : SOP1_BCNT1 <0x00000010, "S_BCNT1_I32_B64", []>; +////def S_FF0_I32_B32 : SOP1_FF0 <0x00000011, "S_FF0_I32_B32", []>; +////def S_FF0_I32_B64 : SOP1_FF0 <0x00000012, "S_FF0_I32_B64", []>; +////def S_FF1_I32_B32 : SOP1_FF1 <0x00000013, "S_FF1_I32_B32", []>; +////def S_FF1_I32_B64 : SOP1_FF1 <0x00000014, "S_FF1_I32_B64", []>; +//def S_FLBIT_I32_B32 : SOP1_32 <0x00000015, "S_FLBIT_I32_B32", []>; +//def S_FLBIT_I32_B64 : SOP1_32 <0x00000016, "S_FLBIT_I32_B64", []>; +def S_FLBIT_I32 : SOP1_32 <0x00000017, "S_FLBIT_I32", []>; +//def S_FLBIT_I32_I64 : SOP1_32 <0x00000018, "S_FLBIT_I32_I64", []>; +//def S_SEXT_I32_I8 : SOP1_32 <0x00000019, "S_SEXT_I32_I8", []>; +//def S_SEXT_I32_I16 : SOP1_32 <0x0000001a, "S_SEXT_I32_I16", []>; +////def S_BITSET0_B32 : SOP1_BITSET0 <0x0000001b, "S_BITSET0_B32", []>; +////def S_BITSET0_B64 : SOP1_BITSET0 <0x0000001c, "S_BITSET0_B64", []>; +////def S_BITSET1_B32 : SOP1_BITSET1 <0x0000001d, "S_BITSET1_B32", []>; +////def S_BITSET1_B64 : SOP1_BITSET1 <0x0000001e, "S_BITSET1_B64", []>; +def S_GETPC_B64 : SOP1_64 <0x0000001f, "S_GETPC_B64", []>; +def S_SETPC_B64 : SOP1_64 <0x00000020, "S_SETPC_B64", []>; +def S_SWAPPC_B64 : SOP1_64 <0x00000021, "S_SWAPPC_B64", []>; +def S_RFE_B64 : SOP1_64 <0x00000022, "S_RFE_B64", []>; +def S_AND_SAVEEXEC_B64 : SOP1_64 <0x00000024, "S_AND_SAVEEXEC_B64", []>; +def S_OR_SAVEEXEC_B64 : SOP1_64 <0x00000025, "S_OR_SAVEEXEC_B64", []>; +def S_XOR_SAVEEXEC_B64 : SOP1_64 <0x00000026, "S_XOR_SAVEEXEC_B64", []>; +////def S_ANDN2_SAVEEXEC_B64 : SOP1_ANDN2 <0x00000027, "S_ANDN2_SAVEEXEC_B64", []>; +////def S_ORN2_SAVEEXEC_B64 : SOP1_ORN2 <0x00000028, "S_ORN2_SAVEEXEC_B64", []>; +def S_NAND_SAVEEXEC_B64 : SOP1_64 <0x00000029, "S_NAND_SAVEEXEC_B64", []>; +def S_NOR_SAVEEXEC_B64 : SOP1_64 <0x0000002a, "S_NOR_SAVEEXEC_B64", []>; +def S_XNOR_SAVEEXEC_B64 : SOP1_64 <0x0000002b, "S_XNOR_SAVEEXEC_B64", []>; +def S_QUADMASK_B32 : SOP1_32 <0x0000002c, "S_QUADMASK_B32", []>; +def S_QUADMASK_B64 : SOP1_64 <0x0000002d, "S_QUADMASK_B64", []>; +def S_MOVRELS_B32 : SOP1_32 <0x0000002e, "S_MOVRELS_B32", []>; +def S_MOVRELS_B64 : SOP1_64 <0x0000002f, "S_MOVRELS_B64", []>; +def S_MOVRELD_B32 : SOP1_32 <0x00000030, "S_MOVRELD_B32", []>; +def S_MOVRELD_B64 : SOP1_64 <0x00000031, "S_MOVRELD_B64", []>; +//def S_CBRANCH_JOIN : SOP1_ <0x00000032, "S_CBRANCH_JOIN", []>; +def S_MOV_REGRD_B32 : SOP1_32 <0x00000033, "S_MOV_REGRD_B32", []>; +def S_ABS_I32 : SOP1_32 <0x00000034, "S_ABS_I32", []>; +def S_MOV_FED_B32 : SOP1_32 <0x00000035, "S_MOV_FED_B32", []>; +def S_MOVK_I32 : SOPK_32 <0x00000000, "S_MOVK_I32", []>; +def S_CMOVK_I32 : SOPK_32 <0x00000002, "S_CMOVK_I32", []>; +def S_CMPK_EQ_I32 : SOPK_32 <0x00000003, "S_CMPK_EQ_I32", []>; +def S_CMPK_LG_I32 : SOPK_32 <0x00000004, "S_CMPK_LG_I32", []>; +def S_CMPK_GT_I32 : SOPK_32 <0x00000005, "S_CMPK_GT_I32", []>; +def S_CMPK_GE_I32 : SOPK_32 <0x00000006, "S_CMPK_GE_I32", []>; +def S_CMPK_LT_I32 : SOPK_32 <0x00000007, "S_CMPK_LT_I32", []>; +def S_CMPK_LE_I32 : SOPK_32 <0x00000008, "S_CMPK_LE_I32", []>; +def S_CMPK_EQ_U32 : SOPK_32 <0x00000009, "S_CMPK_EQ_U32", []>; +def S_CMPK_LG_U32 : SOPK_32 <0x0000000a, "S_CMPK_LG_U32", []>; +def S_CMPK_GT_U32 : SOPK_32 <0x0000000b, "S_CMPK_GT_U32", []>; +def S_CMPK_GE_U32 : SOPK_32 <0x0000000c, "S_CMPK_GE_U32", []>; +def S_CMPK_LT_U32 : SOPK_32 <0x0000000d, "S_CMPK_LT_U32", []>; +def S_CMPK_LE_U32 : SOPK_32 <0x0000000e, "S_CMPK_LE_U32", []>; +def S_ADDK_I32 : SOPK_32 <0x0000000f, "S_ADDK_I32", []>; +def S_MULK_I32 : SOPK_32 <0x00000010, "S_MULK_I32", []>; +//def S_CBRANCH_I_FORK : SOPK_ <0x00000011, "S_CBRANCH_I_FORK", []>; +def S_GETREG_B32 : SOPK_32 <0x00000012, "S_GETREG_B32", []>; +def S_SETREG_B32 : SOPK_32 <0x00000013, "S_SETREG_B32", []>; +def S_GETREG_REGRD_B32 : SOPK_32 <0x00000014, "S_GETREG_REGRD_B32", []>; +//def S_SETREG_IMM32_B32 : SOPK_32 <0x00000015, "S_SETREG_IMM32_B32", []>; +//def EXP : EXP_ <0x00000000, "EXP", []>; +defm V_CMP_F_F32 : VOPC_32 <0x00000000, "V_CMP_F_F32", []>; +defm V_CMP_LT_F32 : VOPC_32 <0x00000001, "V_CMP_LT_F32", []>; +defm V_CMP_EQ_F32 : VOPC_32 <0x00000002, "V_CMP_EQ_F32", []>; +defm V_CMP_LE_F32 : VOPC_32 <0x00000003, "V_CMP_LE_F32", []>; +defm V_CMP_GT_F32 : VOPC_32 <0x00000004, "V_CMP_GT_F32", []>; +defm V_CMP_LG_F32 : VOPC_32 <0x00000005, "V_CMP_LG_F32", []>; +defm V_CMP_GE_F32 : VOPC_32 <0x00000006, "V_CMP_GE_F32", []>; +defm V_CMP_O_F32 : VOPC_32 <0x00000007, "V_CMP_O_F32", []>; +defm V_CMP_U_F32 : VOPC_32 <0x00000008, "V_CMP_U_F32", []>; +defm V_CMP_NGE_F32 : VOPC_32 <0x00000009, "V_CMP_NGE_F32", []>; +defm V_CMP_NLG_F32 : VOPC_32 <0x0000000a, "V_CMP_NLG_F32", []>; +defm V_CMP_NGT_F32 : VOPC_32 <0x0000000b, "V_CMP_NGT_F32", []>; +defm V_CMP_NLE_F32 : VOPC_32 <0x0000000c, "V_CMP_NLE_F32", []>; +defm V_CMP_NEQ_F32 : VOPC_32 <0x0000000d, "V_CMP_NEQ_F32", []>; +defm V_CMP_NLT_F32 : VOPC_32 <0x0000000e, "V_CMP_NLT_F32", []>; +defm V_CMP_TRU_F32 : VOPC_32 <0x0000000f, "V_CMP_TRU_F32", []>; +defm V_CMPX_F_F32 : VOPC_32 <0x00000010, "V_CMPX_F_F32", []>; +defm V_CMPX_LT_F32 : VOPC_32 <0x00000011, "V_CMPX_LT_F32", []>; +defm V_CMPX_EQ_F32 : VOPC_32 <0x00000012, "V_CMPX_EQ_F32", []>; +defm V_CMPX_LE_F32 : VOPC_32 <0x00000013, "V_CMPX_LE_F32", []>; +defm V_CMPX_GT_F32 : VOPC_32 <0x00000014, "V_CMPX_GT_F32", []>; +defm V_CMPX_LG_F32 : VOPC_32 <0x00000015, "V_CMPX_LG_F32", []>; +defm V_CMPX_GE_F32 : VOPC_32 <0x00000016, "V_CMPX_GE_F32", []>; +defm V_CMPX_O_F32 : VOPC_32 <0x00000017, "V_CMPX_O_F32", []>; +defm V_CMPX_U_F32 : VOPC_32 <0x00000018, "V_CMPX_U_F32", []>; +defm V_CMPX_NGE_F32 : VOPC_32 <0x00000019, "V_CMPX_NGE_F32", []>; +defm V_CMPX_NLG_F32 : VOPC_32 <0x0000001a, "V_CMPX_NLG_F32", []>; +defm V_CMPX_NGT_F32 : VOPC_32 <0x0000001b, "V_CMPX_NGT_F32", []>; +defm V_CMPX_NLE_F32 : VOPC_32 <0x0000001c, "V_CMPX_NLE_F32", []>; +defm V_CMPX_NEQ_F32 : VOPC_32 <0x0000001d, "V_CMPX_NEQ_F32", []>; +defm V_CMPX_NLT_F32 : VOPC_32 <0x0000001e, "V_CMPX_NLT_F32", []>; +defm V_CMPX_TRU_F32 : VOPC_32 <0x0000001f, "V_CMPX_TRU_F32", []>; +defm V_CMP_F_F64 : VOPC_64 <0x00000020, "V_CMP_F_F64", []>; +defm V_CMP_LT_F64 : VOPC_64 <0x00000021, "V_CMP_LT_F64", []>; +defm V_CMP_EQ_F64 : VOPC_64 <0x00000022, "V_CMP_EQ_F64", []>; +defm V_CMP_LE_F64 : VOPC_64 <0x00000023, "V_CMP_LE_F64", []>; +defm V_CMP_GT_F64 : VOPC_64 <0x00000024, "V_CMP_GT_F64", []>; +defm V_CMP_LG_F64 : VOPC_64 <0x00000025, "V_CMP_LG_F64", []>; +defm V_CMP_GE_F64 : VOPC_64 <0x00000026, "V_CMP_GE_F64", []>; +defm V_CMP_O_F64 : VOPC_64 <0x00000027, "V_CMP_O_F64", []>; +defm V_CMP_U_F64 : VOPC_64 <0x00000028, "V_CMP_U_F64", []>; +defm V_CMP_NGE_F64 : VOPC_64 <0x00000029, "V_CMP_NGE_F64", []>; +defm V_CMP_NLG_F64 : VOPC_64 <0x0000002a, "V_CMP_NLG_F64", []>; +defm V_CMP_NGT_F64 : VOPC_64 <0x0000002b, "V_CMP_NGT_F64", []>; +defm V_CMP_NLE_F64 : VOPC_64 <0x0000002c, "V_CMP_NLE_F64", []>; +defm V_CMP_NEQ_F64 : VOPC_64 <0x0000002d, "V_CMP_NEQ_F64", []>; +defm V_CMP_NLT_F64 : VOPC_64 <0x0000002e, "V_CMP_NLT_F64", []>; +defm V_CMP_TRU_F64 : VOPC_64 <0x0000002f, "V_CMP_TRU_F64", []>; +defm V_CMPX_F_F64 : VOPC_64 <0x00000030, "V_CMPX_F_F64", []>; +defm V_CMPX_LT_F64 : VOPC_64 <0x00000031, "V_CMPX_LT_F64", []>; +defm V_CMPX_EQ_F64 : VOPC_64 <0x00000032, "V_CMPX_EQ_F64", []>; +defm V_CMPX_LE_F64 : VOPC_64 <0x00000033, "V_CMPX_LE_F64", []>; +defm V_CMPX_GT_F64 : VOPC_64 <0x00000034, "V_CMPX_GT_F64", []>; +defm V_CMPX_LG_F64 : VOPC_64 <0x00000035, "V_CMPX_LG_F64", []>; +defm V_CMPX_GE_F64 : VOPC_64 <0x00000036, "V_CMPX_GE_F64", []>; +defm V_CMPX_O_F64 : VOPC_64 <0x00000037, "V_CMPX_O_F64", []>; +defm V_CMPX_U_F64 : VOPC_64 <0x00000038, "V_CMPX_U_F64", []>; +defm V_CMPX_NGE_F64 : VOPC_64 <0x00000039, "V_CMPX_NGE_F64", []>; +defm V_CMPX_NLG_F64 : VOPC_64 <0x0000003a, "V_CMPX_NLG_F64", []>; +defm V_CMPX_NGT_F64 : VOPC_64 <0x0000003b, "V_CMPX_NGT_F64", []>; +defm V_CMPX_NLE_F64 : VOPC_64 <0x0000003c, "V_CMPX_NLE_F64", []>; +defm V_CMPX_NEQ_F64 : VOPC_64 <0x0000003d, "V_CMPX_NEQ_F64", []>; +defm V_CMPX_NLT_F64 : VOPC_64 <0x0000003e, "V_CMPX_NLT_F64", []>; +defm V_CMPX_TRU_F64 : VOPC_64 <0x0000003f, "V_CMPX_TRU_F64", []>; +defm V_CMPS_F_F32 : VOPC_32 <0x00000040, "V_CMPS_F_F32", []>; +defm V_CMPS_LT_F32 : VOPC_32 <0x00000041, "V_CMPS_LT_F32", []>; +defm V_CMPS_EQ_F32 : VOPC_32 <0x00000042, "V_CMPS_EQ_F32", []>; +defm V_CMPS_LE_F32 : VOPC_32 <0x00000043, "V_CMPS_LE_F32", []>; +defm V_CMPS_GT_F32 : VOPC_32 <0x00000044, "V_CMPS_GT_F32", []>; +defm V_CMPS_LG_F32 : VOPC_32 <0x00000045, "V_CMPS_LG_F32", []>; +defm V_CMPS_GE_F32 : VOPC_32 <0x00000046, "V_CMPS_GE_F32", []>; +defm V_CMPS_O_F32 : VOPC_32 <0x00000047, "V_CMPS_O_F32", []>; +defm V_CMPS_U_F32 : VOPC_32 <0x00000048, "V_CMPS_U_F32", []>; +defm V_CMPS_NGE_F32 : VOPC_32 <0x00000049, "V_CMPS_NGE_F32", []>; +defm V_CMPS_NLG_F32 : VOPC_32 <0x0000004a, "V_CMPS_NLG_F32", []>; +defm V_CMPS_NGT_F32 : VOPC_32 <0x0000004b, "V_CMPS_NGT_F32", []>; +defm V_CMPS_NLE_F32 : VOPC_32 <0x0000004c, "V_CMPS_NLE_F32", []>; +defm V_CMPS_NEQ_F32 : VOPC_32 <0x0000004d, "V_CMPS_NEQ_F32", []>; +defm V_CMPS_NLT_F32 : VOPC_32 <0x0000004e, "V_CMPS_NLT_F32", []>; +defm V_CMPS_TRU_F32 : VOPC_32 <0x0000004f, "V_CMPS_TRU_F32", []>; +defm V_CMPSX_F_F32 : VOPC_32 <0x00000050, "V_CMPSX_F_F32", []>; +defm V_CMPSX_LT_F32 : VOPC_32 <0x00000051, "V_CMPSX_LT_F32", []>; +defm V_CMPSX_EQ_F32 : VOPC_32 <0x00000052, "V_CMPSX_EQ_F32", []>; +defm V_CMPSX_LE_F32 : VOPC_32 <0x00000053, "V_CMPSX_LE_F32", []>; +defm V_CMPSX_GT_F32 : VOPC_32 <0x00000054, "V_CMPSX_GT_F32", []>; +defm V_CMPSX_LG_F32 : VOPC_32 <0x00000055, "V_CMPSX_LG_F32", []>; +defm V_CMPSX_GE_F32 : VOPC_32 <0x00000056, "V_CMPSX_GE_F32", []>; +defm V_CMPSX_O_F32 : VOPC_32 <0x00000057, "V_CMPSX_O_F32", []>; +defm V_CMPSX_U_F32 : VOPC_32 <0x00000058, "V_CMPSX_U_F32", []>; +defm V_CMPSX_NGE_F32 : VOPC_32 <0x00000059, "V_CMPSX_NGE_F32", []>; +defm V_CMPSX_NLG_F32 : VOPC_32 <0x0000005a, "V_CMPSX_NLG_F32", []>; +defm V_CMPSX_NGT_F32 : VOPC_32 <0x0000005b, "V_CMPSX_NGT_F32", []>; +defm V_CMPSX_NLE_F32 : VOPC_32 <0x0000005c, "V_CMPSX_NLE_F32", []>; +defm V_CMPSX_NEQ_F32 : VOPC_32 <0x0000005d, "V_CMPSX_NEQ_F32", []>; +defm V_CMPSX_NLT_F32 : VOPC_32 <0x0000005e, "V_CMPSX_NLT_F32", []>; +defm V_CMPSX_TRU_F32 : VOPC_32 <0x0000005f, "V_CMPSX_TRU_F32", []>; +defm V_CMPS_F_F64 : VOPC_64 <0x00000060, "V_CMPS_F_F64", []>; +defm V_CMPS_LT_F64 : VOPC_64 <0x00000061, "V_CMPS_LT_F64", []>; +defm V_CMPS_EQ_F64 : VOPC_64 <0x00000062, "V_CMPS_EQ_F64", []>; +defm V_CMPS_LE_F64 : VOPC_64 <0x00000063, "V_CMPS_LE_F64", []>; +defm V_CMPS_GT_F64 : VOPC_64 <0x00000064, "V_CMPS_GT_F64", []>; +defm V_CMPS_LG_F64 : VOPC_64 <0x00000065, "V_CMPS_LG_F64", []>; +defm V_CMPS_GE_F64 : VOPC_64 <0x00000066, "V_CMPS_GE_F64", []>; +defm V_CMPS_O_F64 : VOPC_64 <0x00000067, "V_CMPS_O_F64", []>; +defm V_CMPS_U_F64 : VOPC_64 <0x00000068, "V_CMPS_U_F64", []>; +defm V_CMPS_NGE_F64 : VOPC_64 <0x00000069, "V_CMPS_NGE_F64", []>; +defm V_CMPS_NLG_F64 : VOPC_64 <0x0000006a, "V_CMPS_NLG_F64", []>; +defm V_CMPS_NGT_F64 : VOPC_64 <0x0000006b, "V_CMPS_NGT_F64", []>; +defm V_CMPS_NLE_F64 : VOPC_64 <0x0000006c, "V_CMPS_NLE_F64", []>; +defm V_CMPS_NEQ_F64 : VOPC_64 <0x0000006d, "V_CMPS_NEQ_F64", []>; +defm V_CMPS_NLT_F64 : VOPC_64 <0x0000006e, "V_CMPS_NLT_F64", []>; +defm V_CMPS_TRU_F64 : VOPC_64 <0x0000006f, "V_CMPS_TRU_F64", []>; +defm V_CMPSX_F_F64 : VOPC_64 <0x00000070, "V_CMPSX_F_F64", []>; +defm V_CMPSX_LT_F64 : VOPC_64 <0x00000071, "V_CMPSX_LT_F64", []>; +defm V_CMPSX_EQ_F64 : VOPC_64 <0x00000072, "V_CMPSX_EQ_F64", []>; +defm V_CMPSX_LE_F64 : VOPC_64 <0x00000073, "V_CMPSX_LE_F64", []>; +defm V_CMPSX_GT_F64 : VOPC_64 <0x00000074, "V_CMPSX_GT_F64", []>; +defm V_CMPSX_LG_F64 : VOPC_64 <0x00000075, "V_CMPSX_LG_F64", []>; +defm V_CMPSX_GE_F64 : VOPC_64 <0x00000076, "V_CMPSX_GE_F64", []>; +defm V_CMPSX_O_F64 : VOPC_64 <0x00000077, "V_CMPSX_O_F64", []>; +defm V_CMPSX_U_F64 : VOPC_64 <0x00000078, "V_CMPSX_U_F64", []>; +defm V_CMPSX_NGE_F64 : VOPC_64 <0x00000079, "V_CMPSX_NGE_F64", []>; +defm V_CMPSX_NLG_F64 : VOPC_64 <0x0000007a, "V_CMPSX_NLG_F64", []>; +defm V_CMPSX_NGT_F64 : VOPC_64 <0x0000007b, "V_CMPSX_NGT_F64", []>; +defm V_CMPSX_NLE_F64 : VOPC_64 <0x0000007c, "V_CMPSX_NLE_F64", []>; +defm V_CMPSX_NEQ_F64 : VOPC_64 <0x0000007d, "V_CMPSX_NEQ_F64", []>; +defm V_CMPSX_NLT_F64 : VOPC_64 <0x0000007e, "V_CMPSX_NLT_F64", []>; +defm V_CMPSX_TRU_F64 : VOPC_64 <0x0000007f, "V_CMPSX_TRU_F64", []>; +defm V_CMP_F_I32 : VOPC_32 <0x00000080, "V_CMP_F_I32", []>; +defm V_CMP_LT_I32 : VOPC_32 <0x00000081, "V_CMP_LT_I32", []>; +defm V_CMP_EQ_I32 : VOPC_32 <0x00000082, "V_CMP_EQ_I32", []>; +defm V_CMP_LE_I32 : VOPC_32 <0x00000083, "V_CMP_LE_I32", []>; +defm V_CMP_GT_I32 : VOPC_32 <0x00000084, "V_CMP_GT_I32", []>; +defm V_CMP_NE_I32 : VOPC_32 <0x00000085, "V_CMP_NE_I32", []>; +defm V_CMP_GE_I32 : VOPC_32 <0x00000086, "V_CMP_GE_I32", []>; +defm V_CMP_T_I32 : VOPC_32 <0x00000087, "V_CMP_T_I32", []>; +defm V_CMPX_F_I32 : VOPC_32 <0x00000090, "V_CMPX_F_I32", []>; +defm V_CMPX_LT_I32 : VOPC_32 <0x00000091, "V_CMPX_LT_I32", []>; +defm V_CMPX_EQ_I32 : VOPC_32 <0x00000092, "V_CMPX_EQ_I32", []>; +defm V_CMPX_LE_I32 : VOPC_32 <0x00000093, "V_CMPX_LE_I32", []>; +defm V_CMPX_GT_I32 : VOPC_32 <0x00000094, "V_CMPX_GT_I32", []>; +defm V_CMPX_NE_I32 : VOPC_32 <0x00000095, "V_CMPX_NE_I32", []>; +defm V_CMPX_GE_I32 : VOPC_32 <0x00000096, "V_CMPX_GE_I32", []>; +defm V_CMPX_T_I32 : VOPC_32 <0x00000097, "V_CMPX_T_I32", []>; +defm V_CMP_F_I64 : VOPC_64 <0x000000a0, "V_CMP_F_I64", []>; +defm V_CMP_LT_I64 : VOPC_64 <0x000000a1, "V_CMP_LT_I64", []>; +defm V_CMP_EQ_I64 : VOPC_64 <0x000000a2, "V_CMP_EQ_I64", []>; +defm V_CMP_LE_I64 : VOPC_64 <0x000000a3, "V_CMP_LE_I64", []>; +defm V_CMP_GT_I64 : VOPC_64 <0x000000a4, "V_CMP_GT_I64", []>; +defm V_CMP_NE_I64 : VOPC_64 <0x000000a5, "V_CMP_NE_I64", []>; +defm V_CMP_GE_I64 : VOPC_64 <0x000000a6, "V_CMP_GE_I64", []>; +defm V_CMP_T_I64 : VOPC_64 <0x000000a7, "V_CMP_T_I64", []>; +defm V_CMPX_F_I64 : VOPC_64 <0x000000b0, "V_CMPX_F_I64", []>; +defm V_CMPX_LT_I64 : VOPC_64 <0x000000b1, "V_CMPX_LT_I64", []>; +defm V_CMPX_EQ_I64 : VOPC_64 <0x000000b2, "V_CMPX_EQ_I64", []>; +defm V_CMPX_LE_I64 : VOPC_64 <0x000000b3, "V_CMPX_LE_I64", []>; +defm V_CMPX_GT_I64 : VOPC_64 <0x000000b4, "V_CMPX_GT_I64", []>; +defm V_CMPX_NE_I64 : VOPC_64 <0x000000b5, "V_CMPX_NE_I64", []>; +defm V_CMPX_GE_I64 : VOPC_64 <0x000000b6, "V_CMPX_GE_I64", []>; +defm V_CMPX_T_I64 : VOPC_64 <0x000000b7, "V_CMPX_T_I64", []>; +defm V_CMP_F_U32 : VOPC_32 <0x000000c0, "V_CMP_F_U32", []>; +defm V_CMP_LT_U32 : VOPC_32 <0x000000c1, "V_CMP_LT_U32", []>; +defm V_CMP_EQ_U32 : VOPC_32 <0x000000c2, "V_CMP_EQ_U32", []>; +defm V_CMP_LE_U32 : VOPC_32 <0x000000c3, "V_CMP_LE_U32", []>; +defm V_CMP_GT_U32 : VOPC_32 <0x000000c4, "V_CMP_GT_U32", []>; +defm V_CMP_NE_U32 : VOPC_32 <0x000000c5, "V_CMP_NE_U32", []>; +defm V_CMP_GE_U32 : VOPC_32 <0x000000c6, "V_CMP_GE_U32", []>; +defm V_CMP_T_U32 : VOPC_32 <0x000000c7, "V_CMP_T_U32", []>; +defm V_CMPX_F_U32 : VOPC_32 <0x000000d0, "V_CMPX_F_U32", []>; +defm V_CMPX_LT_U32 : VOPC_32 <0x000000d1, "V_CMPX_LT_U32", []>; +defm V_CMPX_EQ_U32 : VOPC_32 <0x000000d2, "V_CMPX_EQ_U32", []>; +defm V_CMPX_LE_U32 : VOPC_32 <0x000000d3, "V_CMPX_LE_U32", []>; +defm V_CMPX_GT_U32 : VOPC_32 <0x000000d4, "V_CMPX_GT_U32", []>; +defm V_CMPX_NE_U32 : VOPC_32 <0x000000d5, "V_CMPX_NE_U32", []>; +defm V_CMPX_GE_U32 : VOPC_32 <0x000000d6, "V_CMPX_GE_U32", []>; +defm V_CMPX_T_U32 : VOPC_32 <0x000000d7, "V_CMPX_T_U32", []>; +defm V_CMP_F_U64 : VOPC_64 <0x000000e0, "V_CMP_F_U64", []>; +defm V_CMP_LT_U64 : VOPC_64 <0x000000e1, "V_CMP_LT_U64", []>; +defm V_CMP_EQ_U64 : VOPC_64 <0x000000e2, "V_CMP_EQ_U64", []>; +defm V_CMP_LE_U64 : VOPC_64 <0x000000e3, "V_CMP_LE_U64", []>; +defm V_CMP_GT_U64 : VOPC_64 <0x000000e4, "V_CMP_GT_U64", []>; +defm V_CMP_NE_U64 : VOPC_64 <0x000000e5, "V_CMP_NE_U64", []>; +defm V_CMP_GE_U64 : VOPC_64 <0x000000e6, "V_CMP_GE_U64", []>; +defm V_CMP_T_U64 : VOPC_64 <0x000000e7, "V_CMP_T_U64", []>; +defm V_CMPX_F_U64 : VOPC_64 <0x000000f0, "V_CMPX_F_U64", []>; +defm V_CMPX_LT_U64 : VOPC_64 <0x000000f1, "V_CMPX_LT_U64", []>; +defm V_CMPX_EQ_U64 : VOPC_64 <0x000000f2, "V_CMPX_EQ_U64", []>; +defm V_CMPX_LE_U64 : VOPC_64 <0x000000f3, "V_CMPX_LE_U64", []>; +defm V_CMPX_GT_U64 : VOPC_64 <0x000000f4, "V_CMPX_GT_U64", []>; +defm V_CMPX_NE_U64 : VOPC_64 <0x000000f5, "V_CMPX_NE_U64", []>; +defm V_CMPX_GE_U64 : VOPC_64 <0x000000f6, "V_CMPX_GE_U64", []>; +defm V_CMPX_T_U64 : VOPC_64 <0x000000f7, "V_CMPX_T_U64", []>; +defm V_CMP_CLASS_F32 : VOPC_32 <0x00000088, "V_CMP_CLASS_F32", []>; +defm V_CMPX_CLASS_F32 : VOPC_32 <0x00000098, "V_CMPX_CLASS_F32", []>; +defm V_CMP_CLASS_F64 : VOPC_64 <0x000000a8, "V_CMP_CLASS_F64", []>; +defm V_CMPX_CLASS_F64 : VOPC_64 <0x000000b8, "V_CMPX_CLASS_F64", []>; +//def BUFFER_LOAD_FORMAT_X : MUBUF_ <0x00000000, "BUFFER_LOAD_FORMAT_X", []>; +//def BUFFER_LOAD_FORMAT_XY : MUBUF_ <0x00000001, "BUFFER_LOAD_FORMAT_XY", []>; +//def BUFFER_LOAD_FORMAT_XYZ : MUBUF_ <0x00000002, "BUFFER_LOAD_FORMAT_XYZ", []>; +def BUFFER_LOAD_FORMAT_XYZW : MUBUF_Load_Helper <0x00000003, "BUFFER_LOAD_FORMAT_XYZW", VReg_128>; +//def BUFFER_STORE_FORMAT_X : MUBUF_ <0x00000004, "BUFFER_STORE_FORMAT_X", []>; +//def BUFFER_STORE_FORMAT_XY : MUBUF_ <0x00000005, "BUFFER_STORE_FORMAT_XY", []>; +//def BUFFER_STORE_FORMAT_XYZ : MUBUF_ <0x00000006, "BUFFER_STORE_FORMAT_XYZ", []>; +//def BUFFER_STORE_FORMAT_XYZW : MUBUF_ <0x00000007, "BUFFER_STORE_FORMAT_XYZW", []>; +//def BUFFER_LOAD_UBYTE : MUBUF_ <0x00000008, "BUFFER_LOAD_UBYTE", []>; +//def BUFFER_LOAD_SBYTE : MUBUF_ <0x00000009, "BUFFER_LOAD_SBYTE", []>; +//def BUFFER_LOAD_USHORT : MUBUF_ <0x0000000a, "BUFFER_LOAD_USHORT", []>; +//def BUFFER_LOAD_SSHORT : MUBUF_ <0x0000000b, "BUFFER_LOAD_SSHORT", []>; +//def BUFFER_LOAD_DWORD : MUBUF_ <0x0000000c, "BUFFER_LOAD_DWORD", []>; +//def BUFFER_LOAD_DWORDX2 : MUBUF_DWORDX2 <0x0000000d, "BUFFER_LOAD_DWORDX2", []>; +//def BUFFER_LOAD_DWORDX4 : MUBUF_DWORDX4 <0x0000000e, "BUFFER_LOAD_DWORDX4", []>; +//def BUFFER_STORE_BYTE : MUBUF_ <0x00000018, "BUFFER_STORE_BYTE", []>; +//def BUFFER_STORE_SHORT : MUBUF_ <0x0000001a, "BUFFER_STORE_SHORT", []>; +//def BUFFER_STORE_DWORD : MUBUF_ <0x0000001c, "BUFFER_STORE_DWORD", []>; +//def BUFFER_STORE_DWORDX2 : MUBUF_DWORDX2 <0x0000001d, "BUFFER_STORE_DWORDX2", []>; +//def BUFFER_STORE_DWORDX4 : MUBUF_DWORDX4 <0x0000001e, "BUFFER_STORE_DWORDX4", []>; +//def BUFFER_ATOMIC_SWAP : MUBUF_ <0x00000030, "BUFFER_ATOMIC_SWAP", []>; +//def BUFFER_ATOMIC_CMPSWAP : MUBUF_ <0x00000031, "BUFFER_ATOMIC_CMPSWAP", []>; +//def BUFFER_ATOMIC_ADD : MUBUF_ <0x00000032, "BUFFER_ATOMIC_ADD", []>; +//def BUFFER_ATOMIC_SUB : MUBUF_ <0x00000033, "BUFFER_ATOMIC_SUB", []>; +//def BUFFER_ATOMIC_RSUB : MUBUF_ <0x00000034, "BUFFER_ATOMIC_RSUB", []>; +//def BUFFER_ATOMIC_SMIN : MUBUF_ <0x00000035, "BUFFER_ATOMIC_SMIN", []>; +//def BUFFER_ATOMIC_UMIN : MUBUF_ <0x00000036, "BUFFER_ATOMIC_UMIN", []>; +//def BUFFER_ATOMIC_SMAX : MUBUF_ <0x00000037, "BUFFER_ATOMIC_SMAX", []>; +//def BUFFER_ATOMIC_UMAX : MUBUF_ <0x00000038, "BUFFER_ATOMIC_UMAX", []>; +//def BUFFER_ATOMIC_AND : MUBUF_ <0x00000039, "BUFFER_ATOMIC_AND", []>; +//def BUFFER_ATOMIC_OR : MUBUF_ <0x0000003a, "BUFFER_ATOMIC_OR", []>; +//def BUFFER_ATOMIC_XOR : MUBUF_ <0x0000003b, "BUFFER_ATOMIC_XOR", []>; +//def BUFFER_ATOMIC_INC : MUBUF_ <0x0000003c, "BUFFER_ATOMIC_INC", []>; +//def BUFFER_ATOMIC_DEC : MUBUF_ <0x0000003d, "BUFFER_ATOMIC_DEC", []>; +//def BUFFER_ATOMIC_FCMPSWAP : MUBUF_ <0x0000003e, "BUFFER_ATOMIC_FCMPSWAP", []>; +//def BUFFER_ATOMIC_FMIN : MUBUF_ <0x0000003f, "BUFFER_ATOMIC_FMIN", []>; +//def BUFFER_ATOMIC_FMAX : MUBUF_ <0x00000040, "BUFFER_ATOMIC_FMAX", []>; +//def BUFFER_ATOMIC_SWAP_X2 : MUBUF_X2 <0x00000050, "BUFFER_ATOMIC_SWAP_X2", []>; +//def BUFFER_ATOMIC_CMPSWAP_X2 : MUBUF_X2 <0x00000051, "BUFFER_ATOMIC_CMPSWAP_X2", []>; +//def BUFFER_ATOMIC_ADD_X2 : MUBUF_X2 <0x00000052, "BUFFER_ATOMIC_ADD_X2", []>; +//def BUFFER_ATOMIC_SUB_X2 : MUBUF_X2 <0x00000053, "BUFFER_ATOMIC_SUB_X2", []>; +//def BUFFER_ATOMIC_RSUB_X2 : MUBUF_X2 <0x00000054, "BUFFER_ATOMIC_RSUB_X2", []>; +//def BUFFER_ATOMIC_SMIN_X2 : MUBUF_X2 <0x00000055, "BUFFER_ATOMIC_SMIN_X2", []>; +//def BUFFER_ATOMIC_UMIN_X2 : MUBUF_X2 <0x00000056, "BUFFER_ATOMIC_UMIN_X2", []>; +//def BUFFER_ATOMIC_SMAX_X2 : MUBUF_X2 <0x00000057, "BUFFER_ATOMIC_SMAX_X2", []>; +//def BUFFER_ATOMIC_UMAX_X2 : MUBUF_X2 <0x00000058, "BUFFER_ATOMIC_UMAX_X2", []>; +//def BUFFER_ATOMIC_AND_X2 : MUBUF_X2 <0x00000059, "BUFFER_ATOMIC_AND_X2", []>; +//def BUFFER_ATOMIC_OR_X2 : MUBUF_X2 <0x0000005a, "BUFFER_ATOMIC_OR_X2", []>; +//def BUFFER_ATOMIC_XOR_X2 : MUBUF_X2 <0x0000005b, "BUFFER_ATOMIC_XOR_X2", []>; +//def BUFFER_ATOMIC_INC_X2 : MUBUF_X2 <0x0000005c, "BUFFER_ATOMIC_INC_X2", []>; +//def BUFFER_ATOMIC_DEC_X2 : MUBUF_X2 <0x0000005d, "BUFFER_ATOMIC_DEC_X2", []>; +//def BUFFER_ATOMIC_FCMPSWAP_X2 : MUBUF_X2 <0x0000005e, "BUFFER_ATOMIC_FCMPSWAP_X2", []>; +//def BUFFER_ATOMIC_FMIN_X2 : MUBUF_X2 <0x0000005f, "BUFFER_ATOMIC_FMIN_X2", []>; +//def BUFFER_ATOMIC_FMAX_X2 : MUBUF_X2 <0x00000060, "BUFFER_ATOMIC_FMAX_X2", []>; +//def BUFFER_WBINVL1_SC : MUBUF_WBINVL1 <0x00000070, "BUFFER_WBINVL1_SC", []>; +//def BUFFER_WBINVL1 : MUBUF_WBINVL1 <0x00000071, "BUFFER_WBINVL1", []>; +//def TBUFFER_LOAD_FORMAT_X : MTBUF_ <0x00000000, "TBUFFER_LOAD_FORMAT_X", []>; +//def TBUFFER_LOAD_FORMAT_XY : MTBUF_ <0x00000001, "TBUFFER_LOAD_FORMAT_XY", []>; +//def TBUFFER_LOAD_FORMAT_XYZ : MTBUF_ <0x00000002, "TBUFFER_LOAD_FORMAT_XYZ", []>; +def TBUFFER_LOAD_FORMAT_XYZW : MTBUF_Load_Helper <0x00000003, "TBUFFER_LOAD_FORMAT_XYZW", VReg_128>; +//def TBUFFER_STORE_FORMAT_X : MTBUF_ <0x00000004, "TBUFFER_STORE_FORMAT_X", []>; +//def TBUFFER_STORE_FORMAT_XY : MTBUF_ <0x00000005, "TBUFFER_STORE_FORMAT_XY", []>; +//def TBUFFER_STORE_FORMAT_XYZ : MTBUF_ <0x00000006, "TBUFFER_STORE_FORMAT_XYZ", []>; +//def TBUFFER_STORE_FORMAT_XYZW : MTBUF_ <0x00000007, "TBUFFER_STORE_FORMAT_XYZW", []>; + +let mayLoad = 0, neverHasSideEffects = 1 in { + +defm S_LOAD_DWORD : SMRD_Helper <0x00000000, "S_LOAD_DWORD", SReg_32>; +//def S_LOAD_DWORDX2 : SMRD_DWORDX2 <0x00000001, "S_LOAD_DWORDX2", []>; +defm S_LOAD_DWORDX4 : SMRD_Helper <0x00000002, "S_LOAD_DWORDX4", SReg_128>; +defm S_LOAD_DWORDX8 : SMRD_Helper <0x00000003, "S_LOAD_DWORDX8", SReg_256>; +//def S_LOAD_DWORDX16 : SMRD_DWORDX16 <0x00000004, "S_LOAD_DWORDX16", []>; +//def S_BUFFER_LOAD_DWORD : SMRD_ <0x00000008, "S_BUFFER_LOAD_DWORD", []>; +//def S_BUFFER_LOAD_DWORDX2 : SMRD_DWORDX2 <0x00000009, "S_BUFFER_LOAD_DWORDX2", []>; +//def S_BUFFER_LOAD_DWORDX4 : SMRD_DWORDX4 <0x0000000a, "S_BUFFER_LOAD_DWORDX4", []>; +//def S_BUFFER_LOAD_DWORDX8 : SMRD_DWORDX8 <0x0000000b, "S_BUFFER_LOAD_DWORDX8", []>; +//def S_BUFFER_LOAD_DWORDX16 : SMRD_DWORDX16 <0x0000000c, "S_BUFFER_LOAD_DWORDX16", []>; + +} // End mayLoad, neverHasSideEffects + +//def S_MEMTIME : SMRD_ <0x0000001e, "S_MEMTIME", []>; +//def S_DCACHE_INV : SMRD_ <0x0000001f, "S_DCACHE_INV", []>; +//def IMAGE_LOAD : MIMG_NoPattern_ <"IMAGE_LOAD", 0x00000000>; +//def IMAGE_LOAD_MIP : MIMG_NoPattern_ <"IMAGE_LOAD_MIP", 0x00000001>; +//def IMAGE_LOAD_PCK : MIMG_NoPattern_ <"IMAGE_LOAD_PCK", 0x00000002>; +//def IMAGE_LOAD_PCK_SGN : MIMG_NoPattern_ <"IMAGE_LOAD_PCK_SGN", 0x00000003>; +//def IMAGE_LOAD_MIP_PCK : MIMG_NoPattern_ <"IMAGE_LOAD_MIP_PCK", 0x00000004>; +//def IMAGE_LOAD_MIP_PCK_SGN : MIMG_NoPattern_ <"IMAGE_LOAD_MIP_PCK_SGN", 0x00000005>; +//def IMAGE_STORE : MIMG_NoPattern_ <"IMAGE_STORE", 0x00000008>; +//def IMAGE_STORE_MIP : MIMG_NoPattern_ <"IMAGE_STORE_MIP", 0x00000009>; +//def IMAGE_STORE_PCK : MIMG_NoPattern_ <"IMAGE_STORE_PCK", 0x0000000a>; +//def IMAGE_STORE_MIP_PCK : MIMG_NoPattern_ <"IMAGE_STORE_MIP_PCK", 0x0000000b>; +//def IMAGE_GET_RESINFO : MIMG_NoPattern_ <"IMAGE_GET_RESINFO", 0x0000000e>; +//def IMAGE_ATOMIC_SWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_SWAP", 0x0000000f>; +//def IMAGE_ATOMIC_CMPSWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_CMPSWAP", 0x00000010>; +//def IMAGE_ATOMIC_ADD : MIMG_NoPattern_ <"IMAGE_ATOMIC_ADD", 0x00000011>; +//def IMAGE_ATOMIC_SUB : MIMG_NoPattern_ <"IMAGE_ATOMIC_SUB", 0x00000012>; +//def IMAGE_ATOMIC_RSUB : MIMG_NoPattern_ <"IMAGE_ATOMIC_RSUB", 0x00000013>; +//def IMAGE_ATOMIC_SMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_SMIN", 0x00000014>; +//def IMAGE_ATOMIC_UMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_UMIN", 0x00000015>; +//def IMAGE_ATOMIC_SMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_SMAX", 0x00000016>; +//def IMAGE_ATOMIC_UMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_UMAX", 0x00000017>; +//def IMAGE_ATOMIC_AND : MIMG_NoPattern_ <"IMAGE_ATOMIC_AND", 0x00000018>; +//def IMAGE_ATOMIC_OR : MIMG_NoPattern_ <"IMAGE_ATOMIC_OR", 0x00000019>; +//def IMAGE_ATOMIC_XOR : MIMG_NoPattern_ <"IMAGE_ATOMIC_XOR", 0x0000001a>; +//def IMAGE_ATOMIC_INC : MIMG_NoPattern_ <"IMAGE_ATOMIC_INC", 0x0000001b>; +//def IMAGE_ATOMIC_DEC : MIMG_NoPattern_ <"IMAGE_ATOMIC_DEC", 0x0000001c>; +//def IMAGE_ATOMIC_FCMPSWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_FCMPSWAP", 0x0000001d>; +//def IMAGE_ATOMIC_FMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_FMIN", 0x0000001e>; +//def IMAGE_ATOMIC_FMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_FMAX", 0x0000001f>; +def IMAGE_SAMPLE : MIMG_Load_Helper <0x00000020, "IMAGE_SAMPLE">; +//def IMAGE_SAMPLE_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_CL", 0x00000021>; +//def IMAGE_SAMPLE_D : MIMG_NoPattern_ <"IMAGE_SAMPLE_D", 0x00000022>; +//def IMAGE_SAMPLE_D_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_D_CL", 0x00000023>; +//def IMAGE_SAMPLE_L : MIMG_NoPattern_ <"IMAGE_SAMPLE_L", 0x00000024>; +//def IMAGE_SAMPLE_B : MIMG_NoPattern_ <"IMAGE_SAMPLE_B", 0x00000025>; +//def IMAGE_SAMPLE_B_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_B_CL", 0x00000026>; +//def IMAGE_SAMPLE_LZ : MIMG_NoPattern_ <"IMAGE_SAMPLE_LZ", 0x00000027>; +//def IMAGE_SAMPLE_C : MIMG_NoPattern_ <"IMAGE_SAMPLE_C", 0x00000028>; +//def IMAGE_SAMPLE_C_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CL", 0x00000029>; +//def IMAGE_SAMPLE_C_D : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D", 0x0000002a>; +//def IMAGE_SAMPLE_C_D_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D_CL", 0x0000002b>; +//def IMAGE_SAMPLE_C_L : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_L", 0x0000002c>; +//def IMAGE_SAMPLE_C_B : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B", 0x0000002d>; +//def IMAGE_SAMPLE_C_B_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B_CL", 0x0000002e>; +//def IMAGE_SAMPLE_C_LZ : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_LZ", 0x0000002f>; +//def IMAGE_SAMPLE_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_O", 0x00000030>; +//def IMAGE_SAMPLE_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_CL_O", 0x00000031>; +//def IMAGE_SAMPLE_D_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_D_O", 0x00000032>; +//def IMAGE_SAMPLE_D_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_D_CL_O", 0x00000033>; +//def IMAGE_SAMPLE_L_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_L_O", 0x00000034>; +//def IMAGE_SAMPLE_B_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_B_O", 0x00000035>; +//def IMAGE_SAMPLE_B_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_B_CL_O", 0x00000036>; +//def IMAGE_SAMPLE_LZ_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_LZ_O", 0x00000037>; +//def IMAGE_SAMPLE_C_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_O", 0x00000038>; +//def IMAGE_SAMPLE_C_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CL_O", 0x00000039>; +//def IMAGE_SAMPLE_C_D_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D_O", 0x0000003a>; +//def IMAGE_SAMPLE_C_D_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D_CL_O", 0x0000003b>; +//def IMAGE_SAMPLE_C_L_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_L_O", 0x0000003c>; +//def IMAGE_SAMPLE_C_B_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B_O", 0x0000003d>; +//def IMAGE_SAMPLE_C_B_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B_CL_O", 0x0000003e>; +//def IMAGE_SAMPLE_C_LZ_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_LZ_O", 0x0000003f>; +//def IMAGE_GATHER4 : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4", 0x00000040>; +//def IMAGE_GATHER4_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_CL", 0x00000041>; +//def IMAGE_GATHER4_L : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_L", 0x00000044>; +//def IMAGE_GATHER4_B : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B", 0x00000045>; +//def IMAGE_GATHER4_B_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B_CL", 0x00000046>; +//def IMAGE_GATHER4_LZ : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_LZ", 0x00000047>; +//def IMAGE_GATHER4_C : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C", 0x00000048>; +//def IMAGE_GATHER4_C_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_CL", 0x00000049>; +//def IMAGE_GATHER4_C_L : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_L", 0x0000004c>; +//def IMAGE_GATHER4_C_B : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B", 0x0000004d>; +//def IMAGE_GATHER4_C_B_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B_CL", 0x0000004e>; +//def IMAGE_GATHER4_C_LZ : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_LZ", 0x0000004f>; +//def IMAGE_GATHER4_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_O", 0x00000050>; +//def IMAGE_GATHER4_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_CL_O", 0x00000051>; +//def IMAGE_GATHER4_L_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_L_O", 0x00000054>; +//def IMAGE_GATHER4_B_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B_O", 0x00000055>; +//def IMAGE_GATHER4_B_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B_CL_O", 0x00000056>; +//def IMAGE_GATHER4_LZ_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_LZ_O", 0x00000057>; +//def IMAGE_GATHER4_C_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_O", 0x00000058>; +//def IMAGE_GATHER4_C_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_CL_O", 0x00000059>; +//def IMAGE_GATHER4_C_L_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_L_O", 0x0000005c>; +//def IMAGE_GATHER4_C_B_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B_O", 0x0000005d>; +//def IMAGE_GATHER4_C_B_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B_CL_O", 0x0000005e>; +//def IMAGE_GATHER4_C_LZ_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_LZ_O", 0x0000005f>; +//def IMAGE_GET_LOD : MIMG_NoPattern_ <"IMAGE_GET_LOD", 0x00000060>; +//def IMAGE_SAMPLE_CD : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD", 0x00000068>; +//def IMAGE_SAMPLE_CD_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD_CL", 0x00000069>; +//def IMAGE_SAMPLE_C_CD : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD", 0x0000006a>; +//def IMAGE_SAMPLE_C_CD_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD_CL", 0x0000006b>; +//def IMAGE_SAMPLE_CD_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD_O", 0x0000006c>; +//def IMAGE_SAMPLE_CD_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD_CL_O", 0x0000006d>; +//def IMAGE_SAMPLE_C_CD_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD_O", 0x0000006e>; +//def IMAGE_SAMPLE_C_CD_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD_CL_O", 0x0000006f>; +//def IMAGE_RSRC256 : MIMG_NoPattern_RSRC256 <"IMAGE_RSRC256", 0x0000007e>; +//def IMAGE_SAMPLER : MIMG_NoPattern_ <"IMAGE_SAMPLER", 0x0000007f>; +//def V_NOP : VOP1_ <0x00000000, "V_NOP", []>; + +let neverHasSideEffects = 1 in { +defm V_MOV_B32 : VOP1_32 <0x00000001, "V_MOV_B32", [], AMDILInst.MOVE_f32>; +} // End neverHasSideEffects +defm V_READFIRSTLANE_B32 : VOP1_32 <0x00000002, "V_READFIRSTLANE_B32", []>; +//defm V_CVT_I32_F64 : VOP1_32 <0x00000003, "V_CVT_I32_F64", []>; +//defm V_CVT_F64_I32 : VOP1_64 <0x00000004, "V_CVT_F64_I32", []>; +//defm V_CVT_F32_I32 : VOP1_32 <0x00000005, "V_CVT_F32_I32", []>; +//defm V_CVT_F32_U32 : VOP1_32 <0x00000006, "V_CVT_F32_U32", []>; +//defm V_CVT_U32_F32 : VOP1_32 <0x00000007, "V_CVT_U32_F32", []>; +//defm V_CVT_I32_F32 : VOP1_32 <0x00000008, "V_CVT_I32_F32", []>; +defm V_MOV_FED_B32 : VOP1_32 <0x00000009, "V_MOV_FED_B32", []>; +////def V_CVT_F16_F32 : VOP1_F16 <0x0000000a, "V_CVT_F16_F32", []>; +//defm V_CVT_F32_F16 : VOP1_32 <0x0000000b, "V_CVT_F32_F16", []>; +//defm V_CVT_RPI_I32_F32 : VOP1_32 <0x0000000c, "V_CVT_RPI_I32_F32", []>; +//defm V_CVT_FLR_I32_F32 : VOP1_32 <0x0000000d, "V_CVT_FLR_I32_F32", []>; +//defm V_CVT_OFF_F32_I4 : VOP1_32 <0x0000000e, "V_CVT_OFF_F32_I4", []>; +//defm V_CVT_F32_F64 : VOP1_32 <0x0000000f, "V_CVT_F32_F64", []>; +//defm V_CVT_F64_F32 : VOP1_64 <0x00000010, "V_CVT_F64_F32", []>; +//defm V_CVT_F32_UBYTE0 : VOP1_32 <0x00000011, "V_CVT_F32_UBYTE0", []>; +//defm V_CVT_F32_UBYTE1 : VOP1_32 <0x00000012, "V_CVT_F32_UBYTE1", []>; +//defm V_CVT_F32_UBYTE2 : VOP1_32 <0x00000013, "V_CVT_F32_UBYTE2", []>; +//defm V_CVT_F32_UBYTE3 : VOP1_32 <0x00000014, "V_CVT_F32_UBYTE3", []>; +//defm V_CVT_U32_F64 : VOP1_32 <0x00000015, "V_CVT_U32_F64", []>; +//defm V_CVT_F64_U32 : VOP1_64 <0x00000016, "V_CVT_F64_U32", []>; +defm V_FRACT_F32 : VOP1_32 <0x00000020, "V_FRACT_F32", []>; +defm V_TRUNC_F32 : VOP1_32 <0x00000021, "V_TRUNC_F32", []>; +defm V_CEIL_F32 : VOP1_32 <0x00000022, "V_CEIL_F32", []>; +defm V_RNDNE_F32 : VOP1_32 <0x00000023, "V_RNDNE_F32", []>; +defm V_FLOOR_F32 : VOP1_32 <0x00000024, "V_FLOOR_F32", []>; +defm V_EXP_F32 : VOP1_32 <0x00000025, "V_EXP_F32", []>; +defm V_LOG_CLAMP_F32 : VOP1_32 <0x00000026, "V_LOG_CLAMP_F32", []>; +defm V_LOG_F32 : VOP1_32 <0x00000027, "V_LOG_F32", []>; +defm V_RCP_CLAMP_F32 : VOP1_32 <0x00000028, "V_RCP_CLAMP_F32", []>; +defm V_RCP_LEGACY_F32 : VOP1_32 <0x00000029, "V_RCP_LEGACY_F32", []>; +defm V_RCP_F32 : VOP1_32 <0x0000002a, "V_RCP_F32", []>; +defm V_RCP_IFLAG_F32 : VOP1_32 <0x0000002b, "V_RCP_IFLAG_F32", []>; +defm V_RSQ_CLAMP_F32 : VOP1_32 <0x0000002c, "V_RSQ_CLAMP_F32", []>; +defm V_RSQ_LEGACY_F32 : VOP1_32 < + 0x0000002d, "V_RSQ_LEGACY_F32", + [(set VReg_32:$dst, (int_AMDGPU_rsq AllReg_32:$src0))] +>; +defm V_RSQ_F32 : VOP1_32 <0x0000002e, "V_RSQ_F32", []>; +defm V_RCP_F64 : VOP1_64 <0x0000002f, "V_RCP_F64", []>; +defm V_RCP_CLAMP_F64 : VOP1_64 <0x00000030, "V_RCP_CLAMP_F64", []>; +defm V_RSQ_F64 : VOP1_64 <0x00000031, "V_RSQ_F64", []>; +defm V_RSQ_CLAMP_F64 : VOP1_64 <0x00000032, "V_RSQ_CLAMP_F64", []>; +defm V_SQRT_F32 : VOP1_32 <0x00000033, "V_SQRT_F32", []>; +defm V_SQRT_F64 : VOP1_64 <0x00000034, "V_SQRT_F64", []>; +defm V_SIN_F32 : VOP1_32 <0x00000035, "V_SIN_F32", []>; +defm V_COS_F32 : VOP1_32 <0x00000036, "V_COS_F32", []>; +defm V_NOT_B32 : VOP1_32 <0x00000037, "V_NOT_B32", []>; +defm V_BFREV_B32 : VOP1_32 <0x00000038, "V_BFREV_B32", []>; +defm V_FFBH_U32 : VOP1_32 <0x00000039, "V_FFBH_U32", []>; +defm V_FFBL_B32 : VOP1_32 <0x0000003a, "V_FFBL_B32", []>; +defm V_FFBH_I32 : VOP1_32 <0x0000003b, "V_FFBH_I32", []>; +//defm V_FREXP_EXP_I32_F64 : VOP1_32 <0x0000003c, "V_FREXP_EXP_I32_F64", []>; +defm V_FREXP_MANT_F64 : VOP1_64 <0x0000003d, "V_FREXP_MANT_F64", []>; +defm V_FRACT_F64 : VOP1_64 <0x0000003e, "V_FRACT_F64", []>; +//defm V_FREXP_EXP_I32_F32 : VOP1_32 <0x0000003f, "V_FREXP_EXP_I32_F32", []>; +defm V_FREXP_MANT_F32 : VOP1_32 <0x00000040, "V_FREXP_MANT_F32", []>; +//def V_CLREXCP : VOP1_ <0x00000041, "V_CLREXCP", []>; +defm V_MOVRELD_B32 : VOP1_32 <0x00000042, "V_MOVRELD_B32", []>; +defm V_MOVRELS_B32 : VOP1_32 <0x00000043, "V_MOVRELS_B32", []>; +defm V_MOVRELSD_B32 : VOP1_32 <0x00000044, "V_MOVRELSD_B32", []>; + +def V_INTERP_P1_F32 : VINTRP < + 0x00000000, + (outs VReg_32:$dst), + (ins VReg_32:$i, i32imm:$attr_chan, i32imm:$attr), + "V_INTERP_P1_F32", + [] +>; + +def V_INTERP_P2_F32 : VINTRP < + 0x00000001, + (outs VReg_32:$dst), + (ins VReg_32:$src0, VReg_32:$j, i32imm:$attr_chan, i32imm:$attr), + "V_INTERP_P2_F32", + []> { + + let Constraints = "$src0 = $dst"; + let DisableEncoding = "$src0"; + +} + +def V_INTERP_MOV_F32 : VINTRP < + 0x00000002, + (outs VReg_32:$dst), + (ins i32imm:$attr_chan, i32imm:$attr), + "V_INTERP_MOV_F32", + []> { + let VSRC = 0; +} + +//def V_INTERP_MOV_F32 : VINTRP_32 <0x00000002, "V_INTERP_MOV_F32", []>; +//def S_NOP : SOPP_ <0x00000000, "S_NOP", []>; +def S_ENDPGM : SOPP <0x00000001, (ins), "S_ENDPGM"> { + let SIMM16 = 0; + let isTerminator = 1; +} +//def S_BRANCH : SOPP_ <0x00000002, "S_BRANCH", []>; +//def S_CBRANCH_SCC0 : SOPP_SCC0 <0x00000004, "S_CBRANCH_SCC0", []>; +//def S_CBRANCH_SCC1 : SOPP_SCC1 <0x00000005, "S_CBRANCH_SCC1", []>; +//def S_CBRANCH_VCCZ : SOPP_ <0x00000006, "S_CBRANCH_VCCZ", []>; +//def S_CBRANCH_VCCNZ : SOPP_ <0x00000007, "S_CBRANCH_VCCNZ", []>; +//def S_CBRANCH_EXECZ : SOPP_ <0x00000008, "S_CBRANCH_EXECZ", []>; +//def S_CBRANCH_EXECNZ : SOPP_ <0x00000009, "S_CBRANCH_EXECNZ", []>; +//def S_BARRIER : SOPP_ <0x0000000a, "S_BARRIER", []>; +def S_WAITCNT : SOPP <0x0000000c, (ins i32imm:$simm16), "S_WAITCNT $simm16">; +//def S_SETHALT : SOPP_ <0x0000000d, "S_SETHALT", []>; +//def S_SLEEP : SOPP_ <0x0000000e, "S_SLEEP", []>; +//def S_SETPRIO : SOPP_ <0x0000000f, "S_SETPRIO", []>; +//def S_SENDMSG : SOPP_ <0x00000010, "S_SENDMSG", []>; +//def S_SENDMSGHALT : SOPP_ <0x00000011, "S_SENDMSGHALT", []>; +//def S_TRAP : SOPP_ <0x00000012, "S_TRAP", []>; +//def S_ICACHE_INV : SOPP_ <0x00000013, "S_ICACHE_INV", []>; +//def S_INCPERFLEVEL : SOPP_ <0x00000014, "S_INCPERFLEVEL", []>; +//def S_DECPERFLEVEL : SOPP_ <0x00000015, "S_DECPERFLEVEL", []>; +//def S_TTRACEDATA : SOPP_ <0x00000016, "S_TTRACEDATA", []>; + +/* XXX: No VOP3 version of this instruction yet */ +def V_CNDMASK_B32 : VOP2_Helper < + 0x00000000, VReg_32, AllReg_32, "V_CNDMASK_B32", []> { + let VDST = 0; + let Uses = [VCC]; +} +defm V_READLANE_B32 : VOP2_32 <0x00000001, "V_READLANE_B32", []>; +defm V_WRITELANE_B32 : VOP2_32 <0x00000002, "V_WRITELANE_B32", []>; + +defm V_ADD_F32 : VOP2_32 <0x00000003, "V_ADD_F32", [], AMDILInst.ADD_f32>; + +defm V_SUB_F32 : VOP2_32 <0x00000004, "V_SUB_F32", []>; +defm V_SUBREV_F32 : VOP2_32 <0x00000005, "V_SUBREV_F32", []>; +defm V_MAC_LEGACY_F32 : VOP2_32 <0x00000006, "V_MAC_LEGACY_F32", []>; +defm V_MUL_LEGACY_F32 : VOP2_32 < + 0x00000007, "V_MUL_LEGACY_F32", + [(set VReg_32:$dst, (int_AMDGPU_mul AllReg_32:$src0, VReg_32:$src1))] +>; +defm V_MUL_F32 : VOP2_32 <0x00000008, "V_MUL_F32", []>; +//defm V_MUL_I32_I24 : VOP2_32 <0x00000009, "V_MUL_I32_I24", []>; +//defm V_MUL_HI_I32_I24 : VOP2_32 <0x0000000a, "V_MUL_HI_I32_I24", []>; +//defm V_MUL_U32_U24 : VOP2_32 <0x0000000b, "V_MUL_U32_U24", []>; +//defm V_MUL_HI_U32_U24 : VOP2_32 <0x0000000c, "V_MUL_HI_U32_U24", []>; +defm V_MIN_LEGACY_F32 : VOP2_32 <0x0000000d, "V_MIN_LEGACY_F32", []>; + +defm V_MAX_LEGACY_F32 : VOP2_32 <0x0000000e, "V_MAX_LEGACY_F32", [], + AMDILInst.MAX_f32>; +defm V_MIN_F32 : VOP2_32 <0x0000000f, "V_MIN_F32", []>; +defm V_MAX_F32 : VOP2_32 <0x00000010, "V_MAX_F32", []>; +defm V_MIN_I32 : VOP2_32 <0x00000011, "V_MIN_I32", []>; +defm V_MAX_I32 : VOP2_32 <0x00000012, "V_MAX_I32", []>; +defm V_MIN_U32 : VOP2_32 <0x00000013, "V_MIN_U32", []>; +defm V_MAX_U32 : VOP2_32 <0x00000014, "V_MAX_U32", []>; +defm V_LSHR_B32 : VOP2_32 <0x00000015, "V_LSHR_B32", []>; +defm V_LSHRREV_B32 : VOP2_32 <0x00000016, "V_LSHRREV_B32", []>; +defm V_ASHR_I32 : VOP2_32 <0x00000017, "V_ASHR_I32", []>; +defm V_ASHRREV_I32 : VOP2_32 <0x00000018, "V_ASHRREV_I32", []>; +defm V_LSHL_B32 : VOP2_32 <0x00000019, "V_LSHL_B32", []>; +defm V_LSHLREV_B32 : VOP2_32 <0x0000001a, "V_LSHLREV_B32", []>; +defm V_AND_B32 : VOP2_32 <0x0000001b, "V_AND_B32", []>; +defm V_OR_B32 : VOP2_32 <0x0000001c, "V_OR_B32", []>; +defm V_XOR_B32 : VOP2_32 <0x0000001d, "V_XOR_B32", []>; +defm V_BFM_B32 : VOP2_32 <0x0000001e, "V_BFM_B32", []>; +defm V_MAC_F32 : VOP2_32 <0x0000001f, "V_MAC_F32", []>; +defm V_MADMK_F32 : VOP2_32 <0x00000020, "V_MADMK_F32", []>; +defm V_MADAK_F32 : VOP2_32 <0x00000021, "V_MADAK_F32", []>; +//defm V_BCNT_U32_B32 : VOP2_32 <0x00000022, "V_BCNT_U32_B32", []>; +//defm V_MBCNT_LO_U32_B32 : VOP2_32 <0x00000023, "V_MBCNT_LO_U32_B32", []>; +//defm V_MBCNT_HI_U32_B32 : VOP2_32 <0x00000024, "V_MBCNT_HI_U32_B32", []>; +defm V_ADD_I32 : VOP2_32 <0x00000025, "V_ADD_I32", []>; +defm V_SUB_I32 : VOP2_32 <0x00000026, "V_SUB_I32", []>; +defm V_SUBREV_I32 : VOP2_32 <0x00000027, "V_SUBREV_I32", []>; +defm V_ADDC_U32 : VOP2_32 <0x00000028, "V_ADDC_U32", []>; +defm V_SUBB_U32 : VOP2_32 <0x00000029, "V_SUBB_U32", []>; +defm V_SUBBREV_U32 : VOP2_32 <0x0000002a, "V_SUBBREV_U32", []>; +defm V_LDEXP_F32 : VOP2_32 <0x0000002b, "V_LDEXP_F32", []>; +////def V_CVT_PKACCUM_U8_F32 : VOP2_U8 <0x0000002c, "V_CVT_PKACCUM_U8_F32", []>; +////def V_CVT_PKNORM_I16_F32 : VOP2_I16 <0x0000002d, "V_CVT_PKNORM_I16_F32", []>; +////def V_CVT_PKNORM_U16_F32 : VOP2_U16 <0x0000002e, "V_CVT_PKNORM_U16_F32", []>; +////def V_CVT_PKRTZ_F16_F32 : VOP2_F16 <0x0000002f, "V_CVT_PKRTZ_F16_F32", []>; +////def V_CVT_PK_U16_U32 : VOP2_U16 <0x00000030, "V_CVT_PK_U16_U32", []>; +////def V_CVT_PK_I16_I32 : VOP2_I16 <0x00000031, "V_CVT_PK_I16_I32", []>; +def S_CMP_EQ_I32 : SOPC_32 <0x00000000, "S_CMP_EQ_I32", []>; +def S_CMP_LG_I32 : SOPC_32 <0x00000001, "S_CMP_LG_I32", []>; +def S_CMP_GT_I32 : SOPC_32 <0x00000002, "S_CMP_GT_I32", []>; +def S_CMP_GE_I32 : SOPC_32 <0x00000003, "S_CMP_GE_I32", []>; +def S_CMP_LT_I32 : SOPC_32 <0x00000004, "S_CMP_LT_I32", []>; +def S_CMP_LE_I32 : SOPC_32 <0x00000005, "S_CMP_LE_I32", []>; +def S_CMP_EQ_U32 : SOPC_32 <0x00000006, "S_CMP_EQ_U32", []>; +def S_CMP_LG_U32 : SOPC_32 <0x00000007, "S_CMP_LG_U32", []>; +def S_CMP_GT_U32 : SOPC_32 <0x00000008, "S_CMP_GT_U32", []>; +def S_CMP_GE_U32 : SOPC_32 <0x00000009, "S_CMP_GE_U32", []>; +def S_CMP_LT_U32 : SOPC_32 <0x0000000a, "S_CMP_LT_U32", []>; +def S_CMP_LE_U32 : SOPC_32 <0x0000000b, "S_CMP_LE_U32", []>; +////def S_BITCMP0_B32 : SOPC_BITCMP0 <0x0000000c, "S_BITCMP0_B32", []>; +////def S_BITCMP1_B32 : SOPC_BITCMP1 <0x0000000d, "S_BITCMP1_B32", []>; +////def S_BITCMP0_B64 : SOPC_BITCMP0 <0x0000000e, "S_BITCMP0_B64", []>; +////def S_BITCMP1_B64 : SOPC_BITCMP1 <0x0000000f, "S_BITCMP1_B64", []>; +//def S_SETVSKIP : SOPC_ <0x00000010, "S_SETVSKIP", []>; + +let neverHasSideEffects = 1 in { + +def V_MAD_LEGACY_F32 : VOP3_32 <0x00000140, "V_MAD_LEGACY_F32", []>; +def V_MAD_F32 : VOP3_32 <0x00000141, "V_MAD_F32", []>; +//def V_MAD_I32_I24 : VOP3_32 <0x00000142, "V_MAD_I32_I24", []>; +//def V_MAD_U32_U24 : VOP3_32 <0x00000143, "V_MAD_U32_U24", []>; + +} // End neverHasSideEffects +def V_CUBEID_F32 : VOP3_32 <0x00000144, "V_CUBEID_F32", []>; +def V_CUBESC_F32 : VOP3_32 <0x00000145, "V_CUBESC_F32", []>; +def V_CUBETC_F32 : VOP3_32 <0x00000146, "V_CUBETC_F32", []>; +def V_CUBEMA_F32 : VOP3_32 <0x00000147, "V_CUBEMA_F32", []>; +def V_BFE_U32 : VOP3_32 <0x00000148, "V_BFE_U32", []>; +def V_BFE_I32 : VOP3_32 <0x00000149, "V_BFE_I32", []>; +def V_BFI_B32 : VOP3_32 <0x0000014a, "V_BFI_B32", []>; +def V_FMA_F32 : VOP3_32 <0x0000014b, "V_FMA_F32", []>; +def V_FMA_F64 : VOP3_64 <0x0000014c, "V_FMA_F64", []>; +//def V_LERP_U8 : VOP3_U8 <0x0000014d, "V_LERP_U8", []>; +def V_ALIGNBIT_B32 : VOP3_32 <0x0000014e, "V_ALIGNBIT_B32", []>; +def V_ALIGNBYTE_B32 : VOP3_32 <0x0000014f, "V_ALIGNBYTE_B32", []>; +def V_MULLIT_F32 : VOP3_32 <0x00000150, "V_MULLIT_F32", []>; +////def V_MIN3_F32 : VOP3_MIN3 <0x00000151, "V_MIN3_F32", []>; +////def V_MIN3_I32 : VOP3_MIN3 <0x00000152, "V_MIN3_I32", []>; +////def V_MIN3_U32 : VOP3_MIN3 <0x00000153, "V_MIN3_U32", []>; +////def V_MAX3_F32 : VOP3_MAX3 <0x00000154, "V_MAX3_F32", []>; +////def V_MAX3_I32 : VOP3_MAX3 <0x00000155, "V_MAX3_I32", []>; +////def V_MAX3_U32 : VOP3_MAX3 <0x00000156, "V_MAX3_U32", []>; +////def V_MED3_F32 : VOP3_MED3 <0x00000157, "V_MED3_F32", []>; +////def V_MED3_I32 : VOP3_MED3 <0x00000158, "V_MED3_I32", []>; +////def V_MED3_U32 : VOP3_MED3 <0x00000159, "V_MED3_U32", []>; +//def V_SAD_U8 : VOP3_U8 <0x0000015a, "V_SAD_U8", []>; +//def V_SAD_HI_U8 : VOP3_U8 <0x0000015b, "V_SAD_HI_U8", []>; +//def V_SAD_U16 : VOP3_U16 <0x0000015c, "V_SAD_U16", []>; +def V_SAD_U32 : VOP3_32 <0x0000015d, "V_SAD_U32", []>; +////def V_CVT_PK_U8_F32 : VOP3_U8 <0x0000015e, "V_CVT_PK_U8_F32", []>; +def V_DIV_FIXUP_F32 : VOP3_32 <0x0000015f, "V_DIV_FIXUP_F32", []>; +def V_DIV_FIXUP_F64 : VOP3_64 <0x00000160, "V_DIV_FIXUP_F64", []>; +def V_LSHL_B64 : VOP3_64 <0x00000161, "V_LSHL_B64", []>; +def V_LSHR_B64 : VOP3_64 <0x00000162, "V_LSHR_B64", []>; +def V_ASHR_I64 : VOP3_64 <0x00000163, "V_ASHR_I64", []>; +def V_ADD_F64 : VOP3_64 <0x00000164, "V_ADD_F64", []>; +def V_MUL_F64 : VOP3_64 <0x00000165, "V_MUL_F64", []>; +def V_MIN_F64 : VOP3_64 <0x00000166, "V_MIN_F64", []>; +def V_MAX_F64 : VOP3_64 <0x00000167, "V_MAX_F64", []>; +def V_LDEXP_F64 : VOP3_64 <0x00000168, "V_LDEXP_F64", []>; +def V_MUL_LO_U32 : VOP3_32 <0x00000169, "V_MUL_LO_U32", []>; +def V_MUL_HI_U32 : VOP3_32 <0x0000016a, "V_MUL_HI_U32", []>; +def V_MUL_LO_I32 : VOP3_32 <0x0000016b, "V_MUL_LO_I32", []>; +def V_MUL_HI_I32 : VOP3_32 <0x0000016c, "V_MUL_HI_I32", []>; +def V_DIV_SCALE_F32 : VOP3_32 <0x0000016d, "V_DIV_SCALE_F32", []>; +def V_DIV_SCALE_F64 : VOP3_64 <0x0000016e, "V_DIV_SCALE_F64", []>; +def V_DIV_FMAS_F32 : VOP3_32 <0x0000016f, "V_DIV_FMAS_F32", []>; +def V_DIV_FMAS_F64 : VOP3_64 <0x00000170, "V_DIV_FMAS_F64", []>; +//def V_MSAD_U8 : VOP3_U8 <0x00000171, "V_MSAD_U8", []>; +//def V_QSAD_U8 : VOP3_U8 <0x00000172, "V_QSAD_U8", []>; +//def V_MQSAD_U8 : VOP3_U8 <0x00000173, "V_MQSAD_U8", []>; +def V_TRIG_PREOP_F64 : VOP3_64 <0x00000174, "V_TRIG_PREOP_F64", []>; +def S_ADD_U32 : SOP2_32 <0x00000000, "S_ADD_U32", []>; +def S_SUB_U32 : SOP2_32 <0x00000001, "S_SUB_U32", []>; +def S_ADD_I32 : SOP2_32 <0x00000002, "S_ADD_I32", []>; +def S_SUB_I32 : SOP2_32 <0x00000003, "S_SUB_I32", []>; +def S_ADDC_U32 : SOP2_32 <0x00000004, "S_ADDC_U32", []>; +def S_SUBB_U32 : SOP2_32 <0x00000005, "S_SUBB_U32", []>; +def S_MIN_I32 : SOP2_32 <0x00000006, "S_MIN_I32", []>; +def S_MIN_U32 : SOP2_32 <0x00000007, "S_MIN_U32", []>; +def S_MAX_I32 : SOP2_32 <0x00000008, "S_MAX_I32", []>; +def S_MAX_U32 : SOP2_32 <0x00000009, "S_MAX_U32", []>; +def S_CSELECT_B32 : SOP2_32 <0x0000000a, "S_CSELECT_B32", []>; +def S_CSELECT_B64 : SOP2_64 <0x0000000b, "S_CSELECT_B64", []>; +def S_AND_B32 : SOP2_32 <0x0000000e, "S_AND_B32", []>; +def S_AND_B64 : SOP2_64 <0x0000000f, "S_AND_B64", []>; +def S_OR_B32 : SOP2_32 <0x00000010, "S_OR_B32", []>; +def S_OR_B64 : SOP2_64 <0x00000011, "S_OR_B64", []>; +def S_XOR_B32 : SOP2_32 <0x00000012, "S_XOR_B32", []>; +def S_XOR_B64 : SOP2_64 <0x00000013, "S_XOR_B64", []>; +////def S_ANDN2_B32 : SOP2_ANDN2 <0x00000014, "S_ANDN2_B32", []>; +////def S_ANDN2_B64 : SOP2_ANDN2 <0x00000015, "S_ANDN2_B64", []>; +////def S_ORN2_B32 : SOP2_ORN2 <0x00000016, "S_ORN2_B32", []>; +////def S_ORN2_B64 : SOP2_ORN2 <0x00000017, "S_ORN2_B64", []>; +def S_NAND_B32 : SOP2_32 <0x00000018, "S_NAND_B32", []>; +def S_NAND_B64 : SOP2_64 <0x00000019, "S_NAND_B64", []>; +def S_NOR_B32 : SOP2_32 <0x0000001a, "S_NOR_B32", []>; +def S_NOR_B64 : SOP2_64 <0x0000001b, "S_NOR_B64", []>; +def S_XNOR_B32 : SOP2_32 <0x0000001c, "S_XNOR_B32", []>; +def S_XNOR_B64 : SOP2_64 <0x0000001d, "S_XNOR_B64", []>; +def S_LSHL_B32 : SOP2_32 <0x0000001e, "S_LSHL_B32", []>; +def S_LSHL_B64 : SOP2_64 <0x0000001f, "S_LSHL_B64", []>; +def S_LSHR_B32 : SOP2_32 <0x00000020, "S_LSHR_B32", []>; +def S_LSHR_B64 : SOP2_64 <0x00000021, "S_LSHR_B64", []>; +def S_ASHR_I32 : SOP2_32 <0x00000022, "S_ASHR_I32", []>; +def S_ASHR_I64 : SOP2_64 <0x00000023, "S_ASHR_I64", []>; +def S_BFM_B32 : SOP2_32 <0x00000024, "S_BFM_B32", []>; +def S_BFM_B64 : SOP2_64 <0x00000025, "S_BFM_B64", []>; +def S_MUL_I32 : SOP2_32 <0x00000026, "S_MUL_I32", []>; +def S_BFE_U32 : SOP2_32 <0x00000027, "S_BFE_U32", []>; +def S_BFE_I32 : SOP2_32 <0x00000028, "S_BFE_I32", []>; +def S_BFE_U64 : SOP2_64 <0x00000029, "S_BFE_U64", []>; +def S_BFE_I64 : SOP2_64 <0x0000002a, "S_BFE_I64", []>; +//def S_CBRANCH_G_FORK : SOP2_ <0x0000002b, "S_CBRANCH_G_FORK", []>; +def S_ABSDIFF_I32 : SOP2_32 <0x0000002c, "S_ABSDIFF_I32", []>; + +def V_MOV_IMM : VOP1 < + 0x1, + (outs VReg_32:$dst), + (ins f32imm:$src0), + "V_MOV_IMM", + [] +>; + +def S_MOV_IMM_I32 : SOP1 < + 0x3, + (outs SReg_32:$dst), + (ins i32Literal:$src0), + "S_MOV_IMM", + [] > { + let neverHasSideEffects = 1; +} + +let isCodeGenOnly = 1, isPseudo = 1 in { + +def SET_M0 : InstSI < + (outs SReg_32:$dst), + (ins i32imm:$src0), + "SET_M0", + [(set SReg_32:$dst, (int_SI_set_M0 imm:$src0))] +>; + +def CONFIG_WRITE : InstSI < + (outs i32imm:$reg), + (ins i32imm:$val), + "CONFIG_WRITE $reg, $val", + [] > { + field bits<32> Inst = 0; +} + +def LOAD_CONST : AMDGPUShaderInst < + (outs GPRF32:$dst), + (ins i32imm:$src), + "LOAD_CONST $dst, $src", + [(set GPRF32:$dst, (int_AMDGPU_load_const imm:$src))] +>; + +let usesCustomInserter = 1 in { + +def SI_V_CNDLT : InstSI < + (outs VReg_32:$dst), + (ins VReg_32:$src0, VReg_32:$src1, VReg_32:$src2), + "SI_V_CNDLT $dst, $src0, $src1, $src2", + [(set VReg_32:$dst, (int_AMDGPU_cndlt VReg_32:$src0, VReg_32:$src1, VReg_32:$src2))] +>; + +def SI_INTERP : InstSI < + (outs VReg_32:$dst), + (ins VReg_32:$i, VReg_32:$j, i32imm:$attr_chan, i32imm:$attr, SReg_32:$params), + "SI_INTERP $dst, $i, $j, $attr_chan, $attr, $params", + [] +>; + +def SI_INTERP_CONST : InstSI < + (outs VReg_32:$dst), + (ins i32imm:$attr_chan, i32imm:$attr, SReg_32:$params), + "SI_INTERP_CONST $dst, $attr_chan, $attr, $params", + [(set VReg_32:$dst, (int_SI_fs_interp_constant imm:$attr_chan, + imm:$attr, SReg_32:$params))] +>; + + +def USE_SGPR_32 : InstSI < + (outs SReg_32:$dst), + (ins i32imm:$src0), + "USE_SGPR_32", + [(set SReg_32:$dst, (int_SI_use_sgpr imm:$src0))] + +> { + field bits<32> Inst = 0; +} + +def USE_SGPR_64 : InstSI < + (outs SReg_64:$dst), + (ins i32imm:$src0), + "USE_SGPR_64", + [(set SReg_64:$dst, (int_SI_use_sgpr imm:$src0))] + +> { + field bits<32> Inst = 0; +} + +def VS_LOAD_BUFFER_INDEX : InstSI < + (outs VReg_32:$dst), + (ins), + "VS_LOAD_BUFFER_INDEX", + [(set VReg_32:$dst, (int_SI_vs_load_buffer_index))]> { + + field bits<32> Inst = 0; +} + +} // end usesCustomInserter + +} // end IsCodeGenOnly, isPseudo + +} // end Gen = AMDGPUGen.SI + +/* int_SI_vs_load_input */ +def : Pat< + (int_SI_vs_load_input SReg_64:$tlst_sgpr, IMM8bit:$t_offset, IMM12bit:$attr_offset, + VReg_32:$buf_idx_vgpr), + (BUFFER_LOAD_FORMAT_XYZW imm:$attr_offset, 0, 1, 0, 0, 0, + VReg_32:$buf_idx_vgpr, + (S_LOAD_DWORDX4_IMM imm:$t_offset, SReg_64:$tlst_sgpr), + 0, 0, (i32 SREG_LIT_0)) +>; + +/* int_SI_load_const */ + +def : Pat < + (int_SI_load_const SReg_64:$const_ptr, IMM8bit:$offset), + (S_LOAD_DWORD_IMM imm:$offset, SReg_64:$const_ptr) +>; + + +/* XXX: Complete this pattern with some form of a scalar move immediate */ +/* +def : Pat < + (int_SI_load_const SReg_64:$const_ptr, imm:$offset), + (S_LOAD_DWORD_SGPR imm:$offset, SReg_64:$const_ptr) +>; +*/ + +/* int_SI_export */ +def : Pat < + (int_SI_export imm:$en, imm:$vm, imm:$done, imm:$tgt, imm:$compr, + VReg_32:$src0,VReg_32:$src1, VReg_32:$src2, VReg_32:$src3), + (EXP imm:$en, imm:$tgt, imm:$compr, imm:$done, imm:$vm, + VReg_32:$src0, VReg_32:$src1, VReg_32:$src2, VReg_32:$src3) +>; + +/* int_SI_sample */ +def : Pat < + (int_SI_sample imm:$writemask, VReg_128:$coord, SReg_64:$rsrc, imm:$rsrc_offset, + SReg_64:$sampler, imm:$sampler_offset), + (IMAGE_SAMPLE imm:$writemask, 0, 0, 0, 0, 0, 0, 0, VReg_128:$coord, + (S_LOAD_DWORDX8_IMM imm:$rsrc_offset, SReg_64:$rsrc), /* Resource */ + (S_LOAD_DWORDX4_IMM imm:$sampler_offset, SReg_64:$sampler)) /* Sampler */ +>; + + +def : Extract_Element ; +def : Extract_Element ; +def : Extract_Element ; +def : Extract_Element ; + +def : Insert_Element ; +def : Insert_Element ; +def : Insert_Element ; +def : Insert_Element ; + +/* +def : Pat< + (int_SI_vs_load_buffer_index), + (COPY_TO_REGCLASS (f32 VGPR0), VReg_32) +>; +*/ + +/********** ===================== **********/ +/********** Interpolation Paterns **********/ +/********** ===================== **********/ + +def : Pat < + (int_SI_fs_interp_linear_center imm:$attr_chan, imm:$attr, SReg_32:$params), + (SI_INTERP (f32 LINEAR_CENTER_I), (f32 LINEAR_CENTER_J), imm:$attr_chan, + imm:$attr, SReg_32:$params) +>; + +/********** ================== **********/ +/********** Intrinsic Patterns **********/ +/********** ================== **********/ + +/* llvm.AMDGPU.pow */ +/* XXX: We are using IEEE MUL, not the 0 * anything = 0 MUL, is this correct? */ +def : POW_Common ; + +} // End isSI predicate diff --git a/lib/Target/AMDIL/SIIntrinsics.td b/lib/Target/AMDIL/SIIntrinsics.td new file mode 100644 index 00000000000..4d23072d4f1 --- /dev/null +++ b/lib/Target/AMDIL/SIIntrinsics.td @@ -0,0 +1,34 @@ +//===-- SIIntrinsics.td - SI Intrinsic defs ----------------*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// SI Intrinsic Definitions +// +//===----------------------------------------------------------------------===// + + +let TargetPrefix = "SI", isTarget = 1 in { + + def int_SI_export : Intrinsic <[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_float_ty], []>; + /* XXX: We may need a seperate intrinsic here for loading integer values */ + def int_SI_load_const : Intrinsic <[llvm_float_ty], [llvm_i64_ty, llvm_i32_ty], []>; + def int_SI_vs_load_buffer_index : Intrinsic <[llvm_i32_ty], [], []>; + def int_SI_vs_load_input : Intrinsic <[llvm_v4f32_ty], [llvm_i64_ty, llvm_i32_ty, llvm_i16_ty, llvm_i32_ty], []> ; + + def int_SI_sample : Intrinsic <[llvm_v4f32_ty], [llvm_i32_ty, llvm_v4f32_ty, llvm_ptr_ty, llvm_i32_ty, llvm_ptr_ty, llvm_i32_ty]>; + def int_SI_use_sgpr : Intrinsic <[llvm_anyint_ty], [llvm_i32_ty], [IntrNoMem]>; + + + /* Interpolation Intrinsics */ + + def int_SI_set_M0 : Intrinsic <[llvm_i32_ty], [llvm_i32_ty]>; + class Interp : Intrinsic <[llvm_float_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>; + + def int_SI_fs_interp_linear_center : Interp; + def int_SI_fs_interp_constant : Interp; +} diff --git a/lib/Target/AMDIL/SIRegisterGetHWRegNum.include b/lib/Target/AMDIL/SIRegisterGetHWRegNum.include new file mode 100644 index 00000000000..abb78c1e012 --- /dev/null +++ b/lib/Target/AMDIL/SIRegisterGetHWRegNum.include @@ -0,0 +1,905 @@ +unsigned SIRegisterInfo::getHWRegNum(unsigned reg) const +{ + switch(reg) { + case AMDIL::VGPR127: + return 127; + case AMDIL::SGPR32: + case AMDIL::SGPR32_64: + case AMDIL::SGPR32_128: + case AMDIL::SGPR32_256: + case AMDIL::VGPR32: + case AMDIL::VGPR32_64: + case AMDIL::VGPR32_128: + return 32; + case AMDIL::SGPR90: + case AMDIL::SGPR90_64: + case AMDIL::VGPR90: + case AMDIL::VGPR90_64: + return 90; + case AMDIL::VGPR206: + case AMDIL::VGPR206_64: + return 206; + case AMDIL::VGPR118: + case AMDIL::VGPR118_64: + return 118; + case AMDIL::SGPR71: + case AMDIL::VGPR71: + return 71; + case AMDIL::SGPR102: + case AMDIL::SGPR102_64: + case AMDIL::VGPR102: + case AMDIL::VGPR102_64: + return 102; + case AMDIL::VGPR200: + case AMDIL::VGPR200_64: + case AMDIL::VGPR200_128: + return 200; + case AMDIL::SGPR18: + case AMDIL::SGPR18_64: + case AMDIL::VGPR18: + case AMDIL::VGPR18_64: + return 18; + case AMDIL::VGPR125: + return 125; + case AMDIL::SGPR16: + case AMDIL::SGPR16_64: + case AMDIL::SGPR16_128: + case AMDIL::SGPR16_256: + case AMDIL::VGPR16: + case AMDIL::VGPR16_64: + case AMDIL::VGPR16_128: + return 16; + case AMDIL::SGPR44: + case AMDIL::SGPR44_64: + case AMDIL::SGPR44_128: + case AMDIL::VGPR44: + case AMDIL::VGPR44_64: + case AMDIL::VGPR44_128: + return 44; + case AMDIL::SGPR55: + case AMDIL::VGPR55: + return 55; + case AMDIL::SGPR84: + case AMDIL::SGPR84_64: + case AMDIL::SGPR84_128: + case AMDIL::VGPR84: + case AMDIL::VGPR84_64: + case AMDIL::VGPR84_128: + return 84; + case AMDIL::SGPR27: + case AMDIL::VGPR27: + return 27; + case AMDIL::VGPR233: + return 233; + case AMDIL::VGPR190: + case AMDIL::VGPR190_64: + return 190; + case AMDIL::VGPR161: + return 161; + case AMDIL::VGPR194: + case AMDIL::VGPR194_64: + return 194; + case AMDIL::SGPR95: + case AMDIL::VGPR95: + return 95; + case AMDIL::SGPR57: + case AMDIL::VGPR57: + return 57; + case AMDIL::VGPR220: + case AMDIL::VGPR220_64: + case AMDIL::VGPR220_128: + return 220; + case AMDIL::SGPR20: + case AMDIL::SGPR20_64: + case AMDIL::SGPR20_128: + case AMDIL::VGPR20: + case AMDIL::VGPR20_64: + case AMDIL::VGPR20_128: + return 20; + case AMDIL::VGPR243: + return 243; + case AMDIL::VGPR231: + return 231; + case AMDIL::VGPR163: + return 163; + case AMDIL::VGPR109: + return 109; + case AMDIL::VGPR151: + return 151; + case AMDIL::SGPR89: + case AMDIL::VGPR89: + return 89; + case AMDIL::VGPR175: + return 175; + case AMDIL::VGPR148: + case AMDIL::VGPR148_64: + case AMDIL::VGPR148_128: + return 148; + case AMDIL::SGPR31: + case AMDIL::VGPR31: + return 31; + case AMDIL::SGPR35: + case AMDIL::VGPR35: + return 35; + case AMDIL::SGPR11: + case AMDIL::VGPR11: + return 11; + case AMDIL::VGPR208: + case AMDIL::VGPR208_64: + case AMDIL::VGPR208_128: + return 208; + case AMDIL::SGPR78: + case AMDIL::SGPR78_64: + case AMDIL::VGPR78: + case AMDIL::VGPR78_64: + return 78; + case AMDIL::SGPR93: + case AMDIL::VGPR93: + return 93; + case AMDIL::VGPR106: + case AMDIL::VGPR106_64: + return 106; + case AMDIL::VGPR157: + return 157; + case AMDIL::SGPR65: + case AMDIL::VGPR65: + return 65; + case AMDIL::SGPR29: + case AMDIL::VGPR29: + return 29; + case AMDIL::VGPR197: + return 197; + case AMDIL::VGPR203: + return 203; + case AMDIL::VGPR138: + case AMDIL::VGPR138_64: + return 138; + case AMDIL::VGPR199: + return 199; + case AMDIL::VGPR114: + case AMDIL::VGPR114_64: + return 114; + case AMDIL::VGPR226: + case AMDIL::VGPR226_64: + return 226; + case AMDIL::SGPR58: + case AMDIL::SGPR58_64: + case AMDIL::VGPR58: + case AMDIL::VGPR58_64: + return 58; + case AMDIL::VGPR211: + return 211; + case AMDIL::VGPR153: + return 153; + case AMDIL::SGPR15: + case AMDIL::VGPR15: + return 15; + case AMDIL::VGPR137: + return 137; + case AMDIL::SGPR81: + case AMDIL::VGPR81: + return 81; + case AMDIL::SGPR60: + case AMDIL::SGPR60_64: + case AMDIL::SGPR60_128: + case AMDIL::VGPR60: + case AMDIL::VGPR60_64: + case AMDIL::VGPR60_128: + return 60; + case AMDIL::SGPR101: + case AMDIL::VGPR101: + return 101; + case AMDIL::SGPR73: + case AMDIL::VGPR73: + return 73; + case AMDIL::SGPR86: + case AMDIL::SGPR86_64: + case AMDIL::VGPR86: + case AMDIL::VGPR86_64: + return 86; + case AMDIL::SGPR76: + case AMDIL::SGPR76_64: + case AMDIL::SGPR76_128: + case AMDIL::VGPR76: + case AMDIL::VGPR76_64: + case AMDIL::VGPR76_128: + return 76; + case AMDIL::SGPR62: + case AMDIL::SGPR62_64: + case AMDIL::VGPR62: + case AMDIL::VGPR62_64: + return 62; + case AMDIL::VGPR247: + return 247; + case AMDIL::SGPR67: + case AMDIL::VGPR67: + return 67; + case AMDIL::VGPR204: + case AMDIL::VGPR204_64: + case AMDIL::VGPR204_128: + return 204; + case AMDIL::VGPR241: + return 241; + case AMDIL::VGPR165: + return 165; + case AMDIL::VGPR198: + case AMDIL::VGPR198_64: + return 198; + case AMDIL::VGPR139: + return 139; + case AMDIL::VGPR129: + return 129; + case AMDIL::SGPR2: + case AMDIL::SGPR2_64: + case AMDIL::VGPR2: + case AMDIL::VGPR2_64: + return 2; + case AMDIL::SGPR17: + case AMDIL::VGPR17: + return 17; + case AMDIL::VGPR186: + case AMDIL::VGPR186_64: + return 186; + case AMDIL::VGPR110: + case AMDIL::VGPR110_64: + return 110; + case AMDIL::SGPR82: + case AMDIL::SGPR82_64: + case AMDIL::VGPR82: + case AMDIL::VGPR82_64: + return 82; + case AMDIL::VGPR147: + return 147; + case AMDIL::VGPR228: + case AMDIL::VGPR228_64: + case AMDIL::VGPR228_128: + return 228; + case AMDIL::VGPR236: + case AMDIL::VGPR236_64: + case AMDIL::VGPR236_128: + return 236; + case AMDIL::VGPR249: + return 249; + case AMDIL::VGPR218: + case AMDIL::VGPR218_64: + return 218; + case AMDIL::VGPR202: + case AMDIL::VGPR202_64: + return 202; + case AMDIL::VGPR168: + case AMDIL::VGPR168_64: + case AMDIL::VGPR168_128: + return 168; + case AMDIL::VGPR184: + case AMDIL::VGPR184_64: + case AMDIL::VGPR184_128: + return 184; + case AMDIL::VGPR135: + return 135; + case AMDIL::SGPR14: + case AMDIL::SGPR14_64: + case AMDIL::VGPR14: + case AMDIL::VGPR14_64: + return 14; + case AMDIL::VGPR112: + case AMDIL::VGPR112_64: + case AMDIL::VGPR112_128: + return 112; + case AMDIL::SGPR69: + case AMDIL::VGPR69: + return 69; + case AMDIL::VGPR191: + return 191; + case AMDIL::VGPR172: + case AMDIL::VGPR172_64: + case AMDIL::VGPR172_128: + return 172; + case AMDIL::VGPR145: + return 145; + case AMDIL::SGPR49: + case AMDIL::VGPR49: + return 49; + case AMDIL::VGPR178: + case AMDIL::VGPR178_64: + return 178; + case AMDIL::SGPR24: + case AMDIL::SGPR24_64: + case AMDIL::SGPR24_128: + case AMDIL::SGPR24_256: + case AMDIL::VGPR24: + case AMDIL::VGPR24_64: + case AMDIL::VGPR24_128: + return 24; + case AMDIL::VGPR224: + case AMDIL::VGPR224_64: + case AMDIL::VGPR224_128: + return 224; + case AMDIL::VGPR187: + return 187; + case AMDIL::VGPR140: + case AMDIL::VGPR140_64: + case AMDIL::VGPR140_128: + return 140; + case AMDIL::VGPR223: + return 223; + case AMDIL::VGPR124: + case AMDIL::VGPR124_64: + case AMDIL::VGPR124_128: + return 124; + case AMDIL::VGPR104: + case AMDIL::VGPR104_64: + case AMDIL::VGPR104_128: + return 104; + case AMDIL::VGPR131: + return 131; + case AMDIL::VGPR181: + return 181; + case AMDIL::VGPR234: + case AMDIL::VGPR234_64: + return 234; + case AMDIL::VGPR121: + return 121; + case AMDIL::SGPR79: + case AMDIL::VGPR79: + return 79; + case AMDIL::VGPR212: + case AMDIL::VGPR212_64: + case AMDIL::VGPR212_128: + return 212; + case AMDIL::VGPR154: + case AMDIL::VGPR154_64: + return 154; + case AMDIL::SGPR0: + case AMDIL::SGPR0_64: + case AMDIL::SGPR0_128: + case AMDIL::SGPR0_256: + case AMDIL::VGPR0: + case AMDIL::VGPR0_64: + case AMDIL::VGPR0_128: + return 0; + case AMDIL::SGPR23: + case AMDIL::VGPR23: + return 23; + case AMDIL::SGPR96: + case AMDIL::SGPR96_64: + case AMDIL::SGPR96_128: + case AMDIL::SGPR96_256: + case AMDIL::VGPR96: + case AMDIL::VGPR96_64: + case AMDIL::VGPR96_128: + return 96; + case AMDIL::VGPR126: + case AMDIL::VGPR126_64: + return 126; + case AMDIL::VGPR238: + case AMDIL::VGPR238_64: + return 238; + case AMDIL::VGPR159: + return 159; + case AMDIL::VGPR251: + return 251; + case AMDIL::VGPR253: + return 253; + case AMDIL::VGPR160: + case AMDIL::VGPR160_64: + case AMDIL::VGPR160_128: + return 160; + case AMDIL::VGPR176: + case AMDIL::VGPR176_64: + case AMDIL::VGPR176_128: + return 176; + case AMDIL::SGPR47: + case AMDIL::VGPR47: + return 47; + case AMDIL::SGPR8: + case AMDIL::SGPR8_64: + case AMDIL::SGPR8_128: + case AMDIL::SGPR8_256: + case AMDIL::VGPR8: + case AMDIL::VGPR8_64: + case AMDIL::VGPR8_128: + return 8; + case AMDIL::VGPR209: + return 209; + case AMDIL::SGPR98: + case AMDIL::SGPR98_64: + case AMDIL::VGPR98: + case AMDIL::VGPR98_64: + return 98; + case AMDIL::VGPR216: + case AMDIL::VGPR216_64: + case AMDIL::VGPR216_128: + return 216; + case AMDIL::SGPR37: + case AMDIL::VGPR37: + return 37; + case AMDIL::VGPR117: + return 117; + case AMDIL::SGPR43: + case AMDIL::VGPR43: + return 43; + case AMDIL::VGPR195: + return 195; + case AMDIL::SGPR5: + case AMDIL::VGPR5: + return 5; + case AMDIL::VGPR170: + case AMDIL::VGPR170_64: + return 170; + case AMDIL::SGPR33: + case AMDIL::VGPR33: + return 33; + case AMDIL::SGPR21: + case AMDIL::VGPR21: + return 21; + case AMDIL::SGPR63: + case AMDIL::VGPR63: + return 63; + case AMDIL::SGPR7: + case AMDIL::VGPR7: + return 7; + case AMDIL::VGPR227: + return 227; + case AMDIL::SGPR26: + case AMDIL::SGPR26_64: + case AMDIL::VGPR26: + case AMDIL::VGPR26_64: + return 26; + case AMDIL::SGPR80: + case AMDIL::SGPR80_64: + case AMDIL::SGPR80_128: + case AMDIL::SGPR80_256: + case AMDIL::VGPR80: + case AMDIL::VGPR80_64: + case AMDIL::VGPR80_128: + return 80; + case AMDIL::VGPR193: + return 193; + case AMDIL::VGPR119: + return 119; + case AMDIL::VGPR180: + case AMDIL::VGPR180_64: + case AMDIL::VGPR180_128: + return 180; + case AMDIL::SGPR99: + case AMDIL::VGPR99: + return 99; + case AMDIL::VGPR244: + case AMDIL::VGPR244_64: + case AMDIL::VGPR244_128: + return 244; + case AMDIL::VGPR179: + return 179; + case AMDIL::VGPR162: + case AMDIL::VGPR162_64: + return 162; + case AMDIL::SGPR72: + case AMDIL::SGPR72_64: + case AMDIL::SGPR72_128: + case AMDIL::SGPR72_256: + case AMDIL::VGPR72: + case AMDIL::VGPR72_64: + case AMDIL::VGPR72_128: + return 72; + case AMDIL::VGPR255: + return 255; + case AMDIL::VGPR246: + case AMDIL::VGPR246_64: + return 246; + case AMDIL::VGPR240: + case AMDIL::VGPR240_64: + case AMDIL::VGPR240_128: + return 240; + case AMDIL::SGPR74: + case AMDIL::SGPR74_64: + case AMDIL::VGPR74: + case AMDIL::VGPR74_64: + return 74; + case AMDIL::VGPR182: + case AMDIL::VGPR182_64: + return 182; + case AMDIL::SGPR61: + case AMDIL::VGPR61: + return 61; + case AMDIL::VGPR230: + case AMDIL::VGPR230_64: + return 230; + case AMDIL::VGPR108: + case AMDIL::VGPR108_64: + case AMDIL::VGPR108_128: + return 108; + case AMDIL::VGPR115: + return 115; + case AMDIL::SGPR92: + case AMDIL::SGPR92_64: + case AMDIL::SGPR92_128: + case AMDIL::VGPR92: + case AMDIL::VGPR92_64: + case AMDIL::VGPR92_128: + return 92; + case AMDIL::SGPR103: + case AMDIL::VGPR103: + return 103; + case AMDIL::VGPR201: + return 201; + case AMDIL::VGPR232: + case AMDIL::VGPR232_64: + case AMDIL::VGPR232_128: + return 232; + case AMDIL::SGPR10: + case AMDIL::SGPR10_64: + case AMDIL::VGPR10: + case AMDIL::VGPR10_64: + return 10; + case AMDIL::VGPR113: + return 113; + case AMDIL::VGPR152: + case AMDIL::VGPR152_64: + case AMDIL::VGPR152_128: + return 152; + case AMDIL::VGPR189: + return 189; + case AMDIL::VGPR225: + return 225; + case AMDIL::VGPR207: + return 207; + case AMDIL::VGPR142: + case AMDIL::VGPR142_64: + return 142; + case AMDIL::SGPR91: + case AMDIL::VGPR91: + return 91; + case AMDIL::VGPR167: + return 167; + case AMDIL::SGPR48: + case AMDIL::SGPR48_64: + case AMDIL::SGPR48_128: + case AMDIL::SGPR48_256: + case AMDIL::VGPR48: + case AMDIL::VGPR48_64: + case AMDIL::VGPR48_128: + return 48; + case AMDIL::VGPR107: + return 107; + case AMDIL::SGPR87: + case AMDIL::VGPR87: + return 87; + case AMDIL::VGPR174: + case AMDIL::VGPR174_64: + return 174; + case AMDIL::SGPR77: + case AMDIL::VGPR77: + return 77; + case AMDIL::VGPR214: + case AMDIL::VGPR214_64: + return 214; + case AMDIL::VGPR133: + return 133; + case AMDIL::VGPR149: + return 149; + case AMDIL::VGPR123: + return 123; + case AMDIL::VGPR221: + return 221; + case AMDIL::SGPR50: + case AMDIL::SGPR50_64: + case AMDIL::VGPR50: + case AMDIL::VGPR50_64: + return 50; + case AMDIL::SGPR39: + case AMDIL::VGPR39: + return 39; + case AMDIL::VGPR210: + case AMDIL::VGPR210_64: + return 210; + case AMDIL::SGPR64: + case AMDIL::SGPR64_64: + case AMDIL::SGPR64_128: + case AMDIL::SGPR64_256: + case AMDIL::VGPR64: + case AMDIL::VGPR64_64: + case AMDIL::VGPR64_128: + return 64; + case AMDIL::SGPR97: + case AMDIL::VGPR97: + return 97; + case AMDIL::SGPR12: + case AMDIL::SGPR12_64: + case AMDIL::SGPR12_128: + case AMDIL::VGPR12: + case AMDIL::VGPR12_64: + case AMDIL::VGPR12_128: + return 12; + case AMDIL::SGPR41: + case AMDIL::VGPR41: + return 41; + case AMDIL::SGPR52: + case AMDIL::SGPR52_64: + case AMDIL::SGPR52_128: + case AMDIL::VGPR52: + case AMDIL::VGPR52_64: + case AMDIL::VGPR52_128: + return 52; + case AMDIL::VGPR173: + return 173; + case AMDIL::SGPR56: + case AMDIL::SGPR56_64: + case AMDIL::SGPR56_128: + case AMDIL::SGPR56_256: + case AMDIL::VGPR56: + case AMDIL::VGPR56_64: + case AMDIL::VGPR56_128: + return 56; + case AMDIL::VGPR229: + return 229; + case AMDIL::SGPR45: + case AMDIL::VGPR45: + return 45; + case AMDIL::SGPR66: + case AMDIL::SGPR66_64: + case AMDIL::VGPR66: + case AMDIL::VGPR66_64: + return 66; + case AMDIL::SGPR19: + case AMDIL::VGPR19: + return 19; + case AMDIL::SGPR54: + case AMDIL::SGPR54_64: + case AMDIL::VGPR54: + case AMDIL::VGPR54_64: + return 54; + case AMDIL::VGPR237: + return 237; + case AMDIL::SGPR70: + case AMDIL::SGPR70_64: + case AMDIL::VGPR70: + case AMDIL::VGPR70_64: + return 70; + case AMDIL::VGPR188: + case AMDIL::VGPR188_64: + case AMDIL::VGPR188_128: + return 188; + case AMDIL::SGPR68: + case AMDIL::SGPR68_64: + case AMDIL::SGPR68_128: + case AMDIL::VGPR68: + case AMDIL::VGPR68_64: + case AMDIL::VGPR68_128: + return 68; + case AMDIL::VGPR166: + case AMDIL::VGPR166_64: + return 166; + case AMDIL::SGPR1: + case AMDIL::VGPR1: + return 1; + case AMDIL::VGPR136: + case AMDIL::VGPR136_64: + case AMDIL::VGPR136_128: + return 136; + case AMDIL::SGPR88: + case AMDIL::SGPR88_64: + case AMDIL::SGPR88_128: + case AMDIL::SGPR88_256: + case AMDIL::VGPR88: + case AMDIL::VGPR88_64: + case AMDIL::VGPR88_128: + return 88; + case AMDIL::VGPR116: + case AMDIL::VGPR116_64: + case AMDIL::VGPR116_128: + return 116; + case AMDIL::VGPR144: + case AMDIL::VGPR144_64: + case AMDIL::VGPR144_128: + return 144; + case AMDIL::VGPR141: + return 141; + case AMDIL::SGPR30: + case AMDIL::SGPR30_64: + case AMDIL::VGPR30: + case AMDIL::VGPR30_64: + return 30; + case AMDIL::SGPR100: + case AMDIL::SGPR100_64: + case AMDIL::SGPR100_128: + case AMDIL::VGPR100: + case AMDIL::VGPR100_64: + case AMDIL::VGPR100_128: + return 100; + case AMDIL::VGPR222: + case AMDIL::VGPR222_64: + return 222; + case AMDIL::VGPR128: + case AMDIL::VGPR128_64: + case AMDIL::VGPR128_128: + return 128; + case AMDIL::SGPR25: + case AMDIL::VGPR25: + return 25; + case AMDIL::VGPR252: + case AMDIL::VGPR252_64: + case AMDIL::VGPR252_128: + return 252; + case AMDIL::SGPR28: + case AMDIL::SGPR28_64: + case AMDIL::SGPR28_128: + case AMDIL::VGPR28: + case AMDIL::VGPR28_64: + case AMDIL::VGPR28_128: + return 28; + case AMDIL::VGPR120: + case AMDIL::VGPR120_64: + case AMDIL::VGPR120_128: + return 120; + case AMDIL::VGPR156: + case AMDIL::VGPR156_64: + case AMDIL::VGPR156_128: + return 156; + case AMDIL::VGPR134: + case AMDIL::VGPR134_64: + return 134; + case AMDIL::SGPR40: + case AMDIL::SGPR40_64: + case AMDIL::SGPR40_128: + case AMDIL::SGPR40_256: + case AMDIL::VGPR40: + case AMDIL::VGPR40_64: + case AMDIL::VGPR40_128: + return 40; + case AMDIL::SGPR75: + case AMDIL::VGPR75: + return 75; + case AMDIL::SGPR83: + case AMDIL::VGPR83: + return 83; + case AMDIL::VGPR250: + case AMDIL::VGPR250_64: + return 250; + case AMDIL::VGPR192: + case AMDIL::VGPR192_64: + case AMDIL::VGPR192_128: + return 192; + case AMDIL::SGPR59: + case AMDIL::VGPR59: + return 59; + case AMDIL::VGPR254: + case AMDIL::VGPR254_64: + return 254; + case AMDIL::VGPR215: + return 215; + case AMDIL::VGPR177: + return 177; + case AMDIL::VGPR150: + case AMDIL::VGPR150_64: + return 150; + case AMDIL::VGPR155: + return 155; + case AMDIL::VGPR130: + case AMDIL::VGPR130_64: + return 130; + case AMDIL::VGPR217: + return 217; + case AMDIL::SGPR53: + case AMDIL::VGPR53: + return 53; + case AMDIL::VGPR245: + return 245; + case AMDIL::VGPR239: + return 239; + case AMDIL::VGPR122: + case AMDIL::VGPR122_64: + return 122; + case AMDIL::VGPR143: + return 143; + case AMDIL::VGPR205: + return 205; + case AMDIL::VGPR158: + case AMDIL::VGPR158_64: + return 158; + case AMDIL::SGPR42: + case AMDIL::SGPR42_64: + case AMDIL::VGPR42: + case AMDIL::VGPR42_64: + return 42; + case AMDIL::SGPR22: + case AMDIL::SGPR22_64: + case AMDIL::VGPR22: + case AMDIL::VGPR22_64: + return 22; + case AMDIL::VGPR219: + return 219; + case AMDIL::SGPR46: + case AMDIL::SGPR46_64: + case AMDIL::VGPR46: + case AMDIL::VGPR46_64: + return 46; + case AMDIL::SGPR13: + case AMDIL::VGPR13: + return 13; + case AMDIL::VGPR235: + return 235; + case AMDIL::VGPR105: + return 105; + case AMDIL::SGPR6: + case AMDIL::SGPR6_64: + case AMDIL::VGPR6: + case AMDIL::VGPR6_64: + return 6; + case AMDIL::SGPR85: + case AMDIL::VGPR85: + return 85; + case AMDIL::VGPR185: + return 185; + case AMDIL::SGPR36: + case AMDIL::SGPR36_64: + case AMDIL::SGPR36_128: + case AMDIL::VGPR36: + case AMDIL::VGPR36_64: + case AMDIL::VGPR36_128: + return 36; + case AMDIL::SGPR3: + case AMDIL::VGPR3: + return 3; + case AMDIL::VGPR248: + case AMDIL::VGPR248_64: + case AMDIL::VGPR248_128: + return 248; + case AMDIL::VGPR213: + return 213; + case AMDIL::VGPR183: + return 183; + case AMDIL::SGPR94: + case AMDIL::SGPR94_64: + case AMDIL::VGPR94: + case AMDIL::VGPR94_64: + return 94; + case AMDIL::VGPR146: + case AMDIL::VGPR146_64: + return 146; + case AMDIL::SGPR51: + case AMDIL::VGPR51: + return 51; + case AMDIL::SGPR9: + case AMDIL::VGPR9: + return 9; + case AMDIL::VGPR111: + return 111; + case AMDIL::SGPR38: + case AMDIL::SGPR38_64: + case AMDIL::VGPR38: + case AMDIL::VGPR38_64: + return 38; + case AMDIL::SGPR4: + case AMDIL::SGPR4_64: + case AMDIL::SGPR4_128: + case AMDIL::VGPR4: + case AMDIL::VGPR4_64: + case AMDIL::VGPR4_128: + return 4; + case AMDIL::SGPR34: + case AMDIL::SGPR34_64: + case AMDIL::VGPR34: + case AMDIL::VGPR34_64: + return 34; + case AMDIL::VGPR169: + return 169; + case AMDIL::VGPR164: + case AMDIL::VGPR164_64: + case AMDIL::VGPR164_128: + return 164; + case AMDIL::VGPR132: + case AMDIL::VGPR132_64: + case AMDIL::VGPR132_128: + return 132; + case AMDIL::VGPR196: + case AMDIL::VGPR196_64: + case AMDIL::VGPR196_128: + return 196; + case AMDIL::VGPR171: + return 171; + case AMDIL::VGPR242: + case AMDIL::VGPR242_64: + return 242; + default: return 0; + } +} diff --git a/lib/Target/AMDIL/SIRegisterInfo.td b/lib/Target/AMDIL/SIRegisterInfo.td new file mode 100644 index 00000000000..4a607516e8a --- /dev/null +++ b/lib/Target/AMDIL/SIRegisterInfo.td @@ -0,0 +1,894 @@ + +let Namespace = "AMDIL" in { + def low : SubRegIndex; + def high : SubRegIndex; + + def sub0 : SubRegIndex; + def sub1 : SubRegIndex; + def sub2 : SubRegIndex; + def sub3 : SubRegIndex; + def sub4 : SubRegIndex; + def sub5 : SubRegIndex; + def sub6 : SubRegIndex; + def sub7 : SubRegIndex; +} + +class SIReg : Register { + let Namespace = "AMDIL"; +} + +class SI_64 subregs> : RegisterWithSubRegs { + let Namespace = "AMDIL"; + let SubRegIndices = [low, high]; +} + +class SI_128 subregs> : RegisterWithSubRegs { + let Namespace = "AMDIL"; + let SubRegIndices = [sel_x, sel_y, sel_z, sel_w]; +} + +class SI_256 subregs> : RegisterWithSubRegs { + let Namespace = "AMDIL"; + let SubRegIndices = [sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7]; +} + +class SGPR_32 num, string name> : SIReg { + field bits<8> Num; + + let Num = num; +} + + +class VGPR_32 num, string name, Register gprf32_alias> : SIReg { + field bits<9> Num; + + let Num = num; + let Aliases = [gprf32_alias]; +} + +class SGPR_64 num, string name, list subregs> : + SI_64 ; + +class VGPR_64 num, string name, list subregs> : + SI_64 ; + +class SGPR_128 num, string name, list subregs> : + SI_128 ; + +class VGPR_128 num, string name, list subregs> : + SI_128 ; + +class SGPR_256 num, string name, list subregs> : + SI_256 ; + +def VCC : SIReg<"VCC">; +def SCC : SIReg<"SCC">; +def SREG_LIT_0 : SIReg <"S LIT 0">; + +def M0 : SIReg <"M0">; + +//Interpolation registers + +def PERSP_SAMPLE_I : SIReg <"PERSP_SAMPLE_I">; +def PERSP_SAMPLE_J : SIReg <"PERSP_SAMPLE_J">; +def PERSP_CENTER_I : SIReg <"PERSP_CENTER_I">; +def PERSP_CENTER_J : SIReg <"PERSP_CENTER_J">; +def PERSP_CENTROID_I : SIReg <"PERSP_CENTROID_I">; +def PERSP_CENTROID_J : SIReg <"PERP_CENTROID_J">; +def PERSP_I_W : SIReg <"PERSP_I_W">; +def PERSP_J_W : SIReg <"PERSP_J_W">; +def PERSP_1_W : SIReg <"PERSP_1_W">; +def LINEAR_SAMPLE_I : SIReg <"LINEAR_SAMPLE_I">; +def LINEAR_SAMPLE_J : SIReg <"LINEAR_SAMPLE_J">; +def LINEAR_CENTER_I : SIReg <"LINEAR_CENTER_I">; +def LINEAR_CENTER_J : SIReg <"LINEAR_CENTER_J">; +def LINEAR_CENTROID_I : SIReg <"LINEAR_CENTROID_I">; +def LINEAR_CENTROID_J : SIReg <"LINEAR_CENTROID_J">; +def LINE_STIPPLE_TEX_COORD : SIReg <"LINE_STIPPLE_TEX_COORD">; +def POS_X_FLOAT : SIReg <"POS_X_FLOAT">; +def POS_Y_FLOAT : SIReg <"POS_Y_FLOAT">; +def POS_Z_FLOAT : SIReg <"POS_Z_FLOAT">; +def POS_W_FLOAT : SIReg <"POS_W_FLOAT">; +def FRONT_FACE : SIReg <"FRONT_FACE">; +def ANCILLARY : SIReg <"ANCILLARY">; +def SAMPLE_COVERAGE : SIReg <"SAMPLE_COVERAGE">; +def POS_FIXED_PT : SIReg <"POS_FIXED_PT">; + +def SGPR0 : SGPR_32 <0, "SGPR0">; +def SGPR1 : SGPR_32 <1, "SGPR1">; +def SGPR2 : SGPR_32 <2, "SGPR2">; +def SGPR3 : SGPR_32 <3, "SGPR3">; +def SGPR4 : SGPR_32 <4, "SGPR4">; +def SGPR5 : SGPR_32 <5, "SGPR5">; +def SGPR6 : SGPR_32 <6, "SGPR6">; +def SGPR7 : SGPR_32 <7, "SGPR7">; +def SGPR8 : SGPR_32 <8, "SGPR8">; +def SGPR9 : SGPR_32 <9, "SGPR9">; +def SGPR10 : SGPR_32 <10, "SGPR10">; +def SGPR11 : SGPR_32 <11, "SGPR11">; +def SGPR12 : SGPR_32 <12, "SGPR12">; +def SGPR13 : SGPR_32 <13, "SGPR13">; +def SGPR14 : SGPR_32 <14, "SGPR14">; +def SGPR15 : SGPR_32 <15, "SGPR15">; +def SGPR16 : SGPR_32 <16, "SGPR16">; +def SGPR17 : SGPR_32 <17, "SGPR17">; +def SGPR18 : SGPR_32 <18, "SGPR18">; +def SGPR19 : SGPR_32 <19, "SGPR19">; +def SGPR20 : SGPR_32 <20, "SGPR20">; +def SGPR21 : SGPR_32 <21, "SGPR21">; +def SGPR22 : SGPR_32 <22, "SGPR22">; +def SGPR23 : SGPR_32 <23, "SGPR23">; +def SGPR24 : SGPR_32 <24, "SGPR24">; +def SGPR25 : SGPR_32 <25, "SGPR25">; +def SGPR26 : SGPR_32 <26, "SGPR26">; +def SGPR27 : SGPR_32 <27, "SGPR27">; +def SGPR28 : SGPR_32 <28, "SGPR28">; +def SGPR29 : SGPR_32 <29, "SGPR29">; +def SGPR30 : SGPR_32 <30, "SGPR30">; +def SGPR31 : SGPR_32 <31, "SGPR31">; +def SGPR32 : SGPR_32 <32, "SGPR32">; +def SGPR33 : SGPR_32 <33, "SGPR33">; +def SGPR34 : SGPR_32 <34, "SGPR34">; +def SGPR35 : SGPR_32 <35, "SGPR35">; +def SGPR36 : SGPR_32 <36, "SGPR36">; +def SGPR37 : SGPR_32 <37, "SGPR37">; +def SGPR38 : SGPR_32 <38, "SGPR38">; +def SGPR39 : SGPR_32 <39, "SGPR39">; +def SGPR40 : SGPR_32 <40, "SGPR40">; +def SGPR41 : SGPR_32 <41, "SGPR41">; +def SGPR42 : SGPR_32 <42, "SGPR42">; +def SGPR43 : SGPR_32 <43, "SGPR43">; +def SGPR44 : SGPR_32 <44, "SGPR44">; +def SGPR45 : SGPR_32 <45, "SGPR45">; +def SGPR46 : SGPR_32 <46, "SGPR46">; +def SGPR47 : SGPR_32 <47, "SGPR47">; +def SGPR48 : SGPR_32 <48, "SGPR48">; +def SGPR49 : SGPR_32 <49, "SGPR49">; +def SGPR50 : SGPR_32 <50, "SGPR50">; +def SGPR51 : SGPR_32 <51, "SGPR51">; +def SGPR52 : SGPR_32 <52, "SGPR52">; +def SGPR53 : SGPR_32 <53, "SGPR53">; +def SGPR54 : SGPR_32 <54, "SGPR54">; +def SGPR55 : SGPR_32 <55, "SGPR55">; +def SGPR56 : SGPR_32 <56, "SGPR56">; +def SGPR57 : SGPR_32 <57, "SGPR57">; +def SGPR58 : SGPR_32 <58, "SGPR58">; +def SGPR59 : SGPR_32 <59, "SGPR59">; +def SGPR60 : SGPR_32 <60, "SGPR60">; +def SGPR61 : SGPR_32 <61, "SGPR61">; +def SGPR62 : SGPR_32 <62, "SGPR62">; +def SGPR63 : SGPR_32 <63, "SGPR63">; +def SGPR64 : SGPR_32 <64, "SGPR64">; +def SGPR65 : SGPR_32 <65, "SGPR65">; +def SGPR66 : SGPR_32 <66, "SGPR66">; +def SGPR67 : SGPR_32 <67, "SGPR67">; +def SGPR68 : SGPR_32 <68, "SGPR68">; +def SGPR69 : SGPR_32 <69, "SGPR69">; +def SGPR70 : SGPR_32 <70, "SGPR70">; +def SGPR71 : SGPR_32 <71, "SGPR71">; +def SGPR72 : SGPR_32 <72, "SGPR72">; +def SGPR73 : SGPR_32 <73, "SGPR73">; +def SGPR74 : SGPR_32 <74, "SGPR74">; +def SGPR75 : SGPR_32 <75, "SGPR75">; +def SGPR76 : SGPR_32 <76, "SGPR76">; +def SGPR77 : SGPR_32 <77, "SGPR77">; +def SGPR78 : SGPR_32 <78, "SGPR78">; +def SGPR79 : SGPR_32 <79, "SGPR79">; +def SGPR80 : SGPR_32 <80, "SGPR80">; +def SGPR81 : SGPR_32 <81, "SGPR81">; +def SGPR82 : SGPR_32 <82, "SGPR82">; +def SGPR83 : SGPR_32 <83, "SGPR83">; +def SGPR84 : SGPR_32 <84, "SGPR84">; +def SGPR85 : SGPR_32 <85, "SGPR85">; +def SGPR86 : SGPR_32 <86, "SGPR86">; +def SGPR87 : SGPR_32 <87, "SGPR87">; +def SGPR88 : SGPR_32 <88, "SGPR88">; +def SGPR89 : SGPR_32 <89, "SGPR89">; +def SGPR90 : SGPR_32 <90, "SGPR90">; +def SGPR91 : SGPR_32 <91, "SGPR91">; +def SGPR92 : SGPR_32 <92, "SGPR92">; +def SGPR93 : SGPR_32 <93, "SGPR93">; +def SGPR94 : SGPR_32 <94, "SGPR94">; +def SGPR95 : SGPR_32 <95, "SGPR95">; +def SGPR96 : SGPR_32 <96, "SGPR96">; +def SGPR97 : SGPR_32 <97, "SGPR97">; +def SGPR98 : SGPR_32 <98, "SGPR98">; +def SGPR99 : SGPR_32 <99, "SGPR99">; +def SGPR100 : SGPR_32 <100, "SGPR100">; +def SGPR101 : SGPR_32 <101, "SGPR101">; +def SGPR102 : SGPR_32 <102, "SGPR102">; +def SGPR103 : SGPR_32 <103, "SGPR103">; +def VGPR0 : VGPR_32 <0, "VGPR0", R1>; +def VGPR1 : VGPR_32 <1, "VGPR1", R2>; +def VGPR2 : VGPR_32 <2, "VGPR2", R3>; +def VGPR3 : VGPR_32 <3, "VGPR3", R4>; +def VGPR4 : VGPR_32 <4, "VGPR4", R5>; +def VGPR5 : VGPR_32 <5, "VGPR5", R6>; +def VGPR6 : VGPR_32 <6, "VGPR6", R7>; +def VGPR7 : VGPR_32 <7, "VGPR7", R8>; +def VGPR8 : VGPR_32 <8, "VGPR8", R9>; +def VGPR9 : VGPR_32 <9, "VGPR9", R10>; +def VGPR10 : VGPR_32 <10, "VGPR10", R11>; +def VGPR11 : VGPR_32 <11, "VGPR11", R12>; +def VGPR12 : VGPR_32 <12, "VGPR12", R13>; +def VGPR13 : VGPR_32 <13, "VGPR13", R14>; +def VGPR14 : VGPR_32 <14, "VGPR14", R15>; +def VGPR15 : VGPR_32 <15, "VGPR15", R16>; +def VGPR16 : VGPR_32 <16, "VGPR16", R17>; +def VGPR17 : VGPR_32 <17, "VGPR17", R18>; +def VGPR18 : VGPR_32 <18, "VGPR18", R19>; +def VGPR19 : VGPR_32 <19, "VGPR19", R20>; +def VGPR20 : VGPR_32 <20, "VGPR20", R21>; +def VGPR21 : VGPR_32 <21, "VGPR21", R22>; +def VGPR22 : VGPR_32 <22, "VGPR22", R23>; +def VGPR23 : VGPR_32 <23, "VGPR23", R24>; +def VGPR24 : VGPR_32 <24, "VGPR24", R25>; +def VGPR25 : VGPR_32 <25, "VGPR25", R26>; +def VGPR26 : VGPR_32 <26, "VGPR26", R27>; +def VGPR27 : VGPR_32 <27, "VGPR27", R28>; +def VGPR28 : VGPR_32 <28, "VGPR28", R29>; +def VGPR29 : VGPR_32 <29, "VGPR29", R30>; +def VGPR30 : VGPR_32 <30, "VGPR30", R31>; +def VGPR31 : VGPR_32 <31, "VGPR31", R32>; +def VGPR32 : VGPR_32 <32, "VGPR32", R33>; +def VGPR33 : VGPR_32 <33, "VGPR33", R34>; +def VGPR34 : VGPR_32 <34, "VGPR34", R35>; +def VGPR35 : VGPR_32 <35, "VGPR35", R36>; +def VGPR36 : VGPR_32 <36, "VGPR36", R37>; +def VGPR37 : VGPR_32 <37, "VGPR37", R38>; +def VGPR38 : VGPR_32 <38, "VGPR38", R39>; +def VGPR39 : VGPR_32 <39, "VGPR39", R40>; +def VGPR40 : VGPR_32 <40, "VGPR40", R41>; +def VGPR41 : VGPR_32 <41, "VGPR41", R42>; +def VGPR42 : VGPR_32 <42, "VGPR42", R43>; +def VGPR43 : VGPR_32 <43, "VGPR43", R44>; +def VGPR44 : VGPR_32 <44, "VGPR44", R45>; +def VGPR45 : VGPR_32 <45, "VGPR45", R46>; +def VGPR46 : VGPR_32 <46, "VGPR46", R47>; +def VGPR47 : VGPR_32 <47, "VGPR47", R48>; +def VGPR48 : VGPR_32 <48, "VGPR48", R49>; +def VGPR49 : VGPR_32 <49, "VGPR49", R50>; +def VGPR50 : VGPR_32 <50, "VGPR50", R51>; +def VGPR51 : VGPR_32 <51, "VGPR51", R52>; +def VGPR52 : VGPR_32 <52, "VGPR52", R53>; +def VGPR53 : VGPR_32 <53, "VGPR53", R54>; +def VGPR54 : VGPR_32 <54, "VGPR54", R55>; +def VGPR55 : VGPR_32 <55, "VGPR55", R56>; +def VGPR56 : VGPR_32 <56, "VGPR56", R57>; +def VGPR57 : VGPR_32 <57, "VGPR57", R58>; +def VGPR58 : VGPR_32 <58, "VGPR58", R59>; +def VGPR59 : VGPR_32 <59, "VGPR59", R60>; +def VGPR60 : VGPR_32 <60, "VGPR60", R61>; +def VGPR61 : VGPR_32 <61, "VGPR61", R62>; +def VGPR62 : VGPR_32 <62, "VGPR62", R63>; +def VGPR63 : VGPR_32 <63, "VGPR63", R64>; +def VGPR64 : VGPR_32 <64, "VGPR64", R65>; +def VGPR65 : VGPR_32 <65, "VGPR65", R66>; +def VGPR66 : VGPR_32 <66, "VGPR66", R67>; +def VGPR67 : VGPR_32 <67, "VGPR67", R68>; +def VGPR68 : VGPR_32 <68, "VGPR68", R69>; +def VGPR69 : VGPR_32 <69, "VGPR69", R70>; +def VGPR70 : VGPR_32 <70, "VGPR70", R71>; +def VGPR71 : VGPR_32 <71, "VGPR71", R72>; +def VGPR72 : VGPR_32 <72, "VGPR72", R73>; +def VGPR73 : VGPR_32 <73, "VGPR73", R74>; +def VGPR74 : VGPR_32 <74, "VGPR74", R75>; +def VGPR75 : VGPR_32 <75, "VGPR75", R76>; +def VGPR76 : VGPR_32 <76, "VGPR76", R77>; +def VGPR77 : VGPR_32 <77, "VGPR77", R78>; +def VGPR78 : VGPR_32 <78, "VGPR78", R79>; +def VGPR79 : VGPR_32 <79, "VGPR79", R80>; +def VGPR80 : VGPR_32 <80, "VGPR80", R81>; +def VGPR81 : VGPR_32 <81, "VGPR81", R82>; +def VGPR82 : VGPR_32 <82, "VGPR82", R83>; +def VGPR83 : VGPR_32 <83, "VGPR83", R84>; +def VGPR84 : VGPR_32 <84, "VGPR84", R85>; +def VGPR85 : VGPR_32 <85, "VGPR85", R86>; +def VGPR86 : VGPR_32 <86, "VGPR86", R87>; +def VGPR87 : VGPR_32 <87, "VGPR87", R88>; +def VGPR88 : VGPR_32 <88, "VGPR88", R89>; +def VGPR89 : VGPR_32 <89, "VGPR89", R90>; +def VGPR90 : VGPR_32 <90, "VGPR90", R91>; +def VGPR91 : VGPR_32 <91, "VGPR91", R92>; +def VGPR92 : VGPR_32 <92, "VGPR92", R93>; +def VGPR93 : VGPR_32 <93, "VGPR93", R94>; +def VGPR94 : VGPR_32 <94, "VGPR94", R95>; +def VGPR95 : VGPR_32 <95, "VGPR95", R96>; +def VGPR96 : VGPR_32 <96, "VGPR96", R97>; +def VGPR97 : VGPR_32 <97, "VGPR97", R98>; +def VGPR98 : VGPR_32 <98, "VGPR98", R99>; +def VGPR99 : VGPR_32 <99, "VGPR99", R100>; +def VGPR100 : VGPR_32 <100, "VGPR100", R101>; +def VGPR101 : VGPR_32 <101, "VGPR101", R102>; +def VGPR102 : VGPR_32 <102, "VGPR102", R103>; +def VGPR103 : VGPR_32 <103, "VGPR103", R104>; +def VGPR104 : VGPR_32 <104, "VGPR104", R105>; +def VGPR105 : VGPR_32 <105, "VGPR105", R106>; +def VGPR106 : VGPR_32 <106, "VGPR106", R107>; +def VGPR107 : VGPR_32 <107, "VGPR107", R108>; +def VGPR108 : VGPR_32 <108, "VGPR108", R109>; +def VGPR109 : VGPR_32 <109, "VGPR109", R110>; +def VGPR110 : VGPR_32 <110, "VGPR110", R111>; +def VGPR111 : VGPR_32 <111, "VGPR111", R112>; +def VGPR112 : VGPR_32 <112, "VGPR112", R113>; +def VGPR113 : VGPR_32 <113, "VGPR113", R114>; +def VGPR114 : VGPR_32 <114, "VGPR114", R115>; +def VGPR115 : VGPR_32 <115, "VGPR115", R116>; +def VGPR116 : VGPR_32 <116, "VGPR116", R117>; +def VGPR117 : VGPR_32 <117, "VGPR117", R118>; +def VGPR118 : VGPR_32 <118, "VGPR118", R119>; +def VGPR119 : VGPR_32 <119, "VGPR119", R120>; +def VGPR120 : VGPR_32 <120, "VGPR120", R121>; +def VGPR121 : VGPR_32 <121, "VGPR121", R122>; +def VGPR122 : VGPR_32 <122, "VGPR122", R123>; +def VGPR123 : VGPR_32 <123, "VGPR123", R124>; +def VGPR124 : VGPR_32 <124, "VGPR124", R125>; +def VGPR125 : VGPR_32 <125, "VGPR125", R126>; +def VGPR126 : VGPR_32 <126, "VGPR126", R127>; +def VGPR127 : VGPR_32 <127, "VGPR127", R128>; +def VGPR128 : VGPR_32 <128, "VGPR128", R129>; +def VGPR129 : VGPR_32 <129, "VGPR129", R130>; +def VGPR130 : VGPR_32 <130, "VGPR130", R131>; +def VGPR131 : VGPR_32 <131, "VGPR131", R132>; +def VGPR132 : VGPR_32 <132, "VGPR132", R133>; +def VGPR133 : VGPR_32 <133, "VGPR133", R134>; +def VGPR134 : VGPR_32 <134, "VGPR134", R135>; +def VGPR135 : VGPR_32 <135, "VGPR135", R136>; +def VGPR136 : VGPR_32 <136, "VGPR136", R137>; +def VGPR137 : VGPR_32 <137, "VGPR137", R138>; +def VGPR138 : VGPR_32 <138, "VGPR138", R139>; +def VGPR139 : VGPR_32 <139, "VGPR139", R140>; +def VGPR140 : VGPR_32 <140, "VGPR140", R141>; +def VGPR141 : VGPR_32 <141, "VGPR141", R142>; +def VGPR142 : VGPR_32 <142, "VGPR142", R143>; +def VGPR143 : VGPR_32 <143, "VGPR143", R144>; +def VGPR144 : VGPR_32 <144, "VGPR144", R145>; +def VGPR145 : VGPR_32 <145, "VGPR145", R146>; +def VGPR146 : VGPR_32 <146, "VGPR146", R147>; +def VGPR147 : VGPR_32 <147, "VGPR147", R148>; +def VGPR148 : VGPR_32 <148, "VGPR148", R149>; +def VGPR149 : VGPR_32 <149, "VGPR149", R150>; +def VGPR150 : VGPR_32 <150, "VGPR150", R151>; +def VGPR151 : VGPR_32 <151, "VGPR151", R152>; +def VGPR152 : VGPR_32 <152, "VGPR152", R153>; +def VGPR153 : VGPR_32 <153, "VGPR153", R154>; +def VGPR154 : VGPR_32 <154, "VGPR154", R155>; +def VGPR155 : VGPR_32 <155, "VGPR155", R156>; +def VGPR156 : VGPR_32 <156, "VGPR156", R157>; +def VGPR157 : VGPR_32 <157, "VGPR157", R158>; +def VGPR158 : VGPR_32 <158, "VGPR158", R159>; +def VGPR159 : VGPR_32 <159, "VGPR159", R160>; +def VGPR160 : VGPR_32 <160, "VGPR160", R161>; +def VGPR161 : VGPR_32 <161, "VGPR161", R162>; +def VGPR162 : VGPR_32 <162, "VGPR162", R163>; +def VGPR163 : VGPR_32 <163, "VGPR163", R164>; +def VGPR164 : VGPR_32 <164, "VGPR164", R165>; +def VGPR165 : VGPR_32 <165, "VGPR165", R166>; +def VGPR166 : VGPR_32 <166, "VGPR166", R167>; +def VGPR167 : VGPR_32 <167, "VGPR167", R168>; +def VGPR168 : VGPR_32 <168, "VGPR168", R169>; +def VGPR169 : VGPR_32 <169, "VGPR169", R170>; +def VGPR170 : VGPR_32 <170, "VGPR170", R171>; +def VGPR171 : VGPR_32 <171, "VGPR171", R172>; +def VGPR172 : VGPR_32 <172, "VGPR172", R173>; +def VGPR173 : VGPR_32 <173, "VGPR173", R174>; +def VGPR174 : VGPR_32 <174, "VGPR174", R175>; +def VGPR175 : VGPR_32 <175, "VGPR175", R176>; +def VGPR176 : VGPR_32 <176, "VGPR176", R177>; +def VGPR177 : VGPR_32 <177, "VGPR177", R178>; +def VGPR178 : VGPR_32 <178, "VGPR178", R179>; +def VGPR179 : VGPR_32 <179, "VGPR179", R180>; +def VGPR180 : VGPR_32 <180, "VGPR180", R181>; +def VGPR181 : VGPR_32 <181, "VGPR181", R182>; +def VGPR182 : VGPR_32 <182, "VGPR182", R183>; +def VGPR183 : VGPR_32 <183, "VGPR183", R184>; +def VGPR184 : VGPR_32 <184, "VGPR184", R185>; +def VGPR185 : VGPR_32 <185, "VGPR185", R186>; +def VGPR186 : VGPR_32 <186, "VGPR186", R187>; +def VGPR187 : VGPR_32 <187, "VGPR187", R188>; +def VGPR188 : VGPR_32 <188, "VGPR188", R189>; +def VGPR189 : VGPR_32 <189, "VGPR189", R190>; +def VGPR190 : VGPR_32 <190, "VGPR190", R191>; +def VGPR191 : VGPR_32 <191, "VGPR191", R192>; +def VGPR192 : VGPR_32 <192, "VGPR192", R193>; +def VGPR193 : VGPR_32 <193, "VGPR193", R194>; +def VGPR194 : VGPR_32 <194, "VGPR194", R195>; +def VGPR195 : VGPR_32 <195, "VGPR195", R196>; +def VGPR196 : VGPR_32 <196, "VGPR196", R197>; +def VGPR197 : VGPR_32 <197, "VGPR197", R198>; +def VGPR198 : VGPR_32 <198, "VGPR198", R199>; +def VGPR199 : VGPR_32 <199, "VGPR199", R200>; +def VGPR200 : VGPR_32 <200, "VGPR200", R201>; +def VGPR201 : VGPR_32 <201, "VGPR201", R202>; +def VGPR202 : VGPR_32 <202, "VGPR202", R203>; +def VGPR203 : VGPR_32 <203, "VGPR203", R204>; +def VGPR204 : VGPR_32 <204, "VGPR204", R205>; +def VGPR205 : VGPR_32 <205, "VGPR205", R206>; +def VGPR206 : VGPR_32 <206, "VGPR206", R207>; +def VGPR207 : VGPR_32 <207, "VGPR207", R208>; +def VGPR208 : VGPR_32 <208, "VGPR208", R209>; +def VGPR209 : VGPR_32 <209, "VGPR209", R210>; +def VGPR210 : VGPR_32 <210, "VGPR210", R211>; +def VGPR211 : VGPR_32 <211, "VGPR211", R212>; +def VGPR212 : VGPR_32 <212, "VGPR212", R213>; +def VGPR213 : VGPR_32 <213, "VGPR213", R214>; +def VGPR214 : VGPR_32 <214, "VGPR214", R215>; +def VGPR215 : VGPR_32 <215, "VGPR215", R216>; +def VGPR216 : VGPR_32 <216, "VGPR216", R217>; +def VGPR217 : VGPR_32 <217, "VGPR217", R218>; +def VGPR218 : VGPR_32 <218, "VGPR218", R219>; +def VGPR219 : VGPR_32 <219, "VGPR219", R220>; +def VGPR220 : VGPR_32 <220, "VGPR220", R221>; +def VGPR221 : VGPR_32 <221, "VGPR221", R222>; +def VGPR222 : VGPR_32 <222, "VGPR222", R223>; +def VGPR223 : VGPR_32 <223, "VGPR223", R224>; +def VGPR224 : VGPR_32 <224, "VGPR224", R225>; +def VGPR225 : VGPR_32 <225, "VGPR225", R226>; +def VGPR226 : VGPR_32 <226, "VGPR226", R227>; +def VGPR227 : VGPR_32 <227, "VGPR227", R228>; +def VGPR228 : VGPR_32 <228, "VGPR228", R229>; +def VGPR229 : VGPR_32 <229, "VGPR229", R230>; +def VGPR230 : VGPR_32 <230, "VGPR230", R231>; +def VGPR231 : VGPR_32 <231, "VGPR231", R232>; +def VGPR232 : VGPR_32 <232, "VGPR232", R233>; +def VGPR233 : VGPR_32 <233, "VGPR233", R234>; +def VGPR234 : VGPR_32 <234, "VGPR234", R235>; +def VGPR235 : VGPR_32 <235, "VGPR235", R236>; +def VGPR236 : VGPR_32 <236, "VGPR236", R237>; +def VGPR237 : VGPR_32 <237, "VGPR237", R238>; +def VGPR238 : VGPR_32 <238, "VGPR238", R239>; +def VGPR239 : VGPR_32 <239, "VGPR239", R240>; +def VGPR240 : VGPR_32 <240, "VGPR240", R241>; +def VGPR241 : VGPR_32 <241, "VGPR241", R242>; +def VGPR242 : VGPR_32 <242, "VGPR242", R243>; +def VGPR243 : VGPR_32 <243, "VGPR243", R244>; +def VGPR244 : VGPR_32 <244, "VGPR244", R245>; +def VGPR245 : VGPR_32 <245, "VGPR245", R246>; +def VGPR246 : VGPR_32 <246, "VGPR246", R247>; +def VGPR247 : VGPR_32 <247, "VGPR247", R248>; +def VGPR248 : VGPR_32 <248, "VGPR248", R249>; +def VGPR249 : VGPR_32 <249, "VGPR249", R250>; +def VGPR250 : VGPR_32 <250, "VGPR250", R251>; +def VGPR251 : VGPR_32 <251, "VGPR251", R252>; +def VGPR252 : VGPR_32 <252, "VGPR252", R253>; +def VGPR253 : VGPR_32 <253, "VGPR253", R254>; +def VGPR254 : VGPR_32 <254, "VGPR254", R255>; +def VGPR255 : VGPR_32 <255, "VGPR255", R256>; + +def SReg_32 : RegisterClass<"AMDIL", [f32, i32], 32, + (add (sequence "SGPR%u", 0, 103), SREG_LIT_0, M0) +>; + +def VReg_32 : RegisterClass<"AMDIL", [f32, i32], 32, + (add (sequence "VGPR%u", 0, 255), + PERSP_SAMPLE_I, PERSP_SAMPLE_J, + PERSP_CENTER_I, PERSP_CENTER_J, + PERSP_CENTROID_I, PERSP_CENTROID_J, + PERSP_I_W, PERSP_J_W, PERSP_1_W, + LINEAR_SAMPLE_I, LINEAR_SAMPLE_J, + LINEAR_CENTER_I, LINEAR_CENTER_J, + LINEAR_CENTROID_I, LINEAR_CENTROID_J, + LINE_STIPPLE_TEX_COORD, + POS_X_FLOAT, + POS_Y_FLOAT, + POS_Z_FLOAT, + POS_W_FLOAT, + FRONT_FACE, + ANCILLARY, + SAMPLE_COVERAGE, + POS_FIXED_PT + ) +>; + +def AllReg_32 : RegisterClass<"AMDIL", [f32, i32], 32, + (add VReg_32, + SReg_32, + (sequence "R%u", 1, 256)) +>; + +def CCReg : RegisterClass<"AMDIL", [f32], 32, (add VCC, SCC)>; + +def SGPR0_64 : SGPR_64 <0, "SGPR0_64", [ SGPR0,SGPR1]>; +def SGPR2_64 : SGPR_64 <2, "SGPR2_64", [ SGPR2,SGPR3]>; +def SGPR4_64 : SGPR_64 <4, "SGPR4_64", [ SGPR4,SGPR5]>; +def SGPR6_64 : SGPR_64 <6, "SGPR6_64", [ SGPR6,SGPR7]>; +def SGPR8_64 : SGPR_64 <8, "SGPR8_64", [ SGPR8,SGPR9]>; +def SGPR10_64 : SGPR_64 <10, "SGPR10_64", [ SGPR10,SGPR11]>; +def SGPR12_64 : SGPR_64 <12, "SGPR12_64", [ SGPR12,SGPR13]>; +def SGPR14_64 : SGPR_64 <14, "SGPR14_64", [ SGPR14,SGPR15]>; +def SGPR16_64 : SGPR_64 <16, "SGPR16_64", [ SGPR16,SGPR17]>; +def SGPR18_64 : SGPR_64 <18, "SGPR18_64", [ SGPR18,SGPR19]>; +def SGPR20_64 : SGPR_64 <20, "SGPR20_64", [ SGPR20,SGPR21]>; +def SGPR22_64 : SGPR_64 <22, "SGPR22_64", [ SGPR22,SGPR23]>; +def SGPR24_64 : SGPR_64 <24, "SGPR24_64", [ SGPR24,SGPR25]>; +def SGPR26_64 : SGPR_64 <26, "SGPR26_64", [ SGPR26,SGPR27]>; +def SGPR28_64 : SGPR_64 <28, "SGPR28_64", [ SGPR28,SGPR29]>; +def SGPR30_64 : SGPR_64 <30, "SGPR30_64", [ SGPR30,SGPR31]>; +def SGPR32_64 : SGPR_64 <32, "SGPR32_64", [ SGPR32,SGPR33]>; +def SGPR34_64 : SGPR_64 <34, "SGPR34_64", [ SGPR34,SGPR35]>; +def SGPR36_64 : SGPR_64 <36, "SGPR36_64", [ SGPR36,SGPR37]>; +def SGPR38_64 : SGPR_64 <38, "SGPR38_64", [ SGPR38,SGPR39]>; +def SGPR40_64 : SGPR_64 <40, "SGPR40_64", [ SGPR40,SGPR41]>; +def SGPR42_64 : SGPR_64 <42, "SGPR42_64", [ SGPR42,SGPR43]>; +def SGPR44_64 : SGPR_64 <44, "SGPR44_64", [ SGPR44,SGPR45]>; +def SGPR46_64 : SGPR_64 <46, "SGPR46_64", [ SGPR46,SGPR47]>; +def SGPR48_64 : SGPR_64 <48, "SGPR48_64", [ SGPR48,SGPR49]>; +def SGPR50_64 : SGPR_64 <50, "SGPR50_64", [ SGPR50,SGPR51]>; +def SGPR52_64 : SGPR_64 <52, "SGPR52_64", [ SGPR52,SGPR53]>; +def SGPR54_64 : SGPR_64 <54, "SGPR54_64", [ SGPR54,SGPR55]>; +def SGPR56_64 : SGPR_64 <56, "SGPR56_64", [ SGPR56,SGPR57]>; +def SGPR58_64 : SGPR_64 <58, "SGPR58_64", [ SGPR58,SGPR59]>; +def SGPR60_64 : SGPR_64 <60, "SGPR60_64", [ SGPR60,SGPR61]>; +def SGPR62_64 : SGPR_64 <62, "SGPR62_64", [ SGPR62,SGPR63]>; +def SGPR64_64 : SGPR_64 <64, "SGPR64_64", [ SGPR64,SGPR65]>; +def SGPR66_64 : SGPR_64 <66, "SGPR66_64", [ SGPR66,SGPR67]>; +def SGPR68_64 : SGPR_64 <68, "SGPR68_64", [ SGPR68,SGPR69]>; +def SGPR70_64 : SGPR_64 <70, "SGPR70_64", [ SGPR70,SGPR71]>; +def SGPR72_64 : SGPR_64 <72, "SGPR72_64", [ SGPR72,SGPR73]>; +def SGPR74_64 : SGPR_64 <74, "SGPR74_64", [ SGPR74,SGPR75]>; +def SGPR76_64 : SGPR_64 <76, "SGPR76_64", [ SGPR76,SGPR77]>; +def SGPR78_64 : SGPR_64 <78, "SGPR78_64", [ SGPR78,SGPR79]>; +def SGPR80_64 : SGPR_64 <80, "SGPR80_64", [ SGPR80,SGPR81]>; +def SGPR82_64 : SGPR_64 <82, "SGPR82_64", [ SGPR82,SGPR83]>; +def SGPR84_64 : SGPR_64 <84, "SGPR84_64", [ SGPR84,SGPR85]>; +def SGPR86_64 : SGPR_64 <86, "SGPR86_64", [ SGPR86,SGPR87]>; +def SGPR88_64 : SGPR_64 <88, "SGPR88_64", [ SGPR88,SGPR89]>; +def SGPR90_64 : SGPR_64 <90, "SGPR90_64", [ SGPR90,SGPR91]>; +def SGPR92_64 : SGPR_64 <92, "SGPR92_64", [ SGPR92,SGPR93]>; +def SGPR94_64 : SGPR_64 <94, "SGPR94_64", [ SGPR94,SGPR95]>; +def SGPR96_64 : SGPR_64 <96, "SGPR96_64", [ SGPR96,SGPR97]>; +def SGPR98_64 : SGPR_64 <98, "SGPR98_64", [ SGPR98,SGPR99]>; +def SGPR100_64 : SGPR_64 <100, "SGPR100_64", [ SGPR100,SGPR101]>; +def SGPR102_64 : SGPR_64 <102, "SGPR102_64", [ SGPR102,SGPR103]>; +def SReg_64 : RegisterClass<"AMDIL", [i64, iPTRAny], 64, + (add SGPR0_64 +, SGPR2_64, SGPR4_64, SGPR6_64, SGPR8_64, SGPR10_64 +, SGPR12_64, SGPR14_64, SGPR16_64, SGPR18_64, SGPR20_64 +, SGPR22_64, SGPR24_64, SGPR26_64, SGPR28_64, SGPR30_64 +, SGPR32_64, SGPR34_64, SGPR36_64, SGPR38_64, SGPR40_64 +, SGPR42_64, SGPR44_64, SGPR46_64, SGPR48_64, SGPR50_64 +, SGPR52_64, SGPR54_64, SGPR56_64, SGPR58_64, SGPR60_64 +, SGPR62_64, SGPR64_64, SGPR66_64, SGPR68_64, SGPR70_64 +, SGPR72_64, SGPR74_64, SGPR76_64, SGPR78_64, SGPR80_64 +, SGPR82_64, SGPR84_64, SGPR86_64, SGPR88_64, SGPR90_64 +, SGPR92_64, SGPR94_64, SGPR96_64, SGPR98_64, SGPR100_64 +, SGPR102_64) +>{ +} +def SGPR0_128 : SGPR_128 <0, "SGPR0_128", [ SGPR0,SGPR1,SGPR2,SGPR3]>; +def SGPR4_128 : SGPR_128 <4, "SGPR4_128", [ SGPR4,SGPR5,SGPR6,SGPR7]>; +def SGPR8_128 : SGPR_128 <8, "SGPR8_128", [ SGPR8,SGPR9,SGPR10,SGPR11]>; +def SGPR12_128 : SGPR_128 <12, "SGPR12_128", [ SGPR12,SGPR13,SGPR14,SGPR15]>; +def SGPR16_128 : SGPR_128 <16, "SGPR16_128", [ SGPR16,SGPR17,SGPR18,SGPR19]>; +def SGPR20_128 : SGPR_128 <20, "SGPR20_128", [ SGPR20,SGPR21,SGPR22,SGPR23]>; +def SGPR24_128 : SGPR_128 <24, "SGPR24_128", [ SGPR24,SGPR25,SGPR26,SGPR27]>; +def SGPR28_128 : SGPR_128 <28, "SGPR28_128", [ SGPR28,SGPR29,SGPR30,SGPR31]>; +def SGPR32_128 : SGPR_128 <32, "SGPR32_128", [ SGPR32,SGPR33,SGPR34,SGPR35]>; +def SGPR36_128 : SGPR_128 <36, "SGPR36_128", [ SGPR36,SGPR37,SGPR38,SGPR39]>; +def SGPR40_128 : SGPR_128 <40, "SGPR40_128", [ SGPR40,SGPR41,SGPR42,SGPR43]>; +def SGPR44_128 : SGPR_128 <44, "SGPR44_128", [ SGPR44,SGPR45,SGPR46,SGPR47]>; +def SGPR48_128 : SGPR_128 <48, "SGPR48_128", [ SGPR48,SGPR49,SGPR50,SGPR51]>; +def SGPR52_128 : SGPR_128 <52, "SGPR52_128", [ SGPR52,SGPR53,SGPR54,SGPR55]>; +def SGPR56_128 : SGPR_128 <56, "SGPR56_128", [ SGPR56,SGPR57,SGPR58,SGPR59]>; +def SGPR60_128 : SGPR_128 <60, "SGPR60_128", [ SGPR60,SGPR61,SGPR62,SGPR63]>; +def SGPR64_128 : SGPR_128 <64, "SGPR64_128", [ SGPR64,SGPR65,SGPR66,SGPR67]>; +def SGPR68_128 : SGPR_128 <68, "SGPR68_128", [ SGPR68,SGPR69,SGPR70,SGPR71]>; +def SGPR72_128 : SGPR_128 <72, "SGPR72_128", [ SGPR72,SGPR73,SGPR74,SGPR75]>; +def SGPR76_128 : SGPR_128 <76, "SGPR76_128", [ SGPR76,SGPR77,SGPR78,SGPR79]>; +def SGPR80_128 : SGPR_128 <80, "SGPR80_128", [ SGPR80,SGPR81,SGPR82,SGPR83]>; +def SGPR84_128 : SGPR_128 <84, "SGPR84_128", [ SGPR84,SGPR85,SGPR86,SGPR87]>; +def SGPR88_128 : SGPR_128 <88, "SGPR88_128", [ SGPR88,SGPR89,SGPR90,SGPR91]>; +def SGPR92_128 : SGPR_128 <92, "SGPR92_128", [ SGPR92,SGPR93,SGPR94,SGPR95]>; +def SGPR96_128 : SGPR_128 <96, "SGPR96_128", [ SGPR96,SGPR97,SGPR98,SGPR99]>; +def SGPR100_128 : SGPR_128 <100, "SGPR100_128", [ SGPR100,SGPR101,SGPR102,SGPR103]>; +def SReg_128 : RegisterClass<"AMDIL", [v4f32], 128, + (add SGPR0_128 +, SGPR4_128, SGPR8_128, SGPR12_128, SGPR16_128, SGPR20_128 +, SGPR24_128, SGPR28_128, SGPR32_128, SGPR36_128, SGPR40_128 +, SGPR44_128, SGPR48_128, SGPR52_128, SGPR56_128, SGPR60_128 +, SGPR64_128, SGPR68_128, SGPR72_128, SGPR76_128, SGPR80_128 +, SGPR84_128, SGPR88_128, SGPR92_128, SGPR96_128, SGPR100_128 +) +>{ +} +def SGPR0_256 : SGPR_256 <0, "SGPR0_256", [ SGPR0,SGPR1,SGPR2,SGPR3,SGPR4,SGPR5,SGPR6,SGPR7]>; +def SGPR8_256 : SGPR_256 <8, "SGPR8_256", [ SGPR8,SGPR9,SGPR10,SGPR11,SGPR12,SGPR13,SGPR14,SGPR15]>; +def SGPR16_256 : SGPR_256 <16, "SGPR16_256", [ SGPR16,SGPR17,SGPR18,SGPR19,SGPR20,SGPR21,SGPR22,SGPR23]>; +def SGPR24_256 : SGPR_256 <24, "SGPR24_256", [ SGPR24,SGPR25,SGPR26,SGPR27,SGPR28,SGPR29,SGPR30,SGPR31]>; +def SGPR32_256 : SGPR_256 <32, "SGPR32_256", [ SGPR32,SGPR33,SGPR34,SGPR35,SGPR36,SGPR37,SGPR38,SGPR39]>; +def SGPR40_256 : SGPR_256 <40, "SGPR40_256", [ SGPR40,SGPR41,SGPR42,SGPR43,SGPR44,SGPR45,SGPR46,SGPR47]>; +def SGPR48_256 : SGPR_256 <48, "SGPR48_256", [ SGPR48,SGPR49,SGPR50,SGPR51,SGPR52,SGPR53,SGPR54,SGPR55]>; +def SGPR56_256 : SGPR_256 <56, "SGPR56_256", [ SGPR56,SGPR57,SGPR58,SGPR59,SGPR60,SGPR61,SGPR62,SGPR63]>; +def SGPR64_256 : SGPR_256 <64, "SGPR64_256", [ SGPR64,SGPR65,SGPR66,SGPR67,SGPR68,SGPR69,SGPR70,SGPR71]>; +def SGPR72_256 : SGPR_256 <72, "SGPR72_256", [ SGPR72,SGPR73,SGPR74,SGPR75,SGPR76,SGPR77,SGPR78,SGPR79]>; +def SGPR80_256 : SGPR_256 <80, "SGPR80_256", [ SGPR80,SGPR81,SGPR82,SGPR83,SGPR84,SGPR85,SGPR86,SGPR87]>; +def SGPR88_256 : SGPR_256 <88, "SGPR88_256", [ SGPR88,SGPR89,SGPR90,SGPR91,SGPR92,SGPR93,SGPR94,SGPR95]>; +def SGPR96_256 : SGPR_256 <96, "SGPR96_256", [ SGPR96,SGPR97,SGPR98,SGPR99,SGPR100,SGPR101,SGPR102,SGPR103]>; +def SReg_256 : RegisterClass<"AMDIL", [v8i32], 256, + (add SGPR0_256 +, SGPR8_256, SGPR16_256, SGPR24_256, SGPR32_256, SGPR40_256 +, SGPR48_256, SGPR56_256, SGPR64_256, SGPR72_256, SGPR80_256 +, SGPR88_256, SGPR96_256) +>{ +} +def VGPR0_64 : VGPR_64 <0, "VGPR0_64", [ VGPR0,VGPR1]>; +def VGPR2_64 : VGPR_64 <2, "VGPR2_64", [ VGPR2,VGPR3]>; +def VGPR4_64 : VGPR_64 <4, "VGPR4_64", [ VGPR4,VGPR5]>; +def VGPR6_64 : VGPR_64 <6, "VGPR6_64", [ VGPR6,VGPR7]>; +def VGPR8_64 : VGPR_64 <8, "VGPR8_64", [ VGPR8,VGPR9]>; +def VGPR10_64 : VGPR_64 <10, "VGPR10_64", [ VGPR10,VGPR11]>; +def VGPR12_64 : VGPR_64 <12, "VGPR12_64", [ VGPR12,VGPR13]>; +def VGPR14_64 : VGPR_64 <14, "VGPR14_64", [ VGPR14,VGPR15]>; +def VGPR16_64 : VGPR_64 <16, "VGPR16_64", [ VGPR16,VGPR17]>; +def VGPR18_64 : VGPR_64 <18, "VGPR18_64", [ VGPR18,VGPR19]>; +def VGPR20_64 : VGPR_64 <20, "VGPR20_64", [ VGPR20,VGPR21]>; +def VGPR22_64 : VGPR_64 <22, "VGPR22_64", [ VGPR22,VGPR23]>; +def VGPR24_64 : VGPR_64 <24, "VGPR24_64", [ VGPR24,VGPR25]>; +def VGPR26_64 : VGPR_64 <26, "VGPR26_64", [ VGPR26,VGPR27]>; +def VGPR28_64 : VGPR_64 <28, "VGPR28_64", [ VGPR28,VGPR29]>; +def VGPR30_64 : VGPR_64 <30, "VGPR30_64", [ VGPR30,VGPR31]>; +def VGPR32_64 : VGPR_64 <32, "VGPR32_64", [ VGPR32,VGPR33]>; +def VGPR34_64 : VGPR_64 <34, "VGPR34_64", [ VGPR34,VGPR35]>; +def VGPR36_64 : VGPR_64 <36, "VGPR36_64", [ VGPR36,VGPR37]>; +def VGPR38_64 : VGPR_64 <38, "VGPR38_64", [ VGPR38,VGPR39]>; +def VGPR40_64 : VGPR_64 <40, "VGPR40_64", [ VGPR40,VGPR41]>; +def VGPR42_64 : VGPR_64 <42, "VGPR42_64", [ VGPR42,VGPR43]>; +def VGPR44_64 : VGPR_64 <44, "VGPR44_64", [ VGPR44,VGPR45]>; +def VGPR46_64 : VGPR_64 <46, "VGPR46_64", [ VGPR46,VGPR47]>; +def VGPR48_64 : VGPR_64 <48, "VGPR48_64", [ VGPR48,VGPR49]>; +def VGPR50_64 : VGPR_64 <50, "VGPR50_64", [ VGPR50,VGPR51]>; +def VGPR52_64 : VGPR_64 <52, "VGPR52_64", [ VGPR52,VGPR53]>; +def VGPR54_64 : VGPR_64 <54, "VGPR54_64", [ VGPR54,VGPR55]>; +def VGPR56_64 : VGPR_64 <56, "VGPR56_64", [ VGPR56,VGPR57]>; +def VGPR58_64 : VGPR_64 <58, "VGPR58_64", [ VGPR58,VGPR59]>; +def VGPR60_64 : VGPR_64 <60, "VGPR60_64", [ VGPR60,VGPR61]>; +def VGPR62_64 : VGPR_64 <62, "VGPR62_64", [ VGPR62,VGPR63]>; +def VGPR64_64 : VGPR_64 <64, "VGPR64_64", [ VGPR64,VGPR65]>; +def VGPR66_64 : VGPR_64 <66, "VGPR66_64", [ VGPR66,VGPR67]>; +def VGPR68_64 : VGPR_64 <68, "VGPR68_64", [ VGPR68,VGPR69]>; +def VGPR70_64 : VGPR_64 <70, "VGPR70_64", [ VGPR70,VGPR71]>; +def VGPR72_64 : VGPR_64 <72, "VGPR72_64", [ VGPR72,VGPR73]>; +def VGPR74_64 : VGPR_64 <74, "VGPR74_64", [ VGPR74,VGPR75]>; +def VGPR76_64 : VGPR_64 <76, "VGPR76_64", [ VGPR76,VGPR77]>; +def VGPR78_64 : VGPR_64 <78, "VGPR78_64", [ VGPR78,VGPR79]>; +def VGPR80_64 : VGPR_64 <80, "VGPR80_64", [ VGPR80,VGPR81]>; +def VGPR82_64 : VGPR_64 <82, "VGPR82_64", [ VGPR82,VGPR83]>; +def VGPR84_64 : VGPR_64 <84, "VGPR84_64", [ VGPR84,VGPR85]>; +def VGPR86_64 : VGPR_64 <86, "VGPR86_64", [ VGPR86,VGPR87]>; +def VGPR88_64 : VGPR_64 <88, "VGPR88_64", [ VGPR88,VGPR89]>; +def VGPR90_64 : VGPR_64 <90, "VGPR90_64", [ VGPR90,VGPR91]>; +def VGPR92_64 : VGPR_64 <92, "VGPR92_64", [ VGPR92,VGPR93]>; +def VGPR94_64 : VGPR_64 <94, "VGPR94_64", [ VGPR94,VGPR95]>; +def VGPR96_64 : VGPR_64 <96, "VGPR96_64", [ VGPR96,VGPR97]>; +def VGPR98_64 : VGPR_64 <98, "VGPR98_64", [ VGPR98,VGPR99]>; +def VGPR100_64 : VGPR_64 <100, "VGPR100_64", [ VGPR100,VGPR101]>; +def VGPR102_64 : VGPR_64 <102, "VGPR102_64", [ VGPR102,VGPR103]>; +def VGPR104_64 : VGPR_64 <104, "VGPR104_64", [ VGPR104,VGPR105]>; +def VGPR106_64 : VGPR_64 <106, "VGPR106_64", [ VGPR106,VGPR107]>; +def VGPR108_64 : VGPR_64 <108, "VGPR108_64", [ VGPR108,VGPR109]>; +def VGPR110_64 : VGPR_64 <110, "VGPR110_64", [ VGPR110,VGPR111]>; +def VGPR112_64 : VGPR_64 <112, "VGPR112_64", [ VGPR112,VGPR113]>; +def VGPR114_64 : VGPR_64 <114, "VGPR114_64", [ VGPR114,VGPR115]>; +def VGPR116_64 : VGPR_64 <116, "VGPR116_64", [ VGPR116,VGPR117]>; +def VGPR118_64 : VGPR_64 <118, "VGPR118_64", [ VGPR118,VGPR119]>; +def VGPR120_64 : VGPR_64 <120, "VGPR120_64", [ VGPR120,VGPR121]>; +def VGPR122_64 : VGPR_64 <122, "VGPR122_64", [ VGPR122,VGPR123]>; +def VGPR124_64 : VGPR_64 <124, "VGPR124_64", [ VGPR124,VGPR125]>; +def VGPR126_64 : VGPR_64 <126, "VGPR126_64", [ VGPR126,VGPR127]>; +def VGPR128_64 : VGPR_64 <128, "VGPR128_64", [ VGPR128,VGPR129]>; +def VGPR130_64 : VGPR_64 <130, "VGPR130_64", [ VGPR130,VGPR131]>; +def VGPR132_64 : VGPR_64 <132, "VGPR132_64", [ VGPR132,VGPR133]>; +def VGPR134_64 : VGPR_64 <134, "VGPR134_64", [ VGPR134,VGPR135]>; +def VGPR136_64 : VGPR_64 <136, "VGPR136_64", [ VGPR136,VGPR137]>; +def VGPR138_64 : VGPR_64 <138, "VGPR138_64", [ VGPR138,VGPR139]>; +def VGPR140_64 : VGPR_64 <140, "VGPR140_64", [ VGPR140,VGPR141]>; +def VGPR142_64 : VGPR_64 <142, "VGPR142_64", [ VGPR142,VGPR143]>; +def VGPR144_64 : VGPR_64 <144, "VGPR144_64", [ VGPR144,VGPR145]>; +def VGPR146_64 : VGPR_64 <146, "VGPR146_64", [ VGPR146,VGPR147]>; +def VGPR148_64 : VGPR_64 <148, "VGPR148_64", [ VGPR148,VGPR149]>; +def VGPR150_64 : VGPR_64 <150, "VGPR150_64", [ VGPR150,VGPR151]>; +def VGPR152_64 : VGPR_64 <152, "VGPR152_64", [ VGPR152,VGPR153]>; +def VGPR154_64 : VGPR_64 <154, "VGPR154_64", [ VGPR154,VGPR155]>; +def VGPR156_64 : VGPR_64 <156, "VGPR156_64", [ VGPR156,VGPR157]>; +def VGPR158_64 : VGPR_64 <158, "VGPR158_64", [ VGPR158,VGPR159]>; +def VGPR160_64 : VGPR_64 <160, "VGPR160_64", [ VGPR160,VGPR161]>; +def VGPR162_64 : VGPR_64 <162, "VGPR162_64", [ VGPR162,VGPR163]>; +def VGPR164_64 : VGPR_64 <164, "VGPR164_64", [ VGPR164,VGPR165]>; +def VGPR166_64 : VGPR_64 <166, "VGPR166_64", [ VGPR166,VGPR167]>; +def VGPR168_64 : VGPR_64 <168, "VGPR168_64", [ VGPR168,VGPR169]>; +def VGPR170_64 : VGPR_64 <170, "VGPR170_64", [ VGPR170,VGPR171]>; +def VGPR172_64 : VGPR_64 <172, "VGPR172_64", [ VGPR172,VGPR173]>; +def VGPR174_64 : VGPR_64 <174, "VGPR174_64", [ VGPR174,VGPR175]>; +def VGPR176_64 : VGPR_64 <176, "VGPR176_64", [ VGPR176,VGPR177]>; +def VGPR178_64 : VGPR_64 <178, "VGPR178_64", [ VGPR178,VGPR179]>; +def VGPR180_64 : VGPR_64 <180, "VGPR180_64", [ VGPR180,VGPR181]>; +def VGPR182_64 : VGPR_64 <182, "VGPR182_64", [ VGPR182,VGPR183]>; +def VGPR184_64 : VGPR_64 <184, "VGPR184_64", [ VGPR184,VGPR185]>; +def VGPR186_64 : VGPR_64 <186, "VGPR186_64", [ VGPR186,VGPR187]>; +def VGPR188_64 : VGPR_64 <188, "VGPR188_64", [ VGPR188,VGPR189]>; +def VGPR190_64 : VGPR_64 <190, "VGPR190_64", [ VGPR190,VGPR191]>; +def VGPR192_64 : VGPR_64 <192, "VGPR192_64", [ VGPR192,VGPR193]>; +def VGPR194_64 : VGPR_64 <194, "VGPR194_64", [ VGPR194,VGPR195]>; +def VGPR196_64 : VGPR_64 <196, "VGPR196_64", [ VGPR196,VGPR197]>; +def VGPR198_64 : VGPR_64 <198, "VGPR198_64", [ VGPR198,VGPR199]>; +def VGPR200_64 : VGPR_64 <200, "VGPR200_64", [ VGPR200,VGPR201]>; +def VGPR202_64 : VGPR_64 <202, "VGPR202_64", [ VGPR202,VGPR203]>; +def VGPR204_64 : VGPR_64 <204, "VGPR204_64", [ VGPR204,VGPR205]>; +def VGPR206_64 : VGPR_64 <206, "VGPR206_64", [ VGPR206,VGPR207]>; +def VGPR208_64 : VGPR_64 <208, "VGPR208_64", [ VGPR208,VGPR209]>; +def VGPR210_64 : VGPR_64 <210, "VGPR210_64", [ VGPR210,VGPR211]>; +def VGPR212_64 : VGPR_64 <212, "VGPR212_64", [ VGPR212,VGPR213]>; +def VGPR214_64 : VGPR_64 <214, "VGPR214_64", [ VGPR214,VGPR215]>; +def VGPR216_64 : VGPR_64 <216, "VGPR216_64", [ VGPR216,VGPR217]>; +def VGPR218_64 : VGPR_64 <218, "VGPR218_64", [ VGPR218,VGPR219]>; +def VGPR220_64 : VGPR_64 <220, "VGPR220_64", [ VGPR220,VGPR221]>; +def VGPR222_64 : VGPR_64 <222, "VGPR222_64", [ VGPR222,VGPR223]>; +def VGPR224_64 : VGPR_64 <224, "VGPR224_64", [ VGPR224,VGPR225]>; +def VGPR226_64 : VGPR_64 <226, "VGPR226_64", [ VGPR226,VGPR227]>; +def VGPR228_64 : VGPR_64 <228, "VGPR228_64", [ VGPR228,VGPR229]>; +def VGPR230_64 : VGPR_64 <230, "VGPR230_64", [ VGPR230,VGPR231]>; +def VGPR232_64 : VGPR_64 <232, "VGPR232_64", [ VGPR232,VGPR233]>; +def VGPR234_64 : VGPR_64 <234, "VGPR234_64", [ VGPR234,VGPR235]>; +def VGPR236_64 : VGPR_64 <236, "VGPR236_64", [ VGPR236,VGPR237]>; +def VGPR238_64 : VGPR_64 <238, "VGPR238_64", [ VGPR238,VGPR239]>; +def VGPR240_64 : VGPR_64 <240, "VGPR240_64", [ VGPR240,VGPR241]>; +def VGPR242_64 : VGPR_64 <242, "VGPR242_64", [ VGPR242,VGPR243]>; +def VGPR244_64 : VGPR_64 <244, "VGPR244_64", [ VGPR244,VGPR245]>; +def VGPR246_64 : VGPR_64 <246, "VGPR246_64", [ VGPR246,VGPR247]>; +def VGPR248_64 : VGPR_64 <248, "VGPR248_64", [ VGPR248,VGPR249]>; +def VGPR250_64 : VGPR_64 <250, "VGPR250_64", [ VGPR250,VGPR251]>; +def VGPR252_64 : VGPR_64 <252, "VGPR252_64", [ VGPR252,VGPR253]>; +def VGPR254_64 : VGPR_64 <254, "VGPR254_64", [ VGPR254,VGPR255]>; +def VReg_64 : RegisterClass<"AMDIL", [i64], 64, + (add VGPR0_64 +, VGPR2_64, VGPR4_64, VGPR6_64, VGPR8_64, VGPR10_64 +, VGPR12_64, VGPR14_64, VGPR16_64, VGPR18_64, VGPR20_64 +, VGPR22_64, VGPR24_64, VGPR26_64, VGPR28_64, VGPR30_64 +, VGPR32_64, VGPR34_64, VGPR36_64, VGPR38_64, VGPR40_64 +, VGPR42_64, VGPR44_64, VGPR46_64, VGPR48_64, VGPR50_64 +, VGPR52_64, VGPR54_64, VGPR56_64, VGPR58_64, VGPR60_64 +, VGPR62_64, VGPR64_64, VGPR66_64, VGPR68_64, VGPR70_64 +, VGPR72_64, VGPR74_64, VGPR76_64, VGPR78_64, VGPR80_64 +, VGPR82_64, VGPR84_64, VGPR86_64, VGPR88_64, VGPR90_64 +, VGPR92_64, VGPR94_64, VGPR96_64, VGPR98_64, VGPR100_64 +, VGPR102_64, VGPR104_64, VGPR106_64, VGPR108_64, VGPR110_64 +, VGPR112_64, VGPR114_64, VGPR116_64, VGPR118_64, VGPR120_64 +, VGPR122_64, VGPR124_64, VGPR126_64, VGPR128_64, VGPR130_64 +, VGPR132_64, VGPR134_64, VGPR136_64, VGPR138_64, VGPR140_64 +, VGPR142_64, VGPR144_64, VGPR146_64, VGPR148_64, VGPR150_64 +, VGPR152_64, VGPR154_64, VGPR156_64, VGPR158_64, VGPR160_64 +, VGPR162_64, VGPR164_64, VGPR166_64, VGPR168_64, VGPR170_64 +, VGPR172_64, VGPR174_64, VGPR176_64, VGPR178_64, VGPR180_64 +, VGPR182_64, VGPR184_64, VGPR186_64, VGPR188_64, VGPR190_64 +, VGPR192_64, VGPR194_64, VGPR196_64, VGPR198_64, VGPR200_64 +, VGPR202_64, VGPR204_64, VGPR206_64, VGPR208_64, VGPR210_64 +, VGPR212_64, VGPR214_64, VGPR216_64, VGPR218_64, VGPR220_64 +, VGPR222_64, VGPR224_64, VGPR226_64, VGPR228_64, VGPR230_64 +, VGPR232_64, VGPR234_64, VGPR236_64, VGPR238_64, VGPR240_64 +, VGPR242_64, VGPR244_64, VGPR246_64, VGPR248_64, VGPR250_64 +, VGPR252_64, VGPR254_64) +>{ +} +def VGPR0_128 : VGPR_128 <0, "VGPR0_128", [ VGPR0,VGPR1,VGPR2,VGPR3]>; +def VGPR4_128 : VGPR_128 <4, "VGPR4_128", [ VGPR4,VGPR5,VGPR6,VGPR7]>; +def VGPR8_128 : VGPR_128 <8, "VGPR8_128", [ VGPR8,VGPR9,VGPR10,VGPR11]>; +def VGPR12_128 : VGPR_128 <12, "VGPR12_128", [ VGPR12,VGPR13,VGPR14,VGPR15]>; +def VGPR16_128 : VGPR_128 <16, "VGPR16_128", [ VGPR16,VGPR17,VGPR18,VGPR19]>; +def VGPR20_128 : VGPR_128 <20, "VGPR20_128", [ VGPR20,VGPR21,VGPR22,VGPR23]>; +def VGPR24_128 : VGPR_128 <24, "VGPR24_128", [ VGPR24,VGPR25,VGPR26,VGPR27]>; +def VGPR28_128 : VGPR_128 <28, "VGPR28_128", [ VGPR28,VGPR29,VGPR30,VGPR31]>; +def VGPR32_128 : VGPR_128 <32, "VGPR32_128", [ VGPR32,VGPR33,VGPR34,VGPR35]>; +def VGPR36_128 : VGPR_128 <36, "VGPR36_128", [ VGPR36,VGPR37,VGPR38,VGPR39]>; +def VGPR40_128 : VGPR_128 <40, "VGPR40_128", [ VGPR40,VGPR41,VGPR42,VGPR43]>; +def VGPR44_128 : VGPR_128 <44, "VGPR44_128", [ VGPR44,VGPR45,VGPR46,VGPR47]>; +def VGPR48_128 : VGPR_128 <48, "VGPR48_128", [ VGPR48,VGPR49,VGPR50,VGPR51]>; +def VGPR52_128 : VGPR_128 <52, "VGPR52_128", [ VGPR52,VGPR53,VGPR54,VGPR55]>; +def VGPR56_128 : VGPR_128 <56, "VGPR56_128", [ VGPR56,VGPR57,VGPR58,VGPR59]>; +def VGPR60_128 : VGPR_128 <60, "VGPR60_128", [ VGPR60,VGPR61,VGPR62,VGPR63]>; +def VGPR64_128 : VGPR_128 <64, "VGPR64_128", [ VGPR64,VGPR65,VGPR66,VGPR67]>; +def VGPR68_128 : VGPR_128 <68, "VGPR68_128", [ VGPR68,VGPR69,VGPR70,VGPR71]>; +def VGPR72_128 : VGPR_128 <72, "VGPR72_128", [ VGPR72,VGPR73,VGPR74,VGPR75]>; +def VGPR76_128 : VGPR_128 <76, "VGPR76_128", [ VGPR76,VGPR77,VGPR78,VGPR79]>; +def VGPR80_128 : VGPR_128 <80, "VGPR80_128", [ VGPR80,VGPR81,VGPR82,VGPR83]>; +def VGPR84_128 : VGPR_128 <84, "VGPR84_128", [ VGPR84,VGPR85,VGPR86,VGPR87]>; +def VGPR88_128 : VGPR_128 <88, "VGPR88_128", [ VGPR88,VGPR89,VGPR90,VGPR91]>; +def VGPR92_128 : VGPR_128 <92, "VGPR92_128", [ VGPR92,VGPR93,VGPR94,VGPR95]>; +def VGPR96_128 : VGPR_128 <96, "VGPR96_128", [ VGPR96,VGPR97,VGPR98,VGPR99]>; +def VGPR100_128 : VGPR_128 <100, "VGPR100_128", [ VGPR100,VGPR101,VGPR102,VGPR103]>; +def VGPR104_128 : VGPR_128 <104, "VGPR104_128", [ VGPR104,VGPR105,VGPR106,VGPR107]>; +def VGPR108_128 : VGPR_128 <108, "VGPR108_128", [ VGPR108,VGPR109,VGPR110,VGPR111]>; +def VGPR112_128 : VGPR_128 <112, "VGPR112_128", [ VGPR112,VGPR113,VGPR114,VGPR115]>; +def VGPR116_128 : VGPR_128 <116, "VGPR116_128", [ VGPR116,VGPR117,VGPR118,VGPR119]>; +def VGPR120_128 : VGPR_128 <120, "VGPR120_128", [ VGPR120,VGPR121,VGPR122,VGPR123]>; +def VGPR124_128 : VGPR_128 <124, "VGPR124_128", [ VGPR124,VGPR125,VGPR126,VGPR127]>; +def VGPR128_128 : VGPR_128 <128, "VGPR128_128", [ VGPR128,VGPR129,VGPR130,VGPR131]>; +def VGPR132_128 : VGPR_128 <132, "VGPR132_128", [ VGPR132,VGPR133,VGPR134,VGPR135]>; +def VGPR136_128 : VGPR_128 <136, "VGPR136_128", [ VGPR136,VGPR137,VGPR138,VGPR139]>; +def VGPR140_128 : VGPR_128 <140, "VGPR140_128", [ VGPR140,VGPR141,VGPR142,VGPR143]>; +def VGPR144_128 : VGPR_128 <144, "VGPR144_128", [ VGPR144,VGPR145,VGPR146,VGPR147]>; +def VGPR148_128 : VGPR_128 <148, "VGPR148_128", [ VGPR148,VGPR149,VGPR150,VGPR151]>; +def VGPR152_128 : VGPR_128 <152, "VGPR152_128", [ VGPR152,VGPR153,VGPR154,VGPR155]>; +def VGPR156_128 : VGPR_128 <156, "VGPR156_128", [ VGPR156,VGPR157,VGPR158,VGPR159]>; +def VGPR160_128 : VGPR_128 <160, "VGPR160_128", [ VGPR160,VGPR161,VGPR162,VGPR163]>; +def VGPR164_128 : VGPR_128 <164, "VGPR164_128", [ VGPR164,VGPR165,VGPR166,VGPR167]>; +def VGPR168_128 : VGPR_128 <168, "VGPR168_128", [ VGPR168,VGPR169,VGPR170,VGPR171]>; +def VGPR172_128 : VGPR_128 <172, "VGPR172_128", [ VGPR172,VGPR173,VGPR174,VGPR175]>; +def VGPR176_128 : VGPR_128 <176, "VGPR176_128", [ VGPR176,VGPR177,VGPR178,VGPR179]>; +def VGPR180_128 : VGPR_128 <180, "VGPR180_128", [ VGPR180,VGPR181,VGPR182,VGPR183]>; +def VGPR184_128 : VGPR_128 <184, "VGPR184_128", [ VGPR184,VGPR185,VGPR186,VGPR187]>; +def VGPR188_128 : VGPR_128 <188, "VGPR188_128", [ VGPR188,VGPR189,VGPR190,VGPR191]>; +def VGPR192_128 : VGPR_128 <192, "VGPR192_128", [ VGPR192,VGPR193,VGPR194,VGPR195]>; +def VGPR196_128 : VGPR_128 <196, "VGPR196_128", [ VGPR196,VGPR197,VGPR198,VGPR199]>; +def VGPR200_128 : VGPR_128 <200, "VGPR200_128", [ VGPR200,VGPR201,VGPR202,VGPR203]>; +def VGPR204_128 : VGPR_128 <204, "VGPR204_128", [ VGPR204,VGPR205,VGPR206,VGPR207]>; +def VGPR208_128 : VGPR_128 <208, "VGPR208_128", [ VGPR208,VGPR209,VGPR210,VGPR211]>; +def VGPR212_128 : VGPR_128 <212, "VGPR212_128", [ VGPR212,VGPR213,VGPR214,VGPR215]>; +def VGPR216_128 : VGPR_128 <216, "VGPR216_128", [ VGPR216,VGPR217,VGPR218,VGPR219]>; +def VGPR220_128 : VGPR_128 <220, "VGPR220_128", [ VGPR220,VGPR221,VGPR222,VGPR223]>; +def VGPR224_128 : VGPR_128 <224, "VGPR224_128", [ VGPR224,VGPR225,VGPR226,VGPR227]>; +def VGPR228_128 : VGPR_128 <228, "VGPR228_128", [ VGPR228,VGPR229,VGPR230,VGPR231]>; +def VGPR232_128 : VGPR_128 <232, "VGPR232_128", [ VGPR232,VGPR233,VGPR234,VGPR235]>; +def VGPR236_128 : VGPR_128 <236, "VGPR236_128", [ VGPR236,VGPR237,VGPR238,VGPR239]>; +def VGPR240_128 : VGPR_128 <240, "VGPR240_128", [ VGPR240,VGPR241,VGPR242,VGPR243]>; +def VGPR244_128 : VGPR_128 <244, "VGPR244_128", [ VGPR244,VGPR245,VGPR246,VGPR247]>; +def VGPR248_128 : VGPR_128 <248, "VGPR248_128", [ VGPR248,VGPR249,VGPR250,VGPR251]>; +def VGPR252_128 : VGPR_128 <252, "VGPR252_128", [ VGPR252,VGPR253,VGPR254,VGPR255]>; +def VReg_128 : RegisterClass<"AMDIL", [v4f32], 128, + (add VGPR0_128 +, VGPR4_128, VGPR8_128, VGPR12_128, VGPR16_128, VGPR20_128 +, VGPR24_128, VGPR28_128, VGPR32_128, VGPR36_128, VGPR40_128 +, VGPR44_128, VGPR48_128, VGPR52_128, VGPR56_128, VGPR60_128 +, VGPR64_128, VGPR68_128, VGPR72_128, VGPR76_128, VGPR80_128 +, VGPR84_128, VGPR88_128, VGPR92_128, VGPR96_128, VGPR100_128 +, VGPR104_128, VGPR108_128, VGPR112_128, VGPR116_128, VGPR120_128 +, VGPR124_128, VGPR128_128, VGPR132_128, VGPR136_128, VGPR140_128 +, VGPR144_128, VGPR148_128, VGPR152_128, VGPR156_128, VGPR160_128 +, VGPR164_128, VGPR168_128, VGPR172_128, VGPR176_128, VGPR180_128 +, VGPR184_128, VGPR188_128, VGPR192_128, VGPR196_128, VGPR200_128 +, VGPR204_128, VGPR208_128, VGPR212_128, VGPR216_128, VGPR220_128 +, VGPR224_128, VGPR228_128, VGPR232_128, VGPR236_128, VGPR240_128 +, VGPR244_128, VGPR248_128, VGPR252_128) +>{ +} + +def AllReg_64 : RegisterClass<"AMDIL", [f64, i64], 64, + (add SGPR0_64 +,SGPR2_64,SGPR4_64,SGPR6_64,SGPR8_64,SGPR10_64 +,SGPR12_64,SGPR14_64,SGPR16_64,SGPR18_64,SGPR20_64 +,SGPR22_64,SGPR24_64,SGPR26_64,SGPR28_64,SGPR30_64 +,SGPR32_64,SGPR34_64,SGPR36_64,SGPR38_64,SGPR40_64 +,SGPR42_64,SGPR44_64,SGPR46_64,SGPR48_64,SGPR50_64 +,SGPR52_64,SGPR54_64,SGPR56_64,SGPR58_64,SGPR60_64 +,SGPR62_64,SGPR64_64,SGPR66_64,SGPR68_64,SGPR70_64 +,SGPR72_64,SGPR74_64,SGPR76_64,SGPR78_64,SGPR80_64 +,SGPR82_64,SGPR84_64,SGPR86_64,SGPR88_64,SGPR90_64 +,SGPR92_64,SGPR94_64,SGPR96_64,SGPR98_64,SGPR100_64 +,SGPR102_64, VGPR0_64 +,VGPR2_64,VGPR4_64,VGPR6_64,VGPR8_64,VGPR10_64 +,VGPR12_64,VGPR14_64,VGPR16_64,VGPR18_64,VGPR20_64 +,VGPR22_64,VGPR24_64,VGPR26_64,VGPR28_64,VGPR30_64 +,VGPR32_64,VGPR34_64,VGPR36_64,VGPR38_64,VGPR40_64 +,VGPR42_64,VGPR44_64,VGPR46_64,VGPR48_64,VGPR50_64 +,VGPR52_64,VGPR54_64,VGPR56_64,VGPR58_64,VGPR60_64 +,VGPR62_64,VGPR64_64,VGPR66_64,VGPR68_64,VGPR70_64 +,VGPR72_64,VGPR74_64,VGPR76_64,VGPR78_64,VGPR80_64 +,VGPR82_64,VGPR84_64,VGPR86_64,VGPR88_64,VGPR90_64 +,VGPR92_64,VGPR94_64,VGPR96_64,VGPR98_64,VGPR100_64 +,VGPR102_64,VGPR104_64,VGPR106_64,VGPR108_64,VGPR110_64 +,VGPR112_64,VGPR114_64,VGPR116_64,VGPR118_64,VGPR120_64 +,VGPR122_64,VGPR124_64,VGPR126_64,VGPR128_64,VGPR130_64 +,VGPR132_64,VGPR134_64,VGPR136_64,VGPR138_64,VGPR140_64 +,VGPR142_64,VGPR144_64,VGPR146_64,VGPR148_64,VGPR150_64 +,VGPR152_64,VGPR154_64,VGPR156_64,VGPR158_64,VGPR160_64 +,VGPR162_64,VGPR164_64,VGPR166_64,VGPR168_64,VGPR170_64 +,VGPR172_64,VGPR174_64,VGPR176_64,VGPR178_64,VGPR180_64 +,VGPR182_64,VGPR184_64,VGPR186_64,VGPR188_64,VGPR190_64 +,VGPR192_64,VGPR194_64,VGPR196_64,VGPR198_64,VGPR200_64 +,VGPR202_64,VGPR204_64,VGPR206_64,VGPR208_64,VGPR210_64 +,VGPR212_64,VGPR214_64,VGPR216_64,VGPR218_64,VGPR220_64 +,VGPR222_64,VGPR224_64,VGPR226_64,VGPR228_64,VGPR230_64 +,VGPR232_64,VGPR234_64,VGPR236_64,VGPR238_64,VGPR240_64 +,VGPR242_64,VGPR244_64,VGPR246_64,VGPR248_64,VGPR250_64 +,VGPR252_64,VGPR254_64) +>; + diff --git a/lib/Target/AMDIL/SISchedule.td b/lib/Target/AMDIL/SISchedule.td new file mode 100644 index 00000000000..28b65b82585 --- /dev/null +++ b/lib/Target/AMDIL/SISchedule.td @@ -0,0 +1,15 @@ +//===-- SISchedule.td - SI Scheduling definitons -------------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// TODO: This is just a place holder for now. +// +//===----------------------------------------------------------------------===// + + +def SI_Itin : ProcessorItineraries <[], [], []>; -- cgit v1.2.3