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2011-07-22ARM assembly parsing and encoding tests.Jim Grosbach1-0/+83
2011-07-22Fix test check!Bruno Cardoso Lopes1-1/+1
2011-07-22Fix PR10422 by adding the necessary AVX UCOMISD memory versions toBruno Cardoso Lopes1-0/+28
2011-07-22ARM assembly parsing and encoding tests for SMLAWB/SMLAWT.Jim Grosbach1-0/+14
2011-07-22ARM assembly parsing and encoding tests.Jim Grosbach1-1/+37
2011-07-22ARM assembly parsing and encoding of SMLAL instruction.Jim Grosbach1-0/+14
2011-07-22ARM encoding and assembly parsing of SMLAD{X} instructions.Jim Grosbach1-0/+13
2011-07-22ARM testcases for assembly parsing and encoding SMLA* instructions.Jim Grosbach1-0/+21
2011-07-22Turn shuffles into unpacks for VT == MVT::v2i64 and MVT::v2f64Rafael Espindola1-0/+26
2011-07-22ARM assembly parsing and encoding for SMC instruction.Jim Grosbach1-0/+9
2011-07-22ARM encoding and assembly parsing tests.Jim Grosbach1-0/+47
2011-07-22ARM assembly parsing and encoding for SETEND instruction.Jim Grosbach2-0/+26
2011-07-22ARM assembly parsing and encoding tests for SEL instruction.Jim Grosbach1-0/+10
2011-07-22-Inspected a AVX code block added by someone in early Feb. This was never usedBruno Cardoso Lopes2-2/+2
2011-07-22Although we already support this, add testcases for consistencyBruno Cardoso Lopes1-0/+21
2011-07-22Add a DAGCombine for transforming 128->256 casts into a simpleBruno Cardoso Lopes1-0/+26
2011-07-21Fix MergeInVectorType to check for vector types with the same allocDan Gohman1-0/+27
2011-07-21ARM parsing and encoding tests for SBC instruction.Jim Grosbach2-3/+53
2011-07-21ARM testcases for SADD/SASX parsing and encoding.Jim Grosbach1-0/+23
2011-07-21ARM assembly parsing support for RSC instruction.Jim Grosbach2-3/+52
2011-07-21ARM assembly parsing support for RSB instruction.Jim Grosbach2-3/+57
2011-07-21ARM parsing and encoding tests for RBIT, REV, REV16 and REVSH.Jim Grosbach1-0/+28
2011-07-21ARM parsing and encodings tests for saturating arithmetic insns.Jim Grosbach2-12/+60
2011-07-21ARM assembly parsing POP/PUSH mnemonics.Jim Grosbach1-0/+29
2011-07-21Add tests for ARM PKH assembly parsing.Jim Grosbach2-0/+48
2011-07-21- Register v16i16 as valid VR256 register classBruno Cardoso Lopes1-1/+12
2011-07-21Add support for 256-bit versions of VPERMIL instruction. This is a newBruno Cardoso Lopes1-0/+16
2011-07-21LSR, correct fix for rdar://9786536. Silly casting bug.Andrew Trick1-1/+1
2011-07-21LSR must sometimes sign-extend before generating double constants.Andrew Trick1-1/+20
2011-07-21LSR crashes on an empty IVUsers list.Andrew Trick1-0/+24
2011-07-20While emitting constant value, look through derived type and use underlying b...Devang Patel1-0/+61
2011-07-20Bring LICM into compliance with the new "Memory Model for Concurrent Operatio...Eli Friedman1-0/+37
2011-07-20Extend the hack for _GLOBAL_OFFSET_TABLE_ slightly; PR10389.Eli Friedman1-2/+3
2011-07-20Add parsing/encoding tests for ARM ORR instruction.Jim Grosbach2-6/+79
2011-07-20Consolidate ARM NOP encoding test.Jim Grosbach2-11/+9
2011-07-20ARM parsing and encoding tests for MVNJim Grosbach1-0/+57
2011-07-20ARM assembly parsing of MUL instruction.Jim Grosbach1-0/+14
2011-07-20PR10421: Fix a straightforward bug in the widening logic for CONCAT_VECTORS.Eli Friedman1-0/+8
2011-07-20Add MCObjectFileInfo and sink the MCSections initialization code fromEvan Cheng1-1/+1
2011-07-20indvars: Added getInsertPointForUses to find a valid place to truncate the IV.Andrew Trick1-0/+39
2011-07-20New pointer rotate test.Eric Christopher1-0/+11
2011-07-20indvars test case for r135558.Andrew Trick1-0/+7
2011-07-20indvars -disable-iv-rewrite fix: derived GEP IVsAndrew Trick1-6/+29
2011-07-19Lower memory barriers to sync instructions.Akira Hatanaka1-0/+19
2011-07-19Fix an obvious typo that's preventing x86 (32-bit) from using .literal16.Evan Cheng1-1/+1
2011-07-19PR10386: Don't try to split an edge from an indirectbr.Eli Friedman1-0/+52
2011-07-19Tweak ARM assembly parsing and printing of MSR instruction.Jim Grosbach4-42/+67
2011-07-19ARM assembly parsing of MRS instruction.Jim Grosbach2-3/+13
2011-07-19ARM assembly parsing for MRC/MRC2/MRRC/MRRC2.Jim Grosbach1-0/+14
2011-07-19Use the correct opcodes: SLLV/SRLV or AND must be used instead of SLL/SRL orAkira Hatanaka1-16/+16