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2013-06-04R600: Fix the fetch limits for R600 generation GPUsr600-gen-fixesTom Stellard2-0/+129
2013-06-05R600: Make sure to schedule AR register uses and defs in the same clauseTom Stellard1-0/+32
2013-06-05Don't print default values for NumberOfAuxSymbols and AuxiliaryData.Rafael Espindola1-0/+1
2013-06-05Revert "R600: Add a pass that merge Vector Register"Rafael Espindola1-30/+0
2013-06-05Handle relocations that don't point to symbols.Rafael Espindola2-0/+7
2013-06-04R600: Add a pass that merge Vector RegisterVincent Lejeune1-0/+30
2013-06-04R600: Const/Neg/Abs can be folded to dot4Vincent Lejeune1-0/+27
2013-06-04Cortex-R5 can issue Thumb2 integer division instructions.Evan Cheng2-20/+23
2013-06-04IndVarSimplify: check if loop invariant expansion can trapDavid Majnemer1-0/+32
2013-06-04ARM: Fix crash in ARM backend inside of ARMConstantIslandPassDavid Majnemer1-0/+14
2013-06-04R600: Swizzle texture/export instructionsVincent Lejeune1-5/+5
2013-06-04R600: Add a test for r183108Vincent Lejeune1-0/+2
2013-06-04Second part of pr16069Rafael Espindola1-1/+15
2013-06-04[llvm-symbolizer] Avoid calling slow getSymbolSize for Mach-O files. Assume t...Alexey Samsonov1-0/+5
2013-06-03SimplifyCFG: Do not transform PHI to select if doing so would be unsafeDavid Majnemer1-0/+14
2013-06-03Enable mcjit tests on ppc64 when building with cmake.Rafael Espindola1-1/+3
2013-06-03R600/SI: Add support for work item and work group intrinsicsTom Stellard1-0/+211
2013-06-03R600/SI: Add a calling convention for compute shadersTom Stellard7-10/+10
2013-06-03R600/SI: Custom lower i64 sign_extendTom Stellard1-0/+12
2013-06-03R600/SI: Add support for global loadsTom Stellard1-3/+49
2013-06-03R600: use capital letter for PV channelVincent Lejeune14-17/+17
2013-06-03Correct handling invalid filename in llvm-symbolizerAlexey Samsonov1-0/+3
2013-06-03Sparc: Add support for indirect branch and blockaddress in Sparc backend.Venkatraman Govindaraju1-0/+77
2013-06-03[Object/COFF] Fix Windows .lib name handling.Rui Ueyama3-0/+26
2013-06-03Sparc: When storing 0, use %g0 directly in the store instruction instead ofVenkatraman Govindaraju2-0/+27
2013-06-02Sparc: Combine add/or/sethi instruction with restore if possible.Venkatraman Govindaraju4-8/+125
2013-06-02Sparc: Perform leaf procedure optimization by defaultVenkatraman Govindaraju9-34/+36
2013-06-01When determining the new index for an insertelement, we may not assume that anNick Lewycky1-0/+11
2013-06-01Sparc: Mark functions calling llvm.vastart and llvm.returnaddress intrinsics ...Venkatraman Govindaraju2-0/+24
2013-06-01Disable new legacy JIT test on ARM.Tim Northover1-0/+1
2013-06-01Revert r183069: "TMP: LEA64_32r fixing"Tim Northover1-4/+3
2013-06-01TMP: LEA64_32r fixingTim Northover1-3/+4
2013-06-01X86: change MOV64ri64i32 into MOV32ri64Tim Northover2-10/+27
2013-06-01[Sparc] Generate correct code for leaf functions with stack objects Venkatraman Govindaraju1-0/+23
2013-05-31Prevent loop-unroll from making assumptions about undefined behavior.Andrew Trick2-22/+62
2013-05-31Temporarily Revert "X86: change MOV64ri64i32 into MOV32ri64" as itEric Christopher1-10/+10
2013-05-31LoopVectorize: PHIs with only outside users should prevent vectorizationArnold Schwaighofer1-0/+41
2013-05-31Modify how the formulae are rated in Loop Strength Reduce.Quentin Colombet3-9/+64
2013-05-31Unit test for SCEV fix r182989, PR16130.Andrew Trick1-3/+28
2013-05-31ARM: permit upper-case BE/LE on setend instructionTim Northover1-0/+4
2013-05-31ARM: add fstmx and fldmx instructions for assemblyTim Northover3-0/+36
2013-05-31Simplify multiplications by vectors whose elements are powers of 2.Rafael Espindola1-0/+408
2013-05-31ARM: fix VEXT encoding corner caseTim Northover1-0/+5
2013-05-31[SystemZ] Don't use LOAD and STORE REVERSED for volatile accessesRichard Sandiford4-24/+72
2013-05-31[NVPTX] Re-enable support for virtual registers in the final outputJustin Holewinski2-35/+35
2013-05-31[msan] Handle mixed track-origins and keep-going settings (llvm part).Evgeniy Stepanov1-2/+3
2013-05-31X86: change MOV64ri64i32 into MOV32ri64Tim Northover1-10/+10
2013-05-31[mips] Big-endian code generation for atomic instructions.Akira Hatanaka1-160/+335
2013-05-31Reapply with r182909 with a fix to the calculation of the new indices forNick Lewycky1-0/+21
2013-05-30Revert r182937 and r182877.Rafael Espindola25-83/+13
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