index
:
~tstellar/llvm
9.1-abi-fix
Nov13-test
Oct18-backup
assembler
assembler-Jan-06-2015
assembler-push
backup-Oct15
backup-Oct18
bfgminer
bfgminer-perf
cayman-only-bfgminer
clover-elf
clover-elf-v2
hazard-rec
hsa
image-support
indirect-addressing
indirect-wip
indirect-wip-2
indirect-wip-3
indirect-wip-4
indirect-wip-5
kernel-args-WIP
lds
lds-v2
long-alu
madk
master
master-testing
master-testing-patches
master-testing-patches-v2
master-testing-si
master-testing-v2
mi-sched-experimental
native
opencv-Sep18-patches
perf-Dec31-2014
perf-Jan-08-2015
push-jan16
r600
r600-May09
r600-alu-encoding
r600-final-push
r600-gen-fixes
r600-imm-flags
r600-initial-review
r600-initial-review-May11
r600-master
r600-private-mem-fixes
r600-private-memory
r600-review-v10
r600-review-v3
r600-review-v7
r600-review-v8
r600-review-v9
r600-rewrite-pats
r600-structurizer
r600-structurizer-v2
r600-tablegen-hwreg
r600-tablegen-reg-encoding
r600-vliw
remove-fold-operands
sched-fixes
sched-perf-Mar-27-2015
si-compute
si-compute-v3
si-fold
si-lowercase
si-scheduler
si-scheduler-v2
si-scheduler-v3
si-sgpr-copies
si-spill-fixes
si-spill-fixes-v2
si-spill-fixes-v3
si-spill-fixes-v4
smrd-cluster
struct-divergence
struct-divergence-v1
vgpr-spilling-Jan07-2014
vinterp-fix
vliw5-rebase
vlj-bottom-up
Unnamed repository; edit this file 'description' to name the repository.
tstellar
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
test
Age
Commit message (
Expand
)
Author
Files
Lines
2014-11-21
R600/SI: Emit s_mov_b32 m0, -1 before every DS instruction
Tom Stellard
1
-1
/
+2
2014-11-21
R600/SI: Add SIFoldOperands pass
Tom Stellard
3
-28
/
+57
2014-11-21
[mips][microMIPS] This patch implements functionality in MIPS delay slot
Jozef Kolek
2
-1
/
+20
2014-11-21
R600/SI: Use hex notation for constant in test
Tom Stellard
1
-1
/
+1
2014-11-21
[Hexagon] Adding sxth instruction.
Colin LeMahieu
1
-0
/
+10
2014-11-21
[Hexagon] Adding sxtb instruction. Renaming some identically named classes t...
Colin LeMahieu
1
-0
/
+10
2014-11-21
Debug Info: revert r222195, r222210 and r222239.
Manman Ren
1
-74
/
+0
2014-11-21
Add a feature flag for slow 32-byte unaligned memory accesses [x86].
Sanjay Patel
2
-13
/
+46
2014-11-21
[x86] Restructure the checking patterns for v16 and v32 avx2 vector
Chandler Carruth
3
-36
/
+23
2014-11-21
[x86] Make the previous logic significantly less conservative and get
Chandler Carruth
2
-80
/
+32
2014-11-21
[DAG] Teach how to turn a build_vector into a shuffle if some of the operands...
Andrea Di Biagio
1
-12
/
+49
2014-11-21
[x86] Teach the x86 vector shuffle lowering to detect mergable 128-bit
Chandler Carruth
7
-201
/
+82
2014-11-21
[x86] Remove more windows line endings that slipped into this file...
Chandler Carruth
1
-113
/
+113
2014-11-21
[x86] Add a bunch of test cases to 256-bit shuffles that exercise
Chandler Carruth
3
-0
/
+338
2014-11-21
[X86] For Silvermont CPU use 16-bit division instead of 64-bit for small posi...
Alexey Volkov
1
-0
/
+28
2014-11-21
[asan] Add new hidden compile-time flag asan-instrument-allocas to sanitize v...
Yury Gribov
1
-0
/
+24
2014-11-21
DAGCombiner: Allow the DAGCombiner to combine multiple FDIVs with the same di...
Hao Liu
1
-0
/
+94
2014-11-21
[PPC] Use SeparateConstOffsetFromGEP
Hal Finkel
1
-0
/
+157
2014-11-21
SROA: The alloca type isn't a candidate promotion type for vectors
David Majnemer
1
-0
/
+19
2014-11-21
[X86] Do not custom lower UINT_TO_FP when the target type does not
Quentin Colombet
1
-0
/
+11
2014-11-20
Fix a trip-count overflow issue in LoopUnroll.
Michael Zolotukhin
2
-1
/
+31
2014-11-20
X86: use the correct alloca symbol for Windows Itanium
Saleem Abdulrasool
1
-0
/
+16
2014-11-20
MCJIT tests passing on ARM after r222414 fixed the relocation
Renato Golin
2
-2
/
+2
2014-11-20
[ELF] Prevent ARM ELF object writer from generating deprecated relocation cod...
Jyoti Allur
2
-3
/
+2
2014-11-20
Add a test for r221870
David Majnemer
2
-0
/
+8
2014-11-19
[Hexagon] Adding A2_xor instruction with IR selection pattern and test.
Colin LeMahieu
1
-0
/
+10
2014-11-19
Revert "[Reassociate] As the expression tree is rewritten make sure the opera...
Chad Rosier
16
-54
/
+53
2014-11-19
[Hexagon] Adding A2_or instruction with IR selection pattern and test.
Colin LeMahieu
1
-0
/
+10
2014-11-19
[X86] Improved lowering of v4x32 build_vector dag nodes.
Andrea Di Biagio
2
-23
/
+138
2014-11-19
R600/SI: Make SIInstrInfo::isOperandLegal() more strict
Tom Stellard
2
-15
/
+15
2014-11-19
[mips][micromips] Implement SWM32 and LWM32 instructions
Zoran Jovanovic
4
-24
/
+67
2014-11-19
Vectorize a reduction chain feeding into a 'return' statement.
Suyog Sarda
1
-0
/
+54
2014-11-19
[mips][microMIPS] Fix opcodes of MFHC1 and MTHC1 instructions.
Jozef Kolek
1
-0
/
+6
2014-11-19
Fix tail recursion elimination
Arnaud A. de Grandmaison
1
-0
/
+26
2014-11-19
[mips][microMIPS] Implement CodeGen support for 16-bit instruction ADDIUR2.
Jozef Kolek
1
-0
/
+7
2014-11-19
[mips][microMIPS] Implement CodeGen support for ADDIUS5 instruction.
Jozef Kolek
1
-0
/
+25
2014-11-19
[mips][microMIPS] Add disassembler tests for new microMIPS 32-bit
Jozef Kolek
2
-0
/
+42
2014-11-19
[mips][microMIPS] Implement LWXS instruction.
Jozef Kolek
1
-0
/
+3
2014-11-19
[mips][microMIPS] Implement SDBBP and RDHWR instructions.
Jozef Kolek
2
-0
/
+30
2014-11-19
[X86][SSE] pslldq/psrldq byte shifts/rotation for SSE2
Simon Pilgrim
5
-352
/
+143
2014-11-19
AliasSetTracker: UnknownInsts should contribute to the refcount
David Majnemer
1
-0
/
+40
2014-11-19
[AArch64] Enable SeparateConstOffsetFromGEP, EarlyCSE and LICM passes on AArc...
Hao Liu
3
-2
/
+165
2014-11-19
llvm-readobj: fix off-by-one error in COFFDumper
Rui Ueyama
1
-17
/
+21
2014-11-19
[Aarch64] Customer lowering of CTPOP to SIMD should check for NEON availability
Weiming Zhao
1
-0
/
+14
2014-11-19
[asan] add experimental basic-block tracing to asan-coverage; also fix -fsani...
Kostya Serebryany
2
-0
/
+34
2014-11-19
llvm-readobj: teach it how to dump COFF base relocation table
Rui Ueyama
2
-0
/
+20
2014-11-19
Revert r222039 because of bot failure.
Manman Ren
2
-56
/
+7
2014-11-19
R600/SI: Implement areMemAccessesTriviallyDisjoint
Matt Arsenault
1
-0
/
+238
2014-11-18
[X86][AVX] 256-bit vector stack unaligned load/stores identification
Simon Pilgrim
2
-16
/
+155
2014-11-18
[Hexagon] Adding A2_and instruction.
Colin LeMahieu
1
-0
/
+10
[next]