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2014-11-21[asan] remove old experimental codeKostya Serebryany1-23/+0
2014-11-21R600/SI: Add a failing test case for offset order in ds_read2 instructionsTom Stellard1-0/+44
2014-11-21R600/SI: Emit s_mov_b32 m0, -1 before every DS instructionTom Stellard1-1/+2
2014-11-21R600/SI: Add SIFoldOperands passTom Stellard3-28/+57
2014-11-21[mips][microMIPS] This patch implements functionality in MIPS delay slotJozef Kolek2-1/+20
2014-11-21R600/SI: Use hex notation for constant in testTom Stellard1-1/+1
2014-11-21[Hexagon] Adding sxth instruction.Colin LeMahieu1-0/+10
2014-11-21[Hexagon] Adding sxtb instruction. Renaming some identically named classes t...Colin LeMahieu1-0/+10
2014-11-21Debug Info: revert r222195, r222210 and r222239.Manman Ren1-74/+0
2014-11-21Add a feature flag for slow 32-byte unaligned memory accesses [x86].Sanjay Patel2-13/+46
2014-11-21[x86] Restructure the checking patterns for v16 and v32 avx2 vectorChandler Carruth3-36/+23
2014-11-21[x86] Make the previous logic significantly less conservative and getChandler Carruth2-80/+32
2014-11-21[DAG] Teach how to turn a build_vector into a shuffle if some of the operands...Andrea Di Biagio1-12/+49
2014-11-21[x86] Teach the x86 vector shuffle lowering to detect mergable 128-bitChandler Carruth7-201/+82
2014-11-21[x86] Remove more windows line endings that slipped into this file...Chandler Carruth1-113/+113
2014-11-21[x86] Add a bunch of test cases to 256-bit shuffles that exerciseChandler Carruth3-0/+338
2014-11-21[X86] For Silvermont CPU use 16-bit division instead of 64-bit for small posi...Alexey Volkov1-0/+28
2014-11-21[asan] Add new hidden compile-time flag asan-instrument-allocas to sanitize v...Yury Gribov1-0/+24
2014-11-21DAGCombiner: Allow the DAGCombiner to combine multiple FDIVs with the same di...Hao Liu1-0/+94
2014-11-21[PPC] Use SeparateConstOffsetFromGEPHal Finkel1-0/+157
2014-11-21SROA: The alloca type isn't a candidate promotion type for vectorsDavid Majnemer1-0/+19
2014-11-21[X86] Do not custom lower UINT_TO_FP when the target type does notQuentin Colombet1-0/+11
2014-11-20Fix a trip-count overflow issue in LoopUnroll.Michael Zolotukhin2-1/+31
2014-11-20X86: use the correct alloca symbol for Windows ItaniumSaleem Abdulrasool1-0/+16
2014-11-20MCJIT tests passing on ARM after r222414 fixed the relocationRenato Golin2-2/+2
2014-11-20[ELF] Prevent ARM ELF object writer from generating deprecated relocation cod...Jyoti Allur2-3/+2
2014-11-20Add a test for r221870David Majnemer2-0/+8
2014-11-19[Hexagon] Adding A2_xor instruction with IR selection pattern and test.Colin LeMahieu1-0/+10
2014-11-19Revert "[Reassociate] As the expression tree is rewritten make sure the opera...Chad Rosier16-54/+53
2014-11-19[Hexagon] Adding A2_or instruction with IR selection pattern and test.Colin LeMahieu1-0/+10
2014-11-19[X86] Improved lowering of v4x32 build_vector dag nodes.Andrea Di Biagio2-23/+138
2014-11-19R600/SI: Make SIInstrInfo::isOperandLegal() more strictTom Stellard2-15/+15
2014-11-19[mips][micromips] Implement SWM32 and LWM32 instructionsZoran Jovanovic4-24/+67
2014-11-19Vectorize a reduction chain feeding into a 'return' statement.Suyog Sarda1-0/+54
2014-11-19[mips][microMIPS] Fix opcodes of MFHC1 and MTHC1 instructions.Jozef Kolek1-0/+6
2014-11-19Fix tail recursion eliminationArnaud A. de Grandmaison1-0/+26
2014-11-19[mips][microMIPS] Implement CodeGen support for 16-bit instruction ADDIUR2.Jozef Kolek1-0/+7
2014-11-19[mips][microMIPS] Implement CodeGen support for ADDIUS5 instruction.Jozef Kolek1-0/+25
2014-11-19[mips][microMIPS] Add disassembler tests for new microMIPS 32-bitJozef Kolek2-0/+42
2014-11-19[mips][microMIPS] Implement LWXS instruction.Jozef Kolek1-0/+3
2014-11-19[mips][microMIPS] Implement SDBBP and RDHWR instructions.Jozef Kolek2-0/+30
2014-11-19[X86][SSE] pslldq/psrldq byte shifts/rotation for SSE2Simon Pilgrim5-352/+143
2014-11-19AliasSetTracker: UnknownInsts should contribute to the refcountDavid Majnemer1-0/+40
2014-11-19[AArch64] Enable SeparateConstOffsetFromGEP, EarlyCSE and LICM passes on AArc...Hao Liu3-2/+165
2014-11-19llvm-readobj: fix off-by-one error in COFFDumperRui Ueyama1-17/+21
2014-11-19[Aarch64] Customer lowering of CTPOP to SIMD should check for NEON availabilityWeiming Zhao1-0/+14
2014-11-19[asan] add experimental basic-block tracing to asan-coverage; also fix -fsani...Kostya Serebryany2-0/+34
2014-11-19llvm-readobj: teach it how to dump COFF base relocation tableRui Ueyama2-0/+20
2014-11-19Revert r222039 because of bot failure.Manman Ren2-56/+7
2014-11-19R600/SI: Implement areMemAccessesTriviallyDisjointMatt Arsenault1-0/+238
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