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AgeCommit message (Expand)AuthorFilesLines
2014-05-15ARM64: print correct aliases for NEON mov & mvn instructionsTim Northover1-5/+5
2014-05-15TableGen/ARM64: print aliases even if they have syntax variants.Tim Northover2-6/+4
2014-05-14ARM: implement support for the UDF mnemonicSaleem Abdulrasool1-39/+0
2014-05-12TableGen: use PrintMethods to print more aliasesTim Northover1-28/+28
2014-05-12[mips] Move disassembler test (test_2r_msa64) into correct folder.Matheus Almeida1-0/+3
2014-05-12[mips] Move disassembler test (Mips MSA test_vec) into correct folder.Matheus Almeida1-0/+9
2014-05-12[mips] Move disassembler tests (Mips MSA test_i*, test_mi10) into correct fol...Matheus Almeida4-0/+92
2014-05-12[mips] Move disassembler tests (Mips MSA test_elm*) into correct folder.Matheus Almeida5-0/+37
2014-05-12[mips] Move disassembler tests (Mips MSA test_lsa, test_dlsa) into correct fo...Matheus Almeida2-0/+12
2014-05-12[mips] Move disassembler test (Mips MSA test_ctrlregs) into correct folder.Matheus Almeida1-0/+35
2014-05-12[mips] Move disassembler test (Mips MSA test_bit) into correct folder.Matheus Almeida1-0/+50
2014-05-12[mips] Move disassembler tests (Mips MSA test_2r, test_2rf, test_3r, test_3rf...Matheus Almeida4-0/+379
2014-05-07AArch64/ARM64: disable test directory if ARM64 not presentTim Northover1-1/+1
2014-05-06AArch64/ARM64: implement diagnosis of unpredictable loads & storesTim Northover1-0/+1
2014-05-01AArch64/ARM64: rewrite test to use FileCheck & add ARM64 linesTim Northover1-22/+45
2014-05-01AArch64/ARM64: port basic disassembly tests to ARM64.Tim Northover8-1145/+1153
2014-05-01AArch64/ARM64: print BFM instructions as BFI or BFXILTim Northover1-2/+2
2014-04-30ARM64: print fp immediates without using scientific notation.Tim Northover2-7/+7
2014-04-30ARM64: print lsr instead of lsrv for variable shifts (etc)Tim Northover1-8/+8
2014-04-30ARM64: use hex immediates for movz/movk instructionsTim Northover1-12/+12
2014-04-30ARM64: hexify printing various immediate operandsTim Northover2-64/+63
2014-04-30ARM64: print canonical syntax for add/sub (imm) instructions.Tim Northover1-8/+8
2014-04-25[ARM64] Print preferred aliases for SFBM/UBFM in InstPrinterBradley Smith1-4/+4
2014-04-25[ARM64] Support crc predicate on ARM64.Kevin Qin1-1/+1
2014-04-24AArch64: print NEON lists with a space.Tim Northover1-77/+77
2014-04-23X86Disassembler - fixed a bug in immediate printElena Demikhovsky1-0/+4
2014-04-23[ARM64] Enable feature predicates for NEON / FP / CRYPTO.Kevin Qin5-6/+6
2014-04-17[X86] Add disassembler support for the 0x0f 0x7f form of movq %mm, %mm.Craig Topper1-0/+3
2014-04-09[ARM64] Change SYS without a register to an alias to make disassembling more ...Bradley Smith1-0/+2
2014-04-09[ARM64] Correctly disassemble ISB operand as ISB not DBarrier.Bradley Smith1-0/+2
2014-04-09[ARM64] Properly support both apple and standard syntax for FMOVBradley Smith2-1/+8
2014-04-09[ARM64] Flag setting logical/add/sub immediate instructions don't use SP.Bradley Smith2-0/+10
2014-04-09[ARM64] Fix disassembly logic for extended loads/stores with 32-bit registers.Bradley Smith1-3/+7
2014-04-09[ARM64] SXTW/UXTW are only valid aliases for 32-bit operations.Bradley Smith1-0/+4
2014-04-09[ARM64] Fix canonicalisation of MOVs. MOV is too complex to be modelled by a ...Bradley Smith1-0/+4
2014-04-09[ARM64] Ensure sp is decoded as SP, not XZR in LD1 instructions.Bradley Smith1-0/+2
2014-04-09[ARM64] Rename LR to the UAL-compliant 'X30'.Bradley Smith1-4/+4
2014-04-09[ARM64] Rename FP to the UAL-compliant 'X29'.Bradley Smith1-4/+4
2014-04-09[ARM64] Add a PostEncoderMethod to FCMP - the Rm field should canonically be ...Bradley Smith1-0/+4
2014-04-09[ARM64] SCVTF and FCVTZS/U are undefined if scale<5> == 0.Bradley Smith1-0/+5
2014-04-09[ARM64] EXT and EXTR instructions on v8i8 and W regs respectively must have t...Bradley Smith1-0/+3
2014-04-09[ARM64] UBFM/BFM is undefined on w registers when imms<5> or immr<5> is 1.Bradley Smith1-0/+2
2014-04-09[ARM64] Port over the PostEncoderMethod fix for SMULH/UMULH from AArch64.Bradley Smith1-0/+4
2014-04-09[ARM64] Port over the PostEncoderMethod from AArch64 for exclusive loads and ...Bradley Smith1-0/+5
2014-04-09[ARM64] Move CPSRField and DBarrier operands over to AArch64-style disassembl...Bradley Smith1-1/+1
2014-04-09[ARM64] Switch the decoder, disassembler, instprinter and asmparser over to u...Bradley Smith1-6/+6
2014-04-09[ARM64] Shifted register ALU ops are reserved if sf=0 and imm6<5>=1, and also...Bradley Smith2-24/+29
2014-04-09[ARM64] STRHro and STRBro were not being decoded at all.Bradley Smith1-0/+2
2014-04-09[ARM64] MOVK with sf=0 and hw<1>=1 is unallocated. Shift amount for ADD/SUB i...Bradley Smith1-1/+10
2014-04-09[ARM64] Register-offset loads and stores with the 'option' field equal to 00x...Bradley Smith1-0/+7