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AgeCommit message (Expand)AuthorFilesLines
2012-10-18Clear unknown mem ops when merging stack slots (pr14090)Sebastian Pop1-0/+76
2012-10-18In SimplifySelectOps we pulled two loads through a select node despite the fa...Nadav Rotem1-0/+61
2012-10-18This patch fixes failures in the SingleSource/Regression/C/uint64_to_floatUlrich Weigand1-0/+27
2012-10-17Revert part of r166049 back and enable test case in r166125.Michael Liao1-1/+0
2012-10-17Disable extract-concat test case temporarilyMichael Liao1-1/+2
2012-10-17Revert r166049Michael Liao1-18/+0
2012-10-17Add conditional branch instructions and their patterns.Reed Kotler10-0/+281
2012-10-17Teach DAG combine to fold (extract_subvec (concat v1, ..) i) to v_iMichael Liao1-0/+17
2012-10-17Fix fallout from RegInfo => FrameLowering refactoring on MSP430.Anton Korobeynikov1-0/+17
2012-10-17Fix setjmp on models with non-Small code model nor non-Static relocation modelMichael Liao1-2/+16
2012-10-16Avoid rematerializing a redef immediately after the old def.Jakob Stoklund Olesen1-0/+23
2012-10-16Revert r166046 "Switch back to the old coalescer for now to fix the 32 bit bit"Jakob Stoklund Olesen2-24/+1
2012-10-16Teach DAG combine to fold (trunc (fptoXi x)) to (fptoXi x)Michael Liao1-0/+18
2012-10-16Switch back to the old coalescer for now to fix the 32 bit bitRafael Espindola2-1/+24
2012-10-16This patch addresses PR13949.Bill Schmidt2-18/+257
2012-10-16Issue:Stepan Dyatkovskiy2-12/+61
2012-10-16Reapply r165661, Patch by Shuxin Yang <shuxin.llvm@gmail.com>.NAKAMURA Takumi1-0/+16
2012-10-16Fix the cpu name and add -verify-machineinstrs.Rafael Espindola1-1/+1
2012-10-16misched: Added handleMove support for updating all kill flags, not just for a...Andrew Trick1-2/+27
2012-10-15Add __builtin_setjmp/_longjmp supprt in X86 backendMichael Liao1-0/+46
2012-10-15ARM: v1i64 and v2i64 VBSL intrinsic support.Jim Grosbach1-0/+30
2012-10-15Check output of the misched unit testsAndrew Trick1-1/+2
2012-10-15Add a cpu to try to fix the atom builder.Rafael Espindola1-1/+1
2012-10-15Add testcase for pr14088.Rafael Espindola1-0/+25
2012-10-15misched tests: add a triple to speculatively fix windows builders.Andrew Trick1-2/+2
2012-10-15misched: ILP scheduler for experimental heuristics.Andrew Trick1-0/+25
2012-10-15Fixed PR13938: the ARM backend was crashing because it couldn't select a VDUP...Silviu Baranga1-0/+36
2012-10-13Drop <def,dead> flags when merging into an unused lane.Jakob Stoklund Olesen1-1/+27
2012-10-13Allow for loops in LiveIntervals::pruneValue().Jakob Stoklund Olesen1-0/+49
2012-10-13X86: Fix accidentally swapped operands.Benjamin Kramer1-4/+4
2012-10-13X86: Promote i8 cmov when both operands are coming from truncates of the same...Benjamin Kramer1-0/+13
2012-10-12ARM: tail-call inside a function where part of a byval argument is on caller'sManman Ren2-0/+49
2012-10-12Fix buildbots: -misched=shuffle is only available in +Asserts builds.Jakob Stoklund Olesen1-0/+1
2012-10-12ARM: Mark VSELECT as 'expand'.Jim Grosbach1-0/+12
2012-10-12Use a transposed algorithm for handleMove().Jakob Stoklund Olesen1-0/+73
2012-10-12Fix coalescing with IMPLICIT_DEF values.Jakob Stoklund Olesen1-0/+103
2012-10-12llvm/test/CodeGen/PowerPC/2012-10-12-bitcast.ll: Try to fix failure on non-pp...NAKAMURA Takumi1-1/+1
2012-10-12Fix big-endian codegen bug in DAGTypeLegalizer::ExpandRes_BITCASTUlrich Weigand1-0/+20
2012-10-12Div, Rem int/unsigned int Reed Kotler6-0/+117
2012-10-12Legalizer optimize a pair of div / mod to a call to divrem libcall if they areEvan Cheng1-12/+34
2012-10-11Pass an explicit operand number to addLiveIns.Jakob Stoklund Olesen1-0/+32
2012-10-11This patch addresses PR13947.Bill Schmidt1-0/+97
2012-10-11Revert r165661, "Patch by Shuxin Yang <shuxin.llvm@gmail.com>."NAKAMURA Takumi1-16/+0
2012-10-10Add isel patterns for v2f32 / v4f32 neon.vbsl intrinsics. rdar://12471808Evan Cheng1-0/+18
2012-10-10Add -mattr=+altivec and remove XFAIL.Bill Schmidt1-3/+2
2012-10-10XFAIL for all targets pending investigationBill Schmidt1-2/+3
2012-10-10Patch by Shuxin Yang <shuxin.llvm@gmail.com>.Nadav Rotem1-0/+16
2012-10-10When generating spill and reload code for vector registers on PowerPC,Bill Schmidt1-0/+19
2012-10-10The PowerPC VRSAVE register has been somewhat of an odd beast sinceBill Schmidt1-0/+15
2012-10-10Specify CPU model to avoid breaking ATOM buildsMichael Liao2-4/+4