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2013-04-20R600: Convert the rest of the patternsr600-rewrite-patsTom Stellard1-26/+26
2013-04-20R600: Begin pattern conversionTom Stellard1-123/+74
2013-04-20R600: Convert AMDGPUInstructions.td to the new syntax.Tom Stellard3-114/+104
2013-04-20R600/SI: remove register classes from the remaining patternsChristian König1-20/+19
Signed-off-by: Christian K??nig <christian.koenig@amd.com>
2013-04-20R600/SI: remove register classes from image sampling patternsChristian König1-51/+41
Signed-off-by: Christian K??nig <christian.koenig@amd.com>
2013-04-20R600/SI: remove register classes from modifier patternsChristian König1-6/+6
Signed-off-by: Christian K??nig <christian.koenig@amd.com>
2013-04-20R600/SI: remove reg classes from interpolation patternsChristian König1-7/+7
Signed-off-by: Christian K??nig <christian.koenig@amd.com>
2013-04-20R600/SI: remove reg classes from instrinsic patternsChristian König1-29/+29
Signed-off-by: Christian K??nig <christian.koenig@amd.com>
2013-04-20R600/SI: remove reg classes from VOP3 patternsChristian König1-2/+4
Signed-off-by: Christian K??nig <christian.koenig@amd.com>
2013-04-20R600/SI: remove reg classes from constant load patternsChristian König1-6/+7
Signed-off-by: Christian K??nig <christian.koenig@amd.com>
2013-04-20R600/SI: start reworking patternsChristian König1-22/+14
We don't need register classes in patterns any longer. Let's start with the indirect addressing patterns. Signed-off-by: Christian K??nig <christian.koenig@amd.com>
2013-04-20R600/SI: remove nonsense select patternChristian König1-8/+1
Fortunately this pattern never matched, otherwise we would have generated incorrect code. Signed-off-by: Christian K??nig <christian.koenig@amd.com>
2013-04-19Add an MRI::verifyUseLists() function.Jakob Stoklund Olesen2-3/+54
This checks the sanity of the register use lists in the MI intermediate representation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179895 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19Use dbgs() consistently for -debug printoutsEli Bendersky1-13/+13
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179894 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19Do not mangle in MS-way the globals with magic \001 in the name.Anton Korobeynikov1-1/+6
Based on the patch by David Nadlinger! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179889 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19LoopVectorizer: Use matcher from PatternMatch.h for the min/max patternsArnold Schwaighofer1-104/+102
Also make some static function class functions to avoid having to mention the class namespace for enums all the time. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179886 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-1980-col fixup.Eric Christopher1-1/+2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179881 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19Rename ClassType to the more accurate UnderlyingType and document its purpose.Adrian Prantl1-3/+3
rdar://problem/13463793 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179877 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19[ms-inline asm] Make code layout more canonical with iniline asm handled last.Chad Rosier1-13/+13
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179875 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19[mips] First patch which adds support for micromips.Akira Hatanaka5-35/+190
This patch adds support for recoded (meaning assembly-language compatible to standard mips32) arithmetic 32-bit instructions. Patch by Zoran Jovanovic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179873 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19[mips] Fix InstAlias of XOR and OR macros. Set EmitAlias flag and changeAkira Hatanaka1-2/+2
operand type to uimm16. Patch by Vladimir Medic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179872 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19[ms-inline asm] Refactor the parsing of identifiers. No functional changeChad Rosier1-39/+33
indended. Part of rdar://13663589 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179871 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19[ms-inline asm] Remove these asserts. C++ variables that use namespaceChad Rosier1-2/+0
qualifiers don't necessarily begin with an identifier (e.g., ::foo::bar). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179867 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19[ms-inline asm] Move this variable into the scope in which it is used.Chad Rosier1-1/+1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179866 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19[ms-inline asm] Make this a hard error.Chad Rosier1-4/+4
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179865 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19ConstantFolding: ComputeMaskedBits wants the scalar size for vectors.Benjamin Kramer1-1/+1
Fixes PR15791. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179859 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19[ms-inline asm] Cleanup the dot operator implementation.Chad Rosier1-29/+15
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179856 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19ARM: Permit "sp" in ARM variant of STREXD instructionsTim Northover1-1/+1
Patch from Mihail Popa git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179854 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19refactor the struct byte swapping to a helper function.Rafael Espindola1-70/+20
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179851 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19Attributes: Don't print trailing whitespace on the function attribute comment.Benjamin Kramer1-5/+4
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179849 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19Don't read one command past the end.Rafael Espindola1-2/+6
Thanks to Evgeniy Stepanov for reporting this. It might be a good idea to add a command iterator abstraction to MachO.h, but this fixes the bug for now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179848 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19ARM: permit "sp" in ARM variants of MOVW/MOVT instructionsTim Northover1-2/+3
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179847 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19Revert "PR14606: debug info imported_module support"Eric Christopher4-73/+6
This reverts commit r179836 as it seems to have caused test failures. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179840 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19PR14606: debug info imported_module supportDavid Blaikie4-6/+73
Adding another CU-wide list, in this case of imported_modules (since they should be relatively rare, it seemed better to add a list where each element had a "context" value, rather than add a (usually empty) list to every scope). This takes care of DW_TAG_imported_module, but to fully address PR14606 we'll need to expand this to cover DW_TAG_imported_declaration too. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179836 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19Use 'array_lengthof' as possible to avoid magic numbersMichael Liao1-23/+32
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179833 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19R600: Add pattern for the BFI_INT instructionTom Stellard3-0/+24
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179830 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19R600/SI: Use InstFlag for VOP3 modifier operandsTom Stellard2-15/+14
InstFlag has a default value of 0 and will simplify the VOP3 patterns. Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179829 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19Keep coding stanard. Don't use "else if" after "return".Jakub Staszak1-3/+4
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179826 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19Add some more stats for fast isel vs. SelectionDAG, w.r.t lowering functionEli Bendersky1-1/+10
arguments in entry BBs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179824 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19Use an enum instead of magic constants to improve readability.Bill Wendling2-16/+44
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179820 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18Implement a better fix for PR15185.Bill Wendling1-6/+11
If the return type is a pointer and the call returns an integer, then do the inttoptr convertions. And vice versa. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179817 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18Relax this assert. It may not hold in all cases.Bill Wendling1-1/+1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179814 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18[ms-inline asm] Apply the condition code mnemonic aliases to both the Intel andChad Rosier1-1/+1
AT&T dialect. Test case for r179804 as well. rdar://13674398 and PR13340. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179813 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18Assert if we're trying to generate a null compact unwind entry.Bill Wendling1-4/+2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179809 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18Set the compact unwind encoding to 'requires EH DWARF' if we cannot generate ↵Bill Wendling1-9/+9
a CU encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179808 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18Disable PPC comparison optimization by defaultHal Finkel1-0/+6
This seems to cause a stage-2 LLVM compile failure (by crashing TableGen); do I'm disabling this for now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179807 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18[asm parser] Add support for predicating MnemonicAlias based on the assemblerChad Rosier3-67/+74
variant/dialect. Addresses a FIXME in the emitMnemonicAliases function. Use and test case to come shortly. rdar://13688439 and part of PR13340. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179804 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18Implement optimizeCompareInstr for PPCHal Finkel2-0/+312
Many PPC instructions have a so-called 'record form' which stores to a specific condition register the result of comparing the result of the instruction with zero (always as a signed comparison). For integer operations on PPC64, this is always a 64-bit comparison. This implementation is derived from the implementation in the ARM backend; there are some differences because PPC condition registers are allocatable virtual registers (although the record forms always use a specific one), and we look for a matching subtraction instruction after the compare (but before the first use) in addition to before it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179802 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18Make the TargetIndependent flag have the right boolean value.Bill Wendling2-4/+4
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179798 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18X86: Add an SSE2 lowering for 64 bit compares when pcmpgtq (SSE4.2) isn't ↵Benjamin Kramer1-15/+40
available. This pattern started popping up in vectorized min/max reductions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179797 91177308-0d34-0410-b5e6-96231b3b80d8