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2013-04-19[mips] First patch which adds support for micromips.Akira Hatanaka5-35/+190
This patch adds support for recoded (meaning assembly-language compatible to standard mips32) arithmetic 32-bit instructions. Patch by Zoran Jovanovic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179873 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19[mips] Fix InstAlias of XOR and OR macros. Set EmitAlias flag and changeAkira Hatanaka1-2/+2
operand type to uimm16. Patch by Vladimir Medic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179872 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19[ms-inline asm] Refactor the parsing of identifiers. No functional changeChad Rosier1-39/+33
indended. Part of rdar://13663589 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179871 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19[ms-inline asm] Remove these asserts. C++ variables that use namespaceChad Rosier1-2/+0
qualifiers don't necessarily begin with an identifier (e.g., ::foo::bar). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179867 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19[ms-inline asm] Move this variable into the scope in which it is used.Chad Rosier1-1/+1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179866 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19[ms-inline asm] Make this a hard error.Chad Rosier1-4/+4
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179865 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19ConstantFolding: ComputeMaskedBits wants the scalar size for vectors.Benjamin Kramer1-1/+1
Fixes PR15791. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179859 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19[ms-inline asm] Cleanup the dot operator implementation.Chad Rosier1-29/+15
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179856 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19ARM: Permit "sp" in ARM variant of STREXD instructionsTim Northover1-1/+1
Patch from Mihail Popa git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179854 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19refactor the struct byte swapping to a helper function.Rafael Espindola1-70/+20
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179851 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19Attributes: Don't print trailing whitespace on the function attribute comment.Benjamin Kramer1-5/+4
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179849 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19Don't read one command past the end.Rafael Espindola1-2/+6
Thanks to Evgeniy Stepanov for reporting this. It might be a good idea to add a command iterator abstraction to MachO.h, but this fixes the bug for now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179848 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19ARM: permit "sp" in ARM variants of MOVW/MOVT instructionsTim Northover1-2/+3
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179847 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19Revert "PR14606: debug info imported_module support"Eric Christopher4-73/+6
This reverts commit r179836 as it seems to have caused test failures. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179840 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19PR14606: debug info imported_module supportDavid Blaikie4-6/+73
Adding another CU-wide list, in this case of imported_modules (since they should be relatively rare, it seemed better to add a list where each element had a "context" value, rather than add a (usually empty) list to every scope). This takes care of DW_TAG_imported_module, but to fully address PR14606 we'll need to expand this to cover DW_TAG_imported_declaration too. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179836 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19Use 'array_lengthof' as possible to avoid magic numbersMichael Liao1-23/+32
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179833 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19R600: Add pattern for the BFI_INT instructionTom Stellard3-0/+24
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179830 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19R600/SI: Use InstFlag for VOP3 modifier operandsTom Stellard2-15/+14
InstFlag has a default value of 0 and will simplify the VOP3 patterns. Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179829 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19Keep coding stanard. Don't use "else if" after "return".Jakub Staszak1-3/+4
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179826 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19Add some more stats for fast isel vs. SelectionDAG, w.r.t lowering functionEli Bendersky1-1/+10
arguments in entry BBs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179824 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-19Use an enum instead of magic constants to improve readability.Bill Wendling2-16/+44
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179820 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18Implement a better fix for PR15185.Bill Wendling1-6/+11
If the return type is a pointer and the call returns an integer, then do the inttoptr convertions. And vice versa. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179817 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18Relax this assert. It may not hold in all cases.Bill Wendling1-1/+1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179814 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18[ms-inline asm] Apply the condition code mnemonic aliases to both the Intel andChad Rosier1-1/+1
AT&T dialect. Test case for r179804 as well. rdar://13674398 and PR13340. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179813 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18Assert if we're trying to generate a null compact unwind entry.Bill Wendling1-4/+2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179809 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18Set the compact unwind encoding to 'requires EH DWARF' if we cannot generate ↵Bill Wendling1-9/+9
a CU encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179808 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18Disable PPC comparison optimization by defaultHal Finkel1-0/+6
This seems to cause a stage-2 LLVM compile failure (by crashing TableGen); do I'm disabling this for now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179807 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18[asm parser] Add support for predicating MnemonicAlias based on the assemblerChad Rosier3-67/+74
variant/dialect. Addresses a FIXME in the emitMnemonicAliases function. Use and test case to come shortly. rdar://13688439 and part of PR13340. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179804 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18Implement optimizeCompareInstr for PPCHal Finkel2-0/+312
Many PPC instructions have a so-called 'record form' which stores to a specific condition register the result of comparing the result of the instruction with zero (always as a signed comparison). For integer operations on PPC64, this is always a 64-bit comparison. This implementation is derived from the implementation in the ARM backend; there are some differences because PPC condition registers are allocatable virtual registers (although the record forms always use a specific one), and we look for a matching subtraction instruction after the compare (but before the first use) in addition to before it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179802 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18Make the TargetIndependent flag have the right boolean value.Bill Wendling2-4/+4
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179798 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18X86: Add an SSE2 lowering for 64 bit compares when pcmpgtq (SSE4.2) isn't ↵Benjamin Kramer1-15/+40
available. This pattern started popping up in vectorized min/max reductions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179797 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18Cleanup patch:Bill Wendling2-59/+59
Semantics of parameters named Index and Idx were inconsistent between "include/llvm/IR/Attributes.h", "lib/IR/AttributeImpl.h" and "lib/IR/Attributes.cpp": sometimes these were fixed 1-based indexes of IR parameters (or AttributeSet::ReturnIndex for IR return values or AttributeSet::FunctionIndex for IR functions), other times they were the internal slot for storage in the underlying AttributeSetImpl. I renamed usage of the former to "Index" and usage of the latter to "Slot" ("Slot" was already being used consistently for the latter in a subset of cases) Patch by Stephen Lin! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179791 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18This patch addresses two cleanup issues:Bill Wendling2-108/+71
1. Verify::VerifyParameterAttrs in "lib/IR/Verifier.cpp" and AttrBuilder::removeFunctionOnlyAttrs in "lib/IR/Attributes.cpp" (only called by Verify::VerifyFunctionAttrs) separately maintained a list of function-only attribute types. I've consolidated the logic into a new function used for both cases in "lib/IR/Verifier.cpp", so this logic is in one place (other than the AsmParser front-end) 2. Various functions in "lib/IR/Verifier.cpp" passed AttributeSet around by reference needlessly, as it's just a handle to an immutable pimpl body. Patch by Stephen Lin! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179790 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18Fix a -Wdocumentation warningDmitri Gribenko1-1/+1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179789 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18In the function InstCombiner::visitExtractElementInst() removed the ↵Anat Shemer1-4/+4
limitation that extract is promoted over a cast only if the cast has only one use. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179786 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18C API: Fix coding styleTom Stellard1-1/+1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179785 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18Added a function scalarizePHI() that sclarizes a vector phi instruction if ↵Anat Shemer2-0/+78
it has only 2 uses: one to promote the vector phi in a loop and the other use is an extract operation of one element at a constant location. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179783 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18Fix comment. Patch by Stephen Lin.Bill Wendling1-2/+3
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179780 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18At Jim Grosbach's request detemplate Object/MachO.h.Rafael Espindola1-82/+1379
We are still able to handle mixed endian objects by swapping one struct at a time. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179778 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18Fix a comment, PR15777.Chris Lattner1-2/+2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179775 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18Allow misaligned stores in x86 fast-isel.Derek Schuff1-5/+0
In X86FastISel::X86SelectStore(), improperly aligned stores are rejected and handled by the DAG-based ISel. However, X86FastISel::X86SelectLoad() makes no such requirement. There doesn't appear to be an x86 architectural correctness issue with allowing potentially unaligned store instructions. This patch removes this restriction. Patch by Jim Stichnot. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179774 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18LoopVectorizer: Recognize min/max reductionsArnold Schwaighofer1-34/+209
A min/max operation is represented by a select(cmp(lt/le/gt/ge, X, Y), X, Y) sequence in LLVM. If we see such a sequence we can treat it just as any other commutative binary instruction and reduce it. This appears to help bzip2 by about 1.5% on an imac12,2. radar://12960601 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179773 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18[ms-inline asm] Simplify some logic and add a FIXME for unhandled unary minus.Chad Rosier1-10/+13
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179765 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18Make this private method.Chad Rosier1-4/+4
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179764 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18LoopVectorize: Use a set to avoid longer cycles in the reduction chain too.Benjamin Kramer1-8/+6
Fixes PR15748. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179757 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18Fix for PR14824, An ARM Load/Store Optimization bugHao Liu1-1/+17
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179751 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18Revert "Combine bit test + conditional or into simple math"David Majnemer1-61/+0
It is causing stage2 builds to fail, let's get them running again. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179750 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18Combine bit test + conditional or into simple mathDavid Majnemer1-0/+61
Simplify: (select (icmp eq (and X, C1), 0), Y, (or Y, C2)) Into: (or (shl (and X, C1), C3), y) Where: C3 = Log(C2) - Log(C1) If: C1 and C2 are both powers of two git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179748 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18[objc-arc] Do not mismatch up retains inside a for loop with releases ↵Michael Gottesman1-96/+131
outside said for loop in the presense of differing provenance caused by escaping blocks. This occurs due to an alloca representing a separate ownership from the original pointer. Thus consider the following pseudo-IR: objc_retain(%a) for (...) { objc_retain(%a) %block <- %a F(%block) objc_release(%block) } objc_release(%a) From the perspective of the optimizer, the %block is a separate provenance from the original %a. Thus the optimizer pairs up the inner retain for %a and the outer release from %a, resulting in segfaults. This is fixed by noting that the signature of a mismatch of retain/releases inside the for loop is a Use/CanRelease top down with an None bottom up (since bottom up the Retain-CanRelease-Use-Release sequence is completed by the inner objc_retain, but top down due to the differing provenance from the objc_release said sequence is not completed). In said case in CheckForCFGHazards, we now clear the state of %a implying that no pairing will occur. Additionally a test case is included. rdar://12969722 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179747 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-18Removed trailing whitespace.Michael Gottesman1-3/+3
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179746 91177308-0d34-0410-b5e6-96231b3b80d8
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