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2012-09-25AMDGPU: Fix register encodingtstellar3-12/+6
2012-09-24R600: support for interpolation intrinsicststellar9-1/+307
2012-09-24R600: Handle loads from the constants address space.tstellar2-0/+10
2012-09-24R600: Expand vector fadd and fmul on R600tstellar1-0/+3
2012-09-24R600: Add support for v4f32 stores on R600tstellar3-9/+27
2012-09-24R600: Add optimization for FP_ROUNDtstellar2-0/+27
2012-09-24R600: Add support for i8 reads on R600tstellar3-0/+25
2012-09-24R600: Replace AMDGPU pow intrinsic with the llvm versiontstellar3-1/+4
2012-09-24Enable the new SROA pass by default.tstellar1-1/+1
2012-09-24Address one of the original FIXMEs for the new SROA pass by implementingtstellar1-1/+118
2012-09-24Emit dtors into proper section while compiling in vcpp-compatible mode.tstellar1-6/+14
2012-09-24Switch to a signed representation for the dynamic offsets while walkingtstellar1-26/+75
2012-09-24Don't do actual work inside an assert statement. Fixes PR11760!tstellar1-4/+6
2012-09-24Add LLVM_OVERRIDE to methods that override their base classes.tstellar6-21/+26
2012-09-24ARMInstPrinter.cpp: Fix a warning in -Asserts. [-Wunused-variable]tstellar1-0/+2
2012-09-24Whitespace.tstellar1-2/+2
2012-09-24Fix edge cases of ARM shift operands in arith instructions.tstellar1-38/+6
2012-09-24Fix the handling of edge cases in ARM shifted operands.tstellar4-8/+35
2012-09-24Fix 16-bit atomic inst encoding and keep pseudo-inst starting with '#'tstellar1-14/+14
2012-09-24Fix typo in r164357tstellar1-1/+1
2012-09-24MIPS DSP: Add immediate leaves.tstellar1-0/+20
2012-09-24MIPS DSP: Add predicates and instruction template.tstellar1-0/+25
2012-09-24Add MIPS DSP register classes. Set actions of DSP vector operations and overridetstellar2-0/+49
2012-09-24SelectionDAG node enums for MIPS DSP nodes.tstellar2-0/+55
2012-09-24Add MIPS accumulator and DSP control registers.tstellar2-1/+45
2012-09-24Add flags and feature bits for mips dsp.tstellar2-0/+9
2012-09-24Fix a case where the new SROA pass failed to zap dead operands totstellar1-0/+4
2012-09-24Add an --enable-backtraces option to configure to determinetstellar1-1/+1
2012-09-24[ms-inline asm] Expose the mnemonicIsValid() function in the AsmParser.tstellar4-0/+16
2012-09-24Have the DbgVariable "isArtificial" and "isObjectPointer" nottstellar2-5/+5
2012-09-24Add comment.tstellar1-1/+2
2012-09-24Add comment.tstellar1-1/+2
2012-09-24Fix a significant recent(?) regression. StackSlotColoring no longer did anythingtstellar4-3/+10
2012-09-24LoopIdiom: Give up when the loop is not in canonical form.tstellar1-0/+5
2012-09-24[fast-isel] Fallback to SelectionDAG isel if we require strict alignment fortstellar1-0/+6
2012-09-21Some cleanups after merge of Mesa branchtstellar7-468/+7
2012-09-21R600: Emit ISA for ALU instructions in the R600 code emitterMichal Sciubidlo5-148/+249
2012-09-21R600: Add a fdiv pattern.Tom Stellard1-3/+10
2012-09-21R600: reserve also corresponding 128bits regVincent Lejeune1-0/+1
2012-09-21R600: Inital flow control support for SITom Stellard6-2/+167
2012-09-21R600: Move kernel arg lowering into R600TargetLowering classTom Stellard4-7/+35
2012-09-21R600: Match integer add/sub for SI.Michel Dänzer1-2/+8
2012-09-21R600: Complete integer comparison patterns for SI.Michel Dänzer1-4/+12
2012-09-21R600: Match AMDGPUfract on SI.Michel Dänzer1-1/+3
2012-09-21R600: Match int_AMDGPU_floor for SI.Michel Dänzer1-1/+3
2012-09-21R600: Match vector logical operations on SI.Michel Dänzer1-3/+9
2012-09-21R600: Support frint on SIChristian König1-1/+3
2012-09-21R600: Fix lowering of vbuildTom Stellard7-93/+19
2012-09-21R600: Support fmul on SITom Stellard1-1/+4
2012-09-21R600: Fix operand order of V_CNDMASK in custom inserterTom Stellard1-1/+1
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