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2012-10-17R600: Use native operands for MOV_IMM_* instructionsTom Stellard4-23/+42
2012-10-17R600: Use native operands for the MOV InstructionTom Stellard4-45/+57
2012-10-17R600: Use native operands for R600_1OP instructionsTom Stellard8-128/+444
2012-10-17R600: Emit CONTINUE instructions correctlyTom Stellard1-3/+2
2012-10-17AMDGPU: Remove unused llvm.AMDGPU.ssg intrinsicTom Stellard2-8/+0
2012-10-16AMDGPU: Fix build after mergetstellar1-8/+0
2012-10-16Merge master branchtstellar178-2215/+7401
2012-10-15R600: use ceil intrinsic instead of llvm.AMDIL.round.posinftstellar2-4/+0
2012-10-15R600: use floor intrinsic instead of llvm.AMDIL.floortstellar4-3/+3
2012-10-15R600: use llvm fabs intrinsictstellar2-3/+1
2012-10-15R600: use llvm intrinsic for flog2tstellar3-3/+2
2012-10-15R600: add support for cos/sin intrinsictstellar2-8/+11
2012-10-15R600: add a pattern for fsqrttstellar1-0/+3
2012-10-15R600: Store channel index in the register's HWEncoding fieldtstellar8-1117/+31
2012-10-11AMDGPU: Fix lowering of UREMtstellar1-5/+4
2012-10-11AMDGPU: Fix build after merging of DataLayout changeststellar3-5/+5
2012-10-11Merge master branchtstellar331-3805/+5400
2012-10-10R600: Fix typo in SETGE_UINT patterntstellar1-1/+1
2012-10-09R600: Disable SI flow control again for nowtstellar1-1/+2
2012-10-09R600: Handle reversed true/false values in selectcctstellar1-6/+8
2012-10-09R600: Prefer lowering SELECT_CC to CND* instructions over SET* instructionststellar1-42/+50
2012-10-09R600: Fix lowering of fcmptstellar1-7/+12
2012-10-09R600: Add a pattern for: (selectcc i32, -1, i32, i32, SETGT)tstellar1-0/+7
2012-10-09R600: Add a comment explaining why we use TRUNC before FLT_TO_*INTtstellar1-0/+10
2012-10-03SI: Mark the V_CMPX* instructions as having side effectststellar1-0/+32
2012-10-03R600: Handle more vector arithmetic instructionststellar1-0/+8
2012-10-03R600: Implement getSetCCResultType in R600TargetLowering clasststellar2-0/+8
2012-10-03R600: Add support for v4i32 global storeststellar1-0/+6
2012-10-03SI: Fix crash in unused register search in LowerFlowControl pasststellar1-4/+4
2012-10-03SI: S_WAITCNT has side effectststellar1-0/+2
2012-10-03SI: Set the section in the Asm Printer before emitting program infotstellar1-1/+1
2012-10-03SI: Fix bug in loops where iterators may be deletedtstellar2-2/+4
2012-10-02Merge master branchtstellar12-42/+73
2012-10-02R600: improve select_cc lowering to generate CND* more oftentstellar3-42/+88
2012-10-02R600: Fix instruction encoding for r600 family GPUststellar3-15/+15
2012-10-02Merge master branchtstellar128-1000/+6792
2012-10-02Merge TOTtstellar16-150/+327
2012-09-25R600: Fix typo in R600RegisterInfo.tdtstellar1-1/+1
2012-09-25AMDGPU: Fix register encodingtstellar3-12/+6
2012-09-24R600: support for interpolation intrinsicststellar9-1/+307
2012-09-24R600: Handle loads from the constants address space.tstellar2-0/+10
2012-09-24R600: Expand vector fadd and fmul on R600tstellar1-0/+3
2012-09-24R600: Add support for v4f32 stores on R600tstellar3-9/+27
2012-09-24R600: Add optimization for FP_ROUNDtstellar2-0/+27
2012-09-24R600: Add support for i8 reads on R600tstellar3-0/+25
2012-09-24R600: Replace AMDGPU pow intrinsic with the llvm versiontstellar3-1/+4
2012-09-24Enable the new SROA pass by default.tstellar1-1/+1
2012-09-24Address one of the original FIXMEs for the new SROA pass by implementingtstellar1-1/+118
2012-09-24Emit dtors into proper section while compiling in vcpp-compatible mode.tstellar1-6/+14
2012-09-24Switch to a signed representation for the dynamic offsets while walkingtstellar1-26/+75
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