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2005-04-20Remove trailing whitespace, patch by Markus Oberhumer.Misha Brukman3-115/+115
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21379 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-19Add completely untested support for mtcrf/mfcrf encodingChris Lattner1-0/+7
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21353 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-19switch over the rest of the formats that use RC to use isDOTChris Lattner2-71/+73
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21352 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-19Convert the XForm instrs and XSForm instruction over to use isDOTChris Lattner2-52/+60
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21351 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-19Now that the ppc64 and vmx operands of I are always 0, forward substituteChris Lattner1-36/+30
them away. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21350 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-19convert over bform and iform instructionsChris Lattner2-17/+17
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21349 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-19Convert over DForm and DSForm instructionsChris Lattner2-90/+80
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21348 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-19Convert XLForm and XForm instructions over to use PPC64 when appropriate.Chris Lattner2-129/+112
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21347 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-19Convert XO XS and XFX forms to use isPPC64Chris Lattner2-53/+52
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21346 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-19Turn PPC64 and VMX into classes that can be added to instructions instead ofChris Lattner2-39/+40
bits that must be passed up the inheritance hierarchy. Convert MForm and AForm instructions over git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21345 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-18Next round of PPC CR optimizations. For the following code:Nate Begeman1-62/+95
int %bar(float %a, float %b, float %c, float %d) { entry: %tmp.1 = setlt float %a, %d %tmp.2 = setlt float %b, %d %or = or bool %tmp.1, %tmp.2 %tmp.3 = setgt float %c, %d %tmp.4 = or bool %or, %tmp.3 %tmp.5 = and bool %tmp.4, true %retval = cast bool %tmp.5 to int ret int %retval } We now emit: _bar: .LBB_bar_0: ; entry fcmpu cr0, f1, f4 fcmpu cr1, f2, f4 cror 0, 0, 4 fcmpu cr1, f3, f4 cror 28, 0, 5 mfcr r2 rlwinm r3, r2, 29, 31, 31 blr Instead of: _bar: .LBB_bar_0: ; entry fcmpu cr7, f1, f4 mfcr r2 rlwinm r2, r2, 29, 31, 31 fcmpu cr7, f2, f4 mfcr r3 rlwinm r3, r3, 29, 31, 31 or r2, r2, r3 fcmpu cr7, f3, f4 mfcr r3 rlwinm r3, r3, 30, 31, 31 or r3, r2, r3 blr git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21321 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-18Change codegen for setcc to read the bit directly out of the conditionNate Begeman3-45/+36
register. Added support in the .td file for the g5-specific variant of cr -> gpr moves that executes faster, but we currently don't generate it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21314 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-18Handle ExternalSymbol operands in the PPC JITChris Lattner1-9/+13
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21312 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-15Make pattern isel default for ppcNate Begeman5-19/+36
Add new ppc beta option related to using condition registers Make pattern isel control flag (-enable-pattern-isel) global and tristate 0 == off 1 == on 2 == target default git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21309 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-14fix callsAndrew Lenharth2-1/+2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21303 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-14a 21264 fix, and fix the operator precidence on an and -> zap check (should ↵Andrew Lenharth2-3/+11
fix hundreds of test cases git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21302 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-14print negative 64 bit immediates as negative numbers, makes things a littleDuraid Madina2-2/+9
easier on the eyes, not that numbers like 18446744073709541376 are bad or anything git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21300 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-14oops, this stopped us turning movl r4=0xFFFFFFFF;; and rX, r4 into zxt4Duraid Madina1-1/+1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21299 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-14Implement multi-way branches through logical ops on condition registers.Nate Begeman2-3/+69
This can generate considerably shorter code, reducing the size of crafty by almost 1%. Also fix the printing of mcrf. The code is currently disabled until it gets a bit more testing, but should work as-is. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21298 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-14we have zextloads, not sextloads!Duraid Madina1-1/+1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21296 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-14Add the necessary support to codegen condition register logical ops withNate Begeman4-17/+72
register allocated condition registers. Make sure that the printed output is gas compatible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21295 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-13Start allocating condition registers. Almost all explicit uses of CR0 areNate Begeman1-23/+26
now gone. Next step is to get rid of the remaining ones and then start allocating bools to CRs where appropriate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21294 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-13Implement the fold shift X, zext(Y) -> shift X, Y at the target level,Nate Begeman1-6/+22
where it is safe to do so. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21293 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-13Disbale the broken fold of shift + sz[ext] for nowNate Begeman1-19/+0
Move the transform for select (a < 0) ? b : 0 into the dag from ppc isel Enable the dag to fold and (setcc, 1) -> setcc for targets where setcc always produces zero or one. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21291 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-13WOW, function calls still seem to work after this.Andrew Lenharth3-19/+30
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21286 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-13prepare for func call optimizationAndrew Lenharth1-1/+1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21285 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-13* add the shladd instructionDuraid Madina2-0/+23
* fold left shifts of 1, 2, 3 or 4 bits into adds This doesn't save much now, but should get a serious workout once multiplies by constants get converted to shift/add/sub sequences. Hold on! :) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21282 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-13add matches for SxADDL and company, as well as simplify the SxADDQ codeAndrew Lenharth1-78/+48
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21281 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-13* if ANDing with a constant of the form:Duraid Madina1-2/+45
0x00000..00FFF..FF ^ ^ ^ ^ any number of 0's followed by some number of 1's then we use dep.z to just paste zeros over the input. For the special cases where this is zxt1/zxt2/zxt4, we use those instructions instead, because we're all about readability!!! that's what it's about!! readability! *twitch* ;D git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21279 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-13added all flavors of zap for andingAndrew Lenharth1-0/+20
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21276 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-13Fix some mysteriously missing {}'s which cause the miscompilation ofChris Lattner1-2/+2
Olden/mst, Ptrdist/bc, Obsequi, etc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21274 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-13remove one more occurance of this that snuck inChris Lattner1-1/+1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21271 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-13Remove support for ZERO_EXTEND_INREG. This pessimizes code, genering stuffChris Lattner1-21/+0
like this: ldah $1,1($31) lda $1,-1($1) and $0,$1,$24 instead of this: zap $0,252,$24 To get this back, the selector should recognize the ISD::AND case where this happens and emit the appropriate ZAP instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21270 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-13Remove special handling of ZERO_EXTEND_INREG. This pessimizes code, causingChris Lattner1-17/+0
things like this: mov r9 = 65535;; and r8 = r8, r9;; To be emitted instead of: zxt2 r8 = r8;; To get this back, the selector for ISD::AND should recognize this case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21269 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-13Elimate handling of ZERO_EXTEND_INREG. This causes the PPC backend to emitChris Lattner2-25/+0
andi instructions instead of rlwinm instructions for zero extend, but they seem like they would take the same time. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21268 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-13Z_E_I is goneChris Lattner1-2/+0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21267 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-12Fold shift by size larger than type size to undefNate Begeman1-1/+0
Make llvm undef values generate ISD::UNDEF nodes git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21261 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-12Implement setcc op, -1 sequencesNate Begeman1-22/+41
Remove dead setcc op, 0 sequences Coming later: generalization of op, imm git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21260 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-12* OK, after changing to use liveIn/liveOut instead of IDEFs,Duraid Madina2-5/+18
to avoid redundant mov out3=r44 type instructions, we need to tell the register allocator the truth about out? registers. FIXME: unfortunately, since the list of allocatable registers is immutable, we can't simply 'delete r127' from the allocation order, say, if 'out0' is used. The only correct thing we can do is have a linear order of regs: out7, out6 ... out2, out1, out0, r32, r33, r34 ... r126, r127 and slide a 'window' of 96 registers along this line, depending on how many of the out? regs a function actually uses. The only downside of this is that the out? registers will be allocated _first_, which makes the resulting assembly ugly. :( Note this in the README. Hope this gets fixed soon. :) (note the 3rd person speech there) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21252 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-12Get rid of idefs for arguments (oops)Andrew Lenharth1-5/+5
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21251 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-12Get rid of idefs for argumentsAndrew Lenharth1-5/+28
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21250 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-12Put out* into the allocation order, allowing the register allocator toChris Lattner1-4/+3
coallesce moves into outgoing args. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21249 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-12Make sure to realize that calls use their argument regsChris Lattner1-0/+1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21248 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-12stop emitting IDEFs for args - change to using liveIn/liveOutDuraid Madina2-4/+31
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21247 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-12Initial support for allocation condition registersNate Begeman5-13/+67
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21246 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-12Implement bitfield clearsNate Begeman2-11/+35
Implement divide by negative power of two git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21240 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-11Update PPC readme. Remove things that are done or aren't ppc specificNate Begeman1-6/+2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21232 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-11IA64 supports this operation.Chris Lattner1-1/+0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21228 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-11ORo sets CR0Chris Lattner1-0/+1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21227 91177308-0d34-0410-b5e6-96231b3b80d8
2005-04-11Revert the previous patch, which I didn't mean to check in.Chris Lattner2-37/+26
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21226 91177308-0d34-0410-b5e6-96231b3b80d8
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