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2013-06-04R600: Fix the fetch limits for R600 generation GPUsr600-gen-fixesTom Stellard4-27/+30
https://bugs.freedesktop.org/show_bug.cgi?id=64257
2013-06-04R600: Move Subtarget feature definitions into AMDGPU.tdTom Stellard2-64/+66
This is the convention used by the other targets.
2013-06-04R600: Remove unnecessary includeTom Stellard3-2/+4
2013-06-05R600: Make sure to schedule AR register uses and defs in the same clauseTom Stellard3-4/+40
Reviewed-by: vljn at ovi.com
2013-06-05Revert "R600: Add a pass that merge Vector Register"Rafael Espindola4-370/+0
This reverts commit r183279. CodeGen/R600/texture-input-merge.ll was failing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183286 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-05Handle relocations that don't point to symbols.Rafael Espindola2-11/+10
In ELF (as in MachO), not all relocations point to symbols. Represent this properly by using a symbol_iterator instead of a SymbolRef. Update llvm-readobj ELF's dumper to handle relocatios without symbols. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183284 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04R600: Add a pass that merge Vector RegisterVincent Lejeune4-0/+370
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183279 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04R600: Const/Neg/Abs can be folded to dot4Vincent Lejeune5-47/+186
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183278 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04Cortex-R5 can issue Thumb2 integer division instructions.Evan Cheng1-1/+2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183275 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04Revert series of sched model patches until I figure out what is going on.Arnold Schwaighofer8-1277/+207
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183273 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04ARM sched model: Add VFP div instruction on SwiftArnold Schwaighofer1-0/+16
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183271 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04ARM sched model: Add SIMD/VFP load/store instructions on SwiftArnold Schwaighofer1-0/+364
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183270 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04ARM sched model: Add integer VFP/SIMD instructions on SwiftArnold Schwaighofer1-0/+120
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183269 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04ARM sched model: Add integer load/store instructions on SwiftArnold Schwaighofer1-0/+209
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183268 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04ARM sched model: Add integer arithmetic instructions on SwiftArnold Schwaighofer1-0/+155
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183267 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04ARM sched model: Cortex A9 - More InstRW sched resourcesArnold Schwaighofer1-4/+45
Add more InstRW mappings. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183266 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04ARM sched model: Add branch thumb instructionsArnold Schwaighofer1-18/+21
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183265 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04ARM sched model: Add branch thumb2 instructionsArnold Schwaighofer1-11/+15
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183264 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04ARM sched model: Add branch instructionsArnold Schwaighofer1-27/+35
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183263 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04ARM sched model: Add preload thumb2 instructionsArnold Schwaighofer1-3/+6
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183262 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04ARM sched model: Add preload instructionsArnold Schwaighofer1-2/+4
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183261 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04ARM sched model: Add more ALU and CMP thumb instructionsArnold Schwaighofer1-46/+61
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183260 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04 ARM sched model: Add more ALU and CMP thumb2 instructionsArnold Schwaighofer1-52/+86
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183259 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04ARM sched model: Add more ALU and CMP instructionsArnold Schwaighofer1-37/+49
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183258 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04ARM sched model: Add divsion, loads, branches, vfp cvtArnold Schwaighofer4-7/+89
Add some generic SchedWrites and assign resources for Swift and Cortex A9. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183257 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04ARMInstrInfo: Improve isSwiftFastImmShiftArnold Schwaighofer1-0/+2
An instruction with less than 3 inputs is trivially a fast immediate shift. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183256 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04Sparc: No functionality change. Cleanup whitespaces, comment formatting etc.,Venkatraman Govindaraju19-154/+157
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183243 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04ARM: Fix crash in ARM backend inside of ARMConstantIslandPassDavid Majnemer1-0/+1
The ARM backend did not expect LDRBi12 to hold a constant pool operand. Allow for LLVM to deal with the instruction similar to how it deals with LDRi12. This fixes PR16215. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183238 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04R600: Swizzle texture/export instructionsVincent Lejeune2-20/+126
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183229 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04Test commit for user vmedic, to verify commit access. One line of comment is ↵Vladimir Medic1-1/+1
added to MipsAsmParser.cpp. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183215 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04Silencing an MSVC warning about mixing bool and unsigned int.Aaron Ballman1-1/+1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183176 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-03R600/SI: Add support for work item and work group intrinsicsTom Stellard3-15/+88
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183138 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-03R600/SI: Add a calling convention for compute shadersTom Stellard3-9/+39
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183137 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-03R600/SI: Custom lower i64 sign_extendTom Stellard2-0/+19
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183136 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-03R600/SI: Adjust some instructions' out register class after ISelTom Stellard2-0/+52
This is necessary to avoid generating VGPR to SGPR copies in some cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183135 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-03R600/SI: Handle REG_SEQUENCE in fitsRegClass()Tom Stellard1-3/+13
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183134 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-03R600/SI: Handle nodes with glue results correctly ↵Tom Stellard1-0/+16
SITargetLowering::foldOperands() git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183133 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-03R600/SI: Fixup CopyToReg register class in PostprocessISelDAG()Tom Stellard1-5/+33
The CopyToReg nodes will sometimes try to copy a value from a VGPR to an SGPR. This kind of copy is not possible, so we need to detect VGPR->SGPR copies and do something else. The current strategy is to replace these copies with VGPR->VGPR copies and hope that all the users of CopyToReg can accept VGPRs as arguments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183132 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-03R600/SI: Add support for global loadsTom Stellard3-4/+39
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183131 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-03R600/SI: Rework MUBUF store instructionsTom Stellard5-42/+71
The lowering of stores is now mostly handled in the tablegen files. No more BUFFER_STORE nodes I generated during legalization. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183130 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-03R600: 3 op instructions have no write bit but the result are store in PVVincent Lejeune1-3/+1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183111 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-03R600: CALL_FS consumes a stack size entryVincent Lejeune1-0/+1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183108 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-03R600: use capital letter for PV channelVincent Lejeune1-4/+4
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183107 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-03R600: Constraints input regs of interp_xy,_zwVincent Lejeune2-11/+15
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183106 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-03X86: sub_xmm registers are 128 bits wide.Ahmed Bougacha1-1/+1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183103 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-03Sparc: Add support for indirect branch and blockaddress in Sparc backend.Venkatraman Govindaraju4-0/+37
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183094 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-03Sparc: When storing 0, use %g0 directly in the store instruction instead ofVenkatraman Govindaraju2-0/+8
using two instructions (sethi and store). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183090 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-02Sparc: Combine add/or/sethi instruction with restore if possible.Venkatraman Govindaraju1-22/+177
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183088 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-02Sparc: Perform leaf procedure optimization by defaultVenkatraman Govindaraju1-1/+1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183083 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-01Sparc: Mark functions calling llvm.vastart and llvm.returnaddress intrinsics ↵Venkatraman Govindaraju1-0/+6
as non-leaf functions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183079 91177308-0d34-0410-b5e6-96231b3b80d8
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