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AgeCommit message (Expand)AuthorFilesLines
2013-06-04R600: Fix the fetch limits for R600 generation GPUsr600-gen-fixesTom Stellard4-27/+30
2013-06-04R600: Move Subtarget feature definitions into AMDGPU.tdTom Stellard2-64/+66
2013-06-04R600: Remove unnecessary includeTom Stellard3-2/+4
2013-06-05R600: Make sure to schedule AR register uses and defs in the same clauseTom Stellard3-4/+40
2013-06-05Revert "R600: Add a pass that merge Vector Register"Rafael Espindola4-370/+0
2013-06-05Handle relocations that don't point to symbols.Rafael Espindola2-11/+10
2013-06-04R600: Add a pass that merge Vector RegisterVincent Lejeune4-0/+370
2013-06-04R600: Const/Neg/Abs can be folded to dot4Vincent Lejeune5-47/+186
2013-06-04Cortex-R5 can issue Thumb2 integer division instructions.Evan Cheng1-1/+2
2013-06-04Revert series of sched model patches until I figure out what is going on.Arnold Schwaighofer8-1277/+207
2013-06-04ARM sched model: Add VFP div instruction on SwiftArnold Schwaighofer1-0/+16
2013-06-04ARM sched model: Add SIMD/VFP load/store instructions on SwiftArnold Schwaighofer1-0/+364
2013-06-04ARM sched model: Add integer VFP/SIMD instructions on SwiftArnold Schwaighofer1-0/+120
2013-06-04ARM sched model: Add integer load/store instructions on SwiftArnold Schwaighofer1-0/+209
2013-06-04ARM sched model: Add integer arithmetic instructions on SwiftArnold Schwaighofer1-0/+155
2013-06-04ARM sched model: Cortex A9 - More InstRW sched resourcesArnold Schwaighofer1-4/+45
2013-06-04ARM sched model: Add branch thumb instructionsArnold Schwaighofer1-18/+21
2013-06-04ARM sched model: Add branch thumb2 instructionsArnold Schwaighofer1-11/+15
2013-06-04ARM sched model: Add branch instructionsArnold Schwaighofer1-27/+35
2013-06-04ARM sched model: Add preload thumb2 instructionsArnold Schwaighofer1-3/+6
2013-06-04ARM sched model: Add preload instructionsArnold Schwaighofer1-2/+4
2013-06-04ARM sched model: Add more ALU and CMP thumb instructionsArnold Schwaighofer1-46/+61
2013-06-04 ARM sched model: Add more ALU and CMP thumb2 instructionsArnold Schwaighofer1-52/+86
2013-06-04ARM sched model: Add more ALU and CMP instructionsArnold Schwaighofer1-37/+49
2013-06-04ARM sched model: Add divsion, loads, branches, vfp cvtArnold Schwaighofer4-7/+89
2013-06-04ARMInstrInfo: Improve isSwiftFastImmShiftArnold Schwaighofer1-0/+2
2013-06-04Sparc: No functionality change. Cleanup whitespaces, comment formatting etc.,Venkatraman Govindaraju19-154/+157
2013-06-04ARM: Fix crash in ARM backend inside of ARMConstantIslandPassDavid Majnemer1-0/+1
2013-06-04R600: Swizzle texture/export instructionsVincent Lejeune2-20/+126
2013-06-04Test commit for user vmedic, to verify commit access. One line of comment is ...Vladimir Medic1-1/+1
2013-06-04Silencing an MSVC warning about mixing bool and unsigned int.Aaron Ballman1-1/+1
2013-06-03R600/SI: Add support for work item and work group intrinsicsTom Stellard3-15/+88
2013-06-03R600/SI: Add a calling convention for compute shadersTom Stellard3-9/+39
2013-06-03R600/SI: Custom lower i64 sign_extendTom Stellard2-0/+19
2013-06-03R600/SI: Adjust some instructions' out register class after ISelTom Stellard2-0/+52
2013-06-03R600/SI: Handle REG_SEQUENCE in fitsRegClass()Tom Stellard1-3/+13
2013-06-03R600/SI: Handle nodes with glue results correctly SITargetLowering::foldOpera...Tom Stellard1-0/+16
2013-06-03R600/SI: Fixup CopyToReg register class in PostprocessISelDAG()Tom Stellard1-5/+33
2013-06-03R600/SI: Add support for global loadsTom Stellard3-4/+39
2013-06-03R600/SI: Rework MUBUF store instructionsTom Stellard5-42/+71
2013-06-03R600: 3 op instructions have no write bit but the result are store in PVVincent Lejeune1-3/+1
2013-06-03R600: CALL_FS consumes a stack size entryVincent Lejeune1-0/+1
2013-06-03R600: use capital letter for PV channelVincent Lejeune1-4/+4
2013-06-03R600: Constraints input regs of interp_xy,_zwVincent Lejeune2-11/+15
2013-06-03X86: sub_xmm registers are 128 bits wide.Ahmed Bougacha1-1/+1
2013-06-03Sparc: Add support for indirect branch and blockaddress in Sparc backend.Venkatraman Govindaraju4-0/+37
2013-06-03Sparc: When storing 0, use %g0 directly in the store instruction instead ofVenkatraman Govindaraju2-0/+8
2013-06-02Sparc: Combine add/or/sethi instruction with restore if possible.Venkatraman Govindaraju1-22/+177
2013-06-02Sparc: Perform leaf procedure optimization by defaultVenkatraman Govindaraju1-1/+1
2013-06-01Sparc: Mark functions calling llvm.vastart and llvm.returnaddress intrinsics ...Venkatraman Govindaraju1-0/+6
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