~tstellar/llvm - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2012-09-24	R600: Add support for v4f32 stores on R600	tstellar	3	-9/+27
2012-09-24	R600: Add optimization for FP_ROUND	tstellar	2	-0/+27
2012-09-24	R600: Add support for i8 reads on R600	tstellar	3	-0/+25
2012-09-24	R600: Replace AMDGPU pow intrinsic with the llvm version	tstellar	3	-1/+4
2012-09-24	ARMInstPrinter.cpp: Fix a warning in -Asserts. [-Wunused-variable]	tstellar	1	-0/+2
2012-09-24	Whitespace.	tstellar	1	-2/+2
2012-09-24	Fix edge cases of ARM shift operands in arith instructions.	tstellar	1	-38/+6
2012-09-24	Fix the handling of edge cases in ARM shifted operands.	tstellar	4	-8/+35
2012-09-24	Fix 16-bit atomic inst encoding and keep pseudo-inst starting with '#'	tstellar	1	-14/+14
2012-09-24	Fix typo in r164357	tstellar	1	-1/+1
2012-09-24	MIPS DSP: Add immediate leaves.	tstellar	1	-0/+20
2012-09-24	MIPS DSP: Add predicates and instruction template.	tstellar	1	-0/+25
2012-09-24	Add MIPS DSP register classes. Set actions of DSP vector operations and override	tstellar	2	-0/+49
2012-09-24	SelectionDAG node enums for MIPS DSP nodes.	tstellar	2	-0/+55
2012-09-24	Add MIPS accumulator and DSP control registers.	tstellar	2	-1/+45
2012-09-24	Add flags and feature bits for mips dsp.	tstellar	2	-0/+9
2012-09-24	[ms-inline asm] Expose the mnemonicIsValid() function in the AsmParser.	tstellar	4	-0/+16
2012-09-24	Add comment.	tstellar	1	-1/+2
2012-09-24	Add comment.	tstellar	1	-1/+2
2012-09-24	[fast-isel] Fallback to SelectionDAG isel if we require strict alignment for	tstellar	1	-0/+6
2012-09-21	Some cleanups after merge of Mesa branch	tstellar	7	-468/+7
2012-09-21	R600: Emit ISA for ALU instructions in the R600 code emitter	Michal Sciubidlo	5	-148/+249
2012-09-21	R600: Add a fdiv pattern.	Tom Stellard	1	-3/+10
2012-09-21	R600: reserve also corresponding 128bits reg	Vincent Lejeune	1	-0/+1
2012-09-21	R600: Inital flow control support for SI	Tom Stellard	6	-2/+167
2012-09-21	R600: Move kernel arg lowering into R600TargetLowering class	Tom Stellard	4	-7/+35
2012-09-21	R600: Match integer add/sub for SI.	Michel Dänzer	1	-2/+8
2012-09-21	R600: Complete integer comparison patterns for SI.	Michel Dänzer	1	-4/+12
2012-09-21	R600: Match AMDGPUfract on SI.	Michel Dänzer	1	-1/+3
2012-09-21	R600: Match int_AMDGPU_floor for SI.	Michel Dänzer	1	-1/+3
2012-09-21	R600: Match vector logical operations on SI.	Michel Dänzer	1	-3/+9
2012-09-21	R600: Support frint on SI	Christian König	1	-1/+3
2012-09-21	R600: Fix lowering of vbuild	Tom Stellard	7	-93/+19
2012-09-21	R600: Support fmul on SI	Tom Stellard	1	-1/+4
2012-09-21	R600: Fix operand order of V_CNDMASK in custom inserter	Tom Stellard	1	-1/+1
2012-09-21	R600: Ignore special registers when calculating reg count	Tom Stellard	1	-0/+2
2012-09-21	radeonsi: Handle position input parameter for pixel shaders v2	Tom Stellard	2	-0/+22
2012-09-21	R600: Coding style fixes	Tom Stellard	4	-31/+31
2012-09-21	radeonsi: Move interpolation mode check into the compiler	Tom Stellard	1	-1/+12
2012-09-21	R600: Add SHADER_TYPE instruction	Tom Stellard	8	-1/+32
2012-09-21	R600: Match fexp2 for SI.	Michel Dänzer	1	-1/+3
2012-09-21	AMDGPU: Fix register assembly for SI	Tom Stellard	1	-2/+2
2012-09-21	AMDGPU: Add license to InstPrinter files	Tom Stellard	2	-0/+16
2012-09-21	AMDGPU: Don't print the default predicate state	Tom Stellard	2	-2/+7
2012-09-21	AMDGPU: Fix register names	Tom Stellard	1	-3/+3
2012-09-21	AMDGPU: Use modern tablegen features in *RegisterInfo.td	Tom Stellard	4	-2414/+111
2012-09-21	AMDGPU: Use new OperandWithDefaultOps for DOT* instructions	Tom Stellard	1	-10/+5
2012-09-21	AMDGPU: Updates for new tablegen property inferences	Tom Stellard	7	-19/+72
2012-09-21	AMDGPU: Add core backend files for R600/SI codegen	Tom Stellard	109	-1/+21757
2012-09-21	Fix a typo in r164357	hliao	1	-8/+8