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2014-01-13[SystemZ] Optimize (sext (ashr (shl ...), ...))Richard Sandiford2-0/+36
...into (ashr (shl (anyext X), ...), ...), which requires one fewer instruction. The (anyext X) can sometimes be simplified too. I didn't do this in DAGCombiner because widening shifts isn't a win on all targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199114 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-09[SystemZ] Fix RNSBG bug introduced by r197802Richard Sandiford1-8/+10
The zext handling added in r197802 wasn't right for RNSBG. This patch restricts it to ROSBG, RXSBG and RISBG. (The tests for RISBG were added in r197802 since RISBG was the motivating example.) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198862 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-07Move the llvm mangler to lib/IR.Rafael Espindola2-2/+2
This makes it available to tools that don't link with target (like llvm-ar). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198708 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-07Re-sort all of the includes with ./utils/sort_includes.py so thatChandler Carruth5-5/+4
subsequent changes are easier to review. About to fix some layering issues, and wanted to separate out the necessary churn. Also comment and sink the include of "Windows.h" in three .inc files to match the usage in Memory.inc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198685 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-03Make the llvm mangler depend only on DataLayout.Rafael Espindola1-1/+1
Before this patch any program that wanted to know the final symbol name of a GlobalValue had to link with Target. This patch implements a compromise solution where the mangler uses DataLayout. This way, any tool that already links with Target (llc, clang) gets the exact behavior as before and new IR files can be mangled without linking with Target. With this patch the mangler is constructed with just a DataLayout and DataLayout is extended to include the information the Mangler needs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198438 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-24Fix typo.Richard Sandiford1-1/+1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197986 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-24[SystemZ] Use interlocked-access 1 instructions for CodeGenRichard Sandiford5-69/+118
...namely LOAD AND ADD, LOAD AND AND, LOAD AND OR and LOAD AND EXCLUSIVE OR. LOAD AND ADD LOGICAL isn't really separately useful for LLVM. I'll look at adding reusing the CC results in new year. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197985 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-24[SystemZ] Add MC support for interlocked-access 1 instructionsRichard Sandiford5-3/+41
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197984 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-20[SystemZ] Optimize comparisons with truncated extended loadsRichard Sandiford1-2/+24
If the extension of a loaded value is compared against zero and used in other arithmetic, InstCombine will change the comparison to use the unextended load. It's also possible that the comparison could be against the unextended load from the outset. In DAG form this becomes a truncation of an extending load. We want to strip the truncation if possible so that we can use load-and-test instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197804 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-20[SystemZ] Extend RISBG optimizationRichard Sandiford1-3/+17
The handling of ANY_EXTEND and ZERO_EXTEND was too strict. In this context we can treat ZERO_EXTEND in much the same way as an AND and then also handle outermost ZERO_EXTENDs. I couldn't find a test that benefited from the ANY_EXTEND change, but it's more obvious to write it this way once SIGN_EXTEND and ZERO_EXTEND are handled differently. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197802 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-16On DataLayout, omit the default of p:64:64:64.Rafael Espindola1-1/+1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197397 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-13[SystemZ] Optimize X [!=]= Y in cases where X - Y or Y - X is also computedRichard Sandiford1-0/+21
In those cases it's better to compare the result of the subtraction against zero. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197239 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-13[SystemZ] Make more use of TMHHRichard Sandiford1-25/+53
This originally came about after noticing that InstCombine turns some of the TMHH (icmp (and...), ...) tests into plain comparisons. Since there is no instruction to compare with a 64-bit immediate, TMHH is generally better than an ordered comparison for the cases that it can handle. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197238 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-13[SystemZ] Extend integer absolute selectionRichard Sandiford4-4/+55
This patch makes more use of LPGFR and LNGFR. It builds on top of the LTGFR selection from r197234. Most of the tests are motivated by what InstCombine would produce. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197236 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-13[SystemZ] Add a structure to represent a selected comparisonRichard Sandiford1-175/+180
...in an attempt to rein back the increasingly complex selection code. A knock-on effect is that ICmpType is exposed from the outset, which slightly simplifies adjustSubwordCmp. The code is no piece of art even after this change, but at least it should be slightly better. No behavioral change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197235 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-13[SystemZ] Make more use of LTGFRRichard Sandiford1-0/+31
InstCombine turns (sext (trunc)) into (ashr (shl)), then converts any comparison of the ashr against zero into a comparison of the shl against zero. This makes sense in itself, but we want to undo it for z, since the sign- extension instruction has a CC-setting form. I've included tests for both the original and InstCombined variants, but the former already worked. The patch fixes the latter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197234 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-12Simplify the SystemZ datalayout string.Rafael Espindola1-2/+1
Reviewed by Richard Sandiford. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197170 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-12Use "a" instead of "a0" in DataLayout.Rafael Espindola1-1/+1
It means exactly the same and is just a bit shorter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197169 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-11[SystemZ] Optimize fcmp X, 0 in cases where X is also negatedRichard Sandiford1-4/+30
In such cases it's often better to test the result of the negation instead, since the negation also sets CC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197032 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-11Prune redundant dependencies in LLVMBuild.txt.NAKAMURA Takumi1-1/+1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196988 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-10Add TargetLowering::prepareVolatileOrAtomicLoadRichard Sandiford3-27/+47
One unusual feature of the z architecture is that the result of a previous load can be reused indefinitely for subsequent loads, even if a cache-coherent store to that location is performed by another CPU. A special serializing instruction must be used if you want to force a load to be reattempted. Since volatile loads are not supposed to be omitted in this way, we should insert a serializing instruction before each such load. The same goes for atomic loads. The patch implements this at the IR->DAG boundary, in a similar way to atomic fences. It is a no-op for targets other than SystemZ. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196906 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-10Add TargetLowering::prepareVolatileOrAtomicLoadRichard Sandiford8-3/+39
One unusual feature of the z architecture is that the result of a previous load can be reused indefinitely for subsequent loads, even if a cache-coherent store to that location is performed by another CPU. A special serializing instruction must be used if you want to force a load to be reattempted. Since volatile loads are not supposed to be omitted in this way, we should insert a serializing instruction before each such load. The same goes for atomic loads. The patch implements this at the IR->DAG boundary, in a similar way to atomic fences. It is a no-op for targets other than SystemZ. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196905 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-10Add proper dependencies to LLVMBuild.txt in llvm/lib.NAKAMURA Takumi1-1/+1
I'll prune redundant deps in LLVMBuild.txt, later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196881 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-06[SystemZ] Use LOAD AND TEST for comparisons with -0Richard Sandiford2-5/+8
...since it os equivalent to comparison with +0. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196580 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-06[SystemZ] Extend the use of C(L)GFRRichard Sandiford1-2/+19
instcombine prefers to put extended operands first, so this patch handles that case for C(L)GFR. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196579 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-06[SystemZ] Optimize selects between 0 and -1Richard Sandiford1-14/+44
Since z has no setcc instruction as such, the choice of setBooleanContents is a bit arbitrary. Currently it's set to ZeroOrOneBooleanContent, so we produced a branch-free form when selecting between 0 and 1, but not when selecting between 0 and -1. This patch handles the latter case too. At some point I'd like to measure whether it's better to use conditional moves for constant selects on z196, but that's future work. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196578 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-03[SystemZ] Fix choice of known-zero mask in insertion optimizationRichard Sandiford1-4/+4
The backend converts 64-bit ORs into subreg moves if the upper 32 bits of one operand and the low 32 bits of the other are known to be zero. It then tries to peel away redundant ANDs from the upper 32 bits. Since AND masks are canonicalized to exclude known-zero bits, the test ORs the mask and the known-zero bits together before checking for redundancy. The problem was that it was using the wrong node when checking for known-zero bits, so could drop ANDs that were still needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196267 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-02Refactor the setting of PrivateGlobalPrefix.Rafael Espindola1-1/+0
No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196170 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-02Change the default of AsmWriterClassName and isMCAsmWriter.Rafael Espindola1-10/+0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196065 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-28[CMake] Let add_public_tablegen_target responsible to provide dependency to ↵NAKAMURA Takumi6-12/+0
CommonTableGen. add_public_tablegen_target adds *CommonTableGen to LLVM_COMMON_DEPENDS. LLVM_COMMON_DEPENDS affects add_llvm_library (and other add_target stuff) within its scope. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195927 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-28[CMake] Prune include_directories() in llvm/lib/Target, take #2.NAKAMURA Takumi4-8/+0
I forgot to commit them. They were staging in my local repo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195924 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-27Don't set GlobalPrefix to the default value.Rafael Espindola1-1/+0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195884 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-26[SystemZ] Fix incorrect use of RISBG for a zero-extended right shiftRichard Sandiford1-19/+8
We would wrongly transform the testcase into the equivalent of an AND with 1. The problem was that, when testing whether the shifted-in bits of the right shift were significant, we used the width of the final zero-extended result rather than the width of the shifted value. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195731 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-22[SystemZ] Fix TMHH and TMHL usage for z10 with -O0Richard Sandiford4-20/+34
I've no idea why I decided to handle TMxx differently from all the other high/low logic operations, but it was a stupid thing to do. The high registers aren't available as separate 32-bit registers on z10, so subreg_h32 can't be used on a GR64 there. I've normally been testing with z196 and with -O3 and so hadn't noticed this until now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195473 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-19[weak vtables] Remove a bunch of weak vtablesJuergen Ributzka7-1/+28
This patch removes most of the trivial cases of weak vtables by pinning them to a single object file. The memory leaks in this version have been fixed. Thanks Alexey for pointing them out. Differential Revision: http://llvm-reviews.chandlerc.com/D2068 Reviewed by Andy git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195064 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18Revert r194865 and r194874.Alexey Samsonov7-29/+1
This change is incorrect. If you delete virtual destructor of both a base class and a subclass, then the following code: Base *foo = new Child(); delete foo; will not cause the destructor for members of Child class. As a result, I observe plently of memory leaks. Notable examples I investigated are: ObjectBuffer and ObjectBufferStream, AttributeImpl and StringSAttributeImpl. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194997 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-15[weak vtables] Remove a bunch of weak vtablesJuergen Ributzka7-1/+29
This patch removes most of the trivial cases of weak vtables by pinning them to a single object file. Differential Revision: http://llvm-reviews.chandlerc.com/D2068 Reviewed by Andy git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194865 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-13[SystemZ] Add the general form of BCRRichard Sandiford2-8/+8
At the moment this is just the MC support. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194585 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-06[SystemZ] Handle vectors in getSetCCResultTypeRichard Sandiford2-5/+8
I don't have a standalone testcase for this, but it should allow r193676 to be reapplied. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194148 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-31[SystemZ] Automatically detect zEC12 and z196 hostsRichard Sandiford2-3/+9
As on other hosts, the CPU identification instruction is priveleged, so we need to look through /proc/cpuinfo. I copied the PowerPC way of handling "generic". Several tests were implicitly assuming z10 and so failed on z196. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193742 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-29Add a helper getSymbol to AsmPrinter.Rafael Espindola2-2/+2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193627 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-29The AsmPrinter has a Mangler. Use it.Rafael Espindola3-8/+6
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193617 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-28[SystemZ] Set usaAA to trueRichard Sandiford1-0/+3
useAA significantly improves the handling of vector code that has TBAA information attached. It also helps other cases, as shown by the testsuite changes here. The only real downside I've seen is that it interferes with MergeConsecutiveStores. The problem is that that optimization works top down, starting at the first store in the chain, and looks for cases where the chain result is only used by a single related store. These related stores don't alias, so useAA will have rewritten all the later stores to use a different chain input (typically the same one as the first store). I think the advantages outweigh the disadvantages though, so for now I've just disabled alias analysis for the unaligned-01.ll test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193521 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-16[SystemZ] Handle extensions in RxSBG optimizationsRichard Sandiford1-8/+26
The input to an RxSBG operation can be narrower as long as the upper bits are don't care. This fixes a FIXME added in r192783. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192790 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-16[SystemZ] Improve handling of SETCCRichard Sandiford5-4/+120
We previously used the default expansion to SELECT_CC, which in turn would expand to "LHI; BRC; LHI". In most cases it's better to use an IPM-based sequence instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192784 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-16Add a MCAsmInfoELF class and factor some code into it.Rafael Espindola2-3/+2
We had a MCAsmInfoCOFF, but no common class for all the ELF MCAsmInfos before. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192760 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-15[SystemZ] Use A(G)SI when spilling the target of a constant additionRichard Sandiford1-2/+24
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192681 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-12Add missing #include's to cctype when using isdigit/alpha/etc.Will Dietz1-0/+2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192519 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-08Add a MCTargetStreamer interface.Rafael Espindola1-1/+1
This patch fixes an old FIXME by creating a MCTargetStreamer interface and moving the target specific functions for ARM, Mips and PPC to it. The ARM streamer is still declared in a common place because it is used from lib/CodeGen/ARMException.cpp, but the Mips and PPC are completely hidden in the corresponding Target directories. I will send an email to llvmdev with instructions on how to use this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192181 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-01[SystemZ] Add comparisons of high words and memoryRichard Sandiford3-2/+30
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191777 91177308-0d34-0410-b5e6-96231b3b80d8
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