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path: root/lib/Target/R600
AgeCommit message (Expand)AuthorFilesLines
2013-06-04R600: Fix the fetch limits for R600 generation GPUsr600-gen-fixesTom Stellard4-27/+30
2013-06-04R600: Move Subtarget feature definitions into AMDGPU.tdTom Stellard2-64/+66
2013-06-04R600: Remove unnecessary includeTom Stellard3-2/+4
2013-06-05R600: Make sure to schedule AR register uses and defs in the same clauseTom Stellard3-4/+40
2013-06-05Revert "R600: Add a pass that merge Vector Register"Rafael Espindola4-370/+0
2013-06-04R600: Add a pass that merge Vector RegisterVincent Lejeune4-0/+370
2013-06-04R600: Const/Neg/Abs can be folded to dot4Vincent Lejeune5-47/+186
2013-06-04R600: Swizzle texture/export instructionsVincent Lejeune2-20/+126
2013-06-04Silencing an MSVC warning about mixing bool and unsigned int.Aaron Ballman1-1/+1
2013-06-03R600/SI: Add support for work item and work group intrinsicsTom Stellard3-15/+88
2013-06-03R600/SI: Add a calling convention for compute shadersTom Stellard3-9/+39
2013-06-03R600/SI: Custom lower i64 sign_extendTom Stellard2-0/+19
2013-06-03R600/SI: Adjust some instructions' out register class after ISelTom Stellard2-0/+52
2013-06-03R600/SI: Handle REG_SEQUENCE in fitsRegClass()Tom Stellard1-3/+13
2013-06-03R600/SI: Handle nodes with glue results correctly SITargetLowering::foldOpera...Tom Stellard1-0/+16
2013-06-03R600/SI: Fixup CopyToReg register class in PostprocessISelDAG()Tom Stellard1-5/+33
2013-06-03R600/SI: Add support for global loadsTom Stellard3-4/+39
2013-06-03R600/SI: Rework MUBUF store instructionsTom Stellard5-42/+71
2013-06-03R600: 3 op instructions have no write bit but the result are store in PVVincent Lejeune1-3/+1
2013-06-03R600: CALL_FS consumes a stack size entryVincent Lejeune1-0/+1
2013-06-03R600: use capital letter for PV channelVincent Lejeune1-4/+4
2013-06-03R600: Constraints input regs of interp_xy,_zwVincent Lejeune2-11/+15
2013-05-31Make SubRegIndex size mandatory, following r183020.Ahmed Bougacha1-1/+2
2013-05-29Temporary fix to get rid of gcc warning.Patrik Hagglund1-1/+10
2013-05-25Track IR ordering of SelectionDAG nodes 2/4.Andrew Trick8-45/+44
2013-05-23R600: Fix R600ControlFlowFinalizer not considering VTX_READ 128 bit dst regTom Stellard1-2/+9
2013-05-23Move passes from namespace llvm into anonymous namespaces. Sort includes whil...Benjamin Kramer14-35/+35
2013-05-23R600: Hide symbols of implementation details.Benjamin Kramer4-63/+25
2013-05-23Setting the default value (fixes CRT assertions about uninitialized variable ...Aaron Ballman1-3/+3
2013-05-23Fix 32 bit build in c++11 mode.Rafael Espindola1-1/+1
2013-05-23Fix a leak on the r600 backend.Rafael Espindola2-8/+12
2013-05-23clang-format this file.Rafael Espindola1-29/+25
2013-05-22Fix use after free (pr16103).Rafael Espindola1-7/+22
2013-05-22Check that a function starts with llvm. before using GET_FUNCTION_RECOGNIZER.Rafael Espindola1-0/+3
2013-05-22R600ISelLowering.cpp: Avoid "using namespace Intrinsic;" to appease MSC. Spec...NAKAMURA Takumi1-18/+15
2013-05-22R600: Whitespace and untabify.NAKAMURA Takumi1-2/+2
2013-05-22Create an FPOW SDNode opcode def in the target independent .td file rather th...Owen Anderson1-2/+0
2013-05-22Attempt to fix the mingw32 bot.Rafael Espindola1-4/+4
2013-05-22s/u_int32_t/uint32_t/Rafael Espindola1-2/+2
2013-05-22Fix warning in non-assert build.Rafael Espindola1-0/+2
2013-05-20R600: Fix bug detected by GCC warning.Benjamin Kramer1-2/+2
2013-05-20R600/SI: Use a multiclass for MUBUF_Load_HelperTom Stellard2-20/+30
2013-05-20R600/SI: Add a pattern for S_LOAD_DWORDX2_* instructionsTom Stellard1-0/+1
2013-05-20R600/SI: Add pattern for rotrTom Stellard1-0/+2
2013-05-20R600: Swap the legality of rotl and rotrTom Stellard7-28/+11
2013-05-20R600/SI: Add patterns for 64-bit shift operationsTom Stellard2-3/+22
2013-05-20R600/SI: Use the same names for VOP3 operands and encoding fieldsTom Stellard2-37/+37
2013-05-20R600/SI: Make fitsRegClass() operands constTom Stellard2-2/+3
2013-05-18Add LLVMContext argument to getSetCCResultTypeMatt Arsenault4-11/+11
2013-05-17Fix the build in c++11 mode.Rafael Espindola1-2/+2
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