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AgeCommit message (Expand)AuthorFilesLines
2005-04-19Add completely untested support for mtcrf/mfcrf encodingChris Lattner1-0/+7
2005-04-19switch over the rest of the formats that use RC to use isDOTChris Lattner2-71/+73
2005-04-19Convert the XForm instrs and XSForm instruction over to use isDOTChris Lattner2-52/+60
2005-04-19Now that the ppc64 and vmx operands of I are always 0, forward substituteChris Lattner1-36/+30
2005-04-19convert over bform and iform instructionsChris Lattner2-17/+17
2005-04-19Convert over DForm and DSForm instructionsChris Lattner2-90/+80
2005-04-19Convert XLForm and XForm instructions over to use PPC64 when appropriate.Chris Lattner2-129/+112
2005-04-19Convert XO XS and XFX forms to use isPPC64Chris Lattner2-53/+52
2005-04-19Turn PPC64 and VMX into classes that can be added to instructions instead ofChris Lattner2-39/+40
2005-04-18Next round of PPC CR optimizations. For the following code:Nate Begeman1-62/+95
2005-04-18Change codegen for setcc to read the bit directly out of the conditionNate Begeman3-45/+36
2005-04-18Handle ExternalSymbol operands in the PPC JITChris Lattner1-9/+13
2005-04-15Make pattern isel default for ppcNate Begeman3-11/+24
2005-04-14Implement multi-way branches through logical ops on condition registers.Nate Begeman2-3/+69
2005-04-14Add the necessary support to codegen condition register logical ops withNate Begeman4-17/+72
2005-04-13Start allocating condition registers. Almost all explicit uses of CR0 areNate Begeman1-23/+26
2005-04-13Implement the fold shift X, zext(Y) -> shift X, Y at the target level,Nate Begeman1-6/+22
2005-04-13Disbale the broken fold of shift + sz[ext] for nowNate Begeman1-19/+0
2005-04-13remove one more occurance of this that snuck inChris Lattner1-1/+1
2005-04-13Elimate handling of ZERO_EXTEND_INREG. This causes the PPC backend to emitChris Lattner2-25/+0
2005-04-12Fold shift by size larger than type size to undefNate Begeman1-1/+0
2005-04-12Implement setcc op, -1 sequencesNate Begeman1-22/+41
2005-04-12Initial support for allocation condition registersNate Begeman5-13/+67
2005-04-12Implement bitfield clearsNate Begeman2-11/+35
2005-04-11Update PPC readme. Remove things that are done or aren't ppc specificNate Begeman1-6/+2
2005-04-11ORo sets CR0Chris Lattner1-0/+1
2005-04-11Revert the previous patch, which I didn't mean to check in.Chris Lattner2-37/+26
2005-04-11Fix a minor bug (ORo didn't mark that it set CR0).Chris Lattner2-26/+37
2005-04-11Add recording variants of ISD::AND and ISD::OR. This kills almost 1000Nate Begeman2-10/+48
2005-04-10Fix another fixme: factor out the constant fp generation code.Nate Begeman1-17/+2
2005-04-10Fix 64 bit argument loading that straddles the args in regs / args on stackNate Begeman1-7/+15
2005-04-10Remove unnecessary Implicit Defs. Since r0 is not in allocation, we do notNate Begeman1-4/+0
2005-04-10Make sure that BRCOND branches can be converted into long branches too.Nate Begeman2-2/+4
2005-04-10Don't hand ISD::CALL nodes off to SelectExprFP. This fixes siod.Nate Begeman1-1/+2
2005-04-10rename getPPCOpcodeForSetCCNumber -> getPPCOpcodeForSetCCOpode to be moreChris Lattner1-21/+21
2005-04-09fix ISD::BRCONDTWOWAY codegen to not deference the end() iteratorNate Begeman1-1/+1
2005-04-09Fix CodeGen/Generic/2005-05-09-GlobalInPHI.ll, which was reduced from 254.gap.Chris Lattner1-0/+16
2005-04-09do not set the root to null if an argument is deadChris Lattner1-1/+2
2005-04-09Add rlwnm instruction for variable rotateNate Begeman2-29/+79
2005-04-09Fix a crash on 173.applu by asking for a constant bigger than 32-bits.Chris Lattner1-1/+1
2005-04-09Switch this instruction selector over to using liveins and liveouts, eliminatingChris Lattner1-8/+26
2005-04-09Optimize FSEL a bit for fneg arguments. This fixes the recently added testNate Begeman1-11/+12
2005-04-09This target does not yet support ISD::BRCONDTWOWAYChris Lattner2-0/+2
2005-04-0964b: Expand S/UREMNate Begeman2-7/+31
2005-04-08Fix 64b shiftsNate Begeman1-26/+13
2005-04-08Match Mac OS X 64 bit calling conventionsNate Begeman1-116/+46
2005-04-07Optimized code sequences for setcc reg, 0Nate Begeman1-4/+77
2005-04-07PowerPC zero extends setcc resultsChris Lattner1-0/+1
2005-04-06Pattern match bitfield insert, which helps shift long by immediate, amongNate Begeman1-15/+152
2005-04-06Fix some shift bugsNate Begeman1-3/+12
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