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path: root/lib/Target/AMDGPU/R600RegisterInfo.td
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2012-10-17R600: Use native operands for R600_1OP instructionsTom Stellard1-2/+2
2012-10-15R600: Store channel index in the register's HWEncoding fieldtstellar1-2/+14
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@165965 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-25R600: Fix typo in R600RegisterInfo.tdtstellar1-1/+1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@164603 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-25AMDGPU: Fix register encodingtstellar1-3/+3
The register encodings weren't being defined correctly in the .td files, so they were all encoded as 0. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@164602 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-21AMDGPU: Fix register namesTom Stellard1-3/+3
2012-09-21AMDGPU: Use modern tablegen features in *RegisterInfo.tdTom Stellard1-1171/+41
We no longer need to generate them with perl scripts.
2012-09-21AMDGPU: Add core backend files for R600/SI codegenTom Stellard1-0/+1215
2012-07-16Revert "AMDGPU: Add core backend files for R600/SI codegen v6"Tom Stellard1-5271/+0
This reverts commit 4ea70107c5e51230e9e60f0bf58a0f74aa4885ea. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160303 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16AMDGPU: Add core backend files for R600/SI codegen v6Tom Stellard1-0/+5271
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160270 91177308-0d34-0410-b5e6-96231b3b80d8