index
:
~tstellar/llvm
9.1-abi-fix
Nov13-test
Oct18-backup
assembler
assembler-Jan-06-2015
assembler-push
backup-Oct15
backup-Oct18
bfgminer
bfgminer-perf
cayman-only-bfgminer
clover-elf
clover-elf-v2
hazard-rec
hsa
image-support
indirect-addressing
indirect-wip
indirect-wip-2
indirect-wip-3
indirect-wip-4
indirect-wip-5
kernel-args-WIP
lds
lds-v2
long-alu
madk
master
master-testing
master-testing-patches
master-testing-patches-v2
master-testing-si
master-testing-v2
mi-sched-experimental
native
opencv-Sep18-patches
perf-Dec31-2014
perf-Jan-08-2015
push-jan16
r600
r600-May09
r600-alu-encoding
r600-final-push
r600-gen-fixes
r600-imm-flags
r600-initial-review
r600-initial-review-May11
r600-master
r600-private-mem-fixes
r600-private-memory
r600-review-v10
r600-review-v3
r600-review-v7
r600-review-v8
r600-review-v9
r600-rewrite-pats
r600-structurizer
r600-structurizer-v2
r600-tablegen-hwreg
r600-tablegen-reg-encoding
r600-vliw
remove-fold-operands
sched-fixes
sched-perf-Mar-27-2015
si-compute
si-compute-v3
si-fold
si-lowercase
si-scheduler
si-scheduler-v2
si-scheduler-v3
si-sgpr-copies
si-spill-fixes
si-spill-fixes-v2
si-spill-fixes-v3
si-spill-fixes-v4
smrd-cluster
struct-divergence
struct-divergence-v1
vgpr-spilling-Jan07-2014
vinterp-fix
vliw5-rebase
vlj-bottom-up
Unnamed repository; edit this file 'description' to name the repository.
tstellar
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
lib
/
Target
/
AMDGPU
/
R600Instructions.td
Age
Commit message (
Expand
)
Author
Files
Lines
2012-10-12
XXX: WIP no MIOperandInfo way
backup-Oct15
Tom Stellard
1
-81
/
+230
2012-10-12
R600: use floor intrinsic instead of llvm.AMDIL.floor
Vincent Lejeune
1
-1
/
+1
2012-10-12
R600: use llvm intrinsic for flog2
Vincent Lejeune
1
-1
/
+1
2012-10-12
R600: add support for cos/sin intrinsic
Vincent Lejeune
1
-6
/
+11
2012-10-12
R600: add a pattern for fsqrt
Vincent Lejeune
1
-0
/
+3
2012-10-10
R600: Fix typo in SETGE_UINT pattern
tstellar
1
-1
/
+1
2012-10-09
R600: Add a pattern for: (selectcc i32, -1, i32, i32, SETGT)
tstellar
1
-0
/
+7
2012-10-09
R600: Add a comment explaining why we use TRUNC before FLT_TO_*INT
tstellar
1
-0
/
+10
2012-10-03
R600: Add support for v4i32 global stores
tstellar
1
-0
/
+6
2012-10-02
R600: improve select_cc lowering to generate CND* more often
tstellar
1
-6
/
+32
2012-09-24
R600: support for interpolation intrinsics
tstellar
1
-0
/
+54
2012-09-24
R600: Handle loads from the constants address space.
tstellar
1
-0
/
+9
2012-09-24
R600: Add support for v4f32 stores on R600
tstellar
1
-7
/
+23
2012-09-24
R600: Add support for i8 reads on R600
tstellar
1
-0
/
+16
2012-09-21
Some cleanups after merge of Mesa branch
tstellar
1
-1
/
+1
2012-09-21
R600: Emit ISA for ALU instructions in the R600 code emitter
Michal Sciubidlo
1
-61
/
+119
2012-09-21
R600: Add a fdiv pattern.
Tom Stellard
1
-3
/
+10
2012-09-21
R600: Fix lowering of vbuild
Tom Stellard
1
-10
/
+10
2012-09-21
AMDGPU: Don't print the default predicate state
Tom Stellard
1
-1
/
+1
2012-09-21
AMDGPU: Use new OperandWithDefaultOps for DOT* instructions
Tom Stellard
1
-10
/
+5
2012-09-21
AMDGPU: Updates for new tablegen property inferences
Tom Stellard
1
-4
/
+17
2012-09-21
AMDGPU: Add core backend files for R600/SI codegen
Tom Stellard
1
-0
/
+1266
2012-07-16
Revert "AMDGPU: Add core backend files for R600/SI codegen v6"
Tom Stellard
1
-1322
/
+0
2012-07-16
AMDGPU: Add core backend files for R600/SI codegen v6
Tom Stellard
1
-0
/
+1322