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path: root/lib/Target/AMDGPU/R600Instructions.td
AgeCommit message (Expand)AuthorFilesLines
2012-10-12XXX: WIP no MIOperandInfo waybackup-Oct15Tom Stellard1-81/+230
2012-10-12R600: use floor intrinsic instead of llvm.AMDIL.floorVincent Lejeune1-1/+1
2012-10-12R600: use llvm intrinsic for flog2Vincent Lejeune1-1/+1
2012-10-12R600: add support for cos/sin intrinsicVincent Lejeune1-6/+11
2012-10-12R600: add a pattern for fsqrtVincent Lejeune1-0/+3
2012-10-10R600: Fix typo in SETGE_UINT patterntstellar1-1/+1
2012-10-09R600: Add a pattern for: (selectcc i32, -1, i32, i32, SETGT)tstellar1-0/+7
2012-10-09R600: Add a comment explaining why we use TRUNC before FLT_TO_*INTtstellar1-0/+10
2012-10-03R600: Add support for v4i32 global storeststellar1-0/+6
2012-10-02R600: improve select_cc lowering to generate CND* more oftentstellar1-6/+32
2012-09-24R600: support for interpolation intrinsicststellar1-0/+54
2012-09-24R600: Handle loads from the constants address space.tstellar1-0/+9
2012-09-24R600: Add support for v4f32 stores on R600tstellar1-7/+23
2012-09-24R600: Add support for i8 reads on R600tstellar1-0/+16
2012-09-21Some cleanups after merge of Mesa branchtstellar1-1/+1
2012-09-21R600: Emit ISA for ALU instructions in the R600 code emitterMichal Sciubidlo1-61/+119
2012-09-21R600: Add a fdiv pattern.Tom Stellard1-3/+10
2012-09-21R600: Fix lowering of vbuildTom Stellard1-10/+10
2012-09-21AMDGPU: Don't print the default predicate stateTom Stellard1-1/+1
2012-09-21AMDGPU: Use new OperandWithDefaultOps for DOT* instructionsTom Stellard1-10/+5
2012-09-21AMDGPU: Updates for new tablegen property inferencesTom Stellard1-4/+17
2012-09-21AMDGPU: Add core backend files for R600/SI codegenTom Stellard1-0/+1266
2012-07-16Revert "AMDGPU: Add core backend files for R600/SI codegen v6"Tom Stellard1-1322/+0
2012-07-16AMDGPU: Add core backend files for R600/SI codegen v6Tom Stellard1-0/+1322