path: root/lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp
AgeCommit message (Expand)AuthorFilesLines
2012-10-17R600: Lower PRED_X to a native instruction prior to codegenTom Stellard1-1/+1
2012-10-17R600: Use native operands for R600_1OP instructionsTom Stellard1-18/+46
2012-10-17R600: Emit CONTINUE instructions correctlyTom Stellard1-3/+2
2012-10-15R600: Store channel index in the register's HWEncoding fieldtstellar1-24/+4
2012-10-02R600: Fix instruction encoding for r600 family GPUststellar1-2/+2
2012-09-25AMDGPU: Fix register encodingtstellar1-7/+1
2012-09-24R600: Handle loads from the constants address space.tstellar1-0/+1
2012-09-24R600: Add support for v4f32 stores on R600tstellar1-1/+2
2012-09-24R600: Add support for i8 reads on R600tstellar1-0/+1
2012-09-21Some cleanups after merge of Mesa branchtstellar1-1/+1
2012-09-21R600: Emit ISA for ALU instructions in the R600 code emitterMichal Sciubidlo1-87/+122
2012-09-21AMDGPU: Add core backend files for R600/SI codegenTom Stellard1-0/+669