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2014-05-15[mips][mips64r6] Add CLASS.fmt instructionsZoran Jovanovic3-5/+13
Differential Revision: http://reviews.llvm.org/D3712 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208894 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-15[mips][mips64r6] Add RINT.fmt instructionsZoran Jovanovic4-2/+33
Differential Revision: http://reviews.llvm.org/D3711 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208892 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-15[mips][mips64r6] Add SELEQZ/SELNEZ.fmt instructionsZoran Jovanovic3-4/+29
Differential Revision: http://reviews.llvm.org/D3710 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208891 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-15[mips][mips64r6] Add MAX/MIN/MAXA/MINA.fmt instructionsZoran Jovanovic3-7/+51
Differential Revision: http://reviews.llvm.org/D3709 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208890 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-15R600/SI: Stop using VSrc_* as the default register class for types.Tom Stellard2-63/+11
We now use SReg_* for integer types and VReg_* for floating-point types. This should help simplify the SIFixSGPRCopies pass and no longer causes ISel to insert a COPY after termiator instuctions that output a value. This change is covered by exisitng tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208888 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-15R600/SI: Fix a bug with handling of INSERT_SUBREG in SIFixSGPRCopiesTom Stellard2-7/+28
This prevents a future commit from regressing the load-i1.ll test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208887 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-15R600/SI: Only use SALU instructions for 64-bit add in a block of CF depth 0Tom Stellard2-5/+31
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208886 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-15R600/SI: Use VALU instructions for i1 opsTom Stellard4-23/+65
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208885 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-15TableGen: use correct MIOperand when printing aliasesTim Northover6-45/+56
Previously, TableGen assumed that every aliased operand consumed precisely 1 MachineInstr slot (this was reasonable because until a couple of days ago, nothing more complicated was eligible for printing). This allows a couple more ARM64 aliases to print so we can remove the special code. On the X86 side, I've gone for explicit AT&T size specifiers as the default, so turned off a few of the aliases that would have just started printing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208880 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-15[mips][mips64r6] Add bitswap, and dbitswapDaniel Sanders5-4/+35
Summary: Depends on D3728 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3729 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208877 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-15Instead of littering asserts throughout the code after every call toJay Foad3-93/+59
computeKnownBits, consolidate them into one assert at the end of computeKnownBits itself. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208876 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-15ARM64: print correct aliases for NEON mov & mvn instructionsTim Northover12-153/+145
In all cases, if a "mov" alias exists, it is the canonical form of the instruction. Now that TableGen can support aliases containing syntax variants, we can enable them and improve the quality of the asm output. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208874 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-15[mips][mips64r6] Add align and dalignDaniel Sanders7-10/+67
Summary: Depends on D3689 Reviewers: vmedic, zoran.jovanovic, jkolek Reviewed By: jkolek Differential Revision: http://reviews.llvm.org/D3728 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208872 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-15TableGen/ARM64: print aliases even if they have syntax variants.Tim Northover19-132/+155
To get at least one use of the change (and some actual tests) in with its commit, I've enabled the AArch64 & ARM64 NEON mov aliases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208867 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-15ARM64: add correct vector registers during asm parsingTim Northover2-5/+23
Previously, we ignored the difference between V64 and V128 when parsing assembly: they both got mapped to registers in the FPR128 class. This is basically harmless at the moment because they both print and encode the same way. However, it will affect the printing of aliases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208866 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-15[ARM64] Improve load/store diagnostics and forbid 32-bit register addressesBradley Smith2-6/+15
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208864 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-15[ARM64] Parse fixed vector lanes properly so that diagnostics can be emittedBradley Smith3-81/+92
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208863 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-15[ARM64] Add/Fixup diagnostics for floating point immediatesBradley Smith3-8/+23
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208862 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-15[ARM64] Add condition code operand type such that proper diagnostics can be ↵Bradley Smith4-32/+62
emitted git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208861 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-15[ARM64] Add more simple diagnostics for immediate/shift rangesBradley Smith2-10/+25
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208860 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-15[mips][mips64r6] Add addiupc, aluipc, and auipcDaniel Sanders9-6/+101
Summary: No support for symbols in place of the immediate yet since it requires new relocations. Depends on D3671 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3689 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208858 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-15[mips][mips64r6] Add aui, daui, dahi, and datiDaniel Sanders5-5/+64
Summary: Depends on D3671 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3759 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208857 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-15Teach the constant folder to look through bitcast constant expressionsChandler Carruth2-0/+84
much more effectively when trying to constant fold a load of a constant. Previously, we only handled bitcasts by trying to find a totally generic byte representation of the constant and use that. Now, we look through the bitcast to see what constant we might fold the load into, and then try to form a constant expression cast of the found value that would be equivalent to loading the value. You might wonder why on earth this actually matters. Well, turns out that the Itanium ABI causes us to create a single array for a vtable where the first elements are virtual base offsets, followed by the virtual function pointers. Because the array is homogenous the element type is consistently i8* and we inttoptr the virtual base offsets into the initial elements. Then constructors bitcast these pointers to i64 pointers prior to loading them. Boom, no more constant folding of virtual base offsets. This is the first fix to LLVM to address the *insane* performance Eric Niebler discovered with Clang on his range comprehensions[1]. There is more to come though, this doesn't *really* fix the problem fully. [1]: http://ericniebler.com/2014/04/27/range-comprehensions/ git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208856 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-15[mips][mips64r6] Test that branch likelies are not accepted on MIPS64r6.Daniel Sanders3-2/+36
Summary: They aren't implemented for any ISA at the moment. Depends on D3670 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3671 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208855 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-15Reverting r208848, reason: build failure: ↵Dinesh Dwivedi2-91/+5
sanitizer-x86_64-linux-bootstrap/builds/3399 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208852 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-15Added instcombine for 'MIN(MIN(A, 27), 93)' and 'MAX(MAX(A, 93), 27)'Dinesh Dwivedi2-2/+66
MIN(MIN(A, 23), 97) -> MIN(A, 23) MAX(MAX(A, 97), 23) -> MAX(A, 97) Differential Revision: http://reviews.llvm.org/D3629 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208849 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-15Added inst combine transforms for single bit tests from Chris's noteDinesh Dwivedi2-5/+91
if ((x & C) == 0) x |= C becomes x |= C if ((x & C) != 0) x ^= C becomes x &= ~C if ((x & C) == 0) x ^= C becomes x |= C if ((x & C) != 0) x &= ~C becomes x &= ~C if ((x & C) == 0) x &= ~C becomes nothing Z3 Verifications code for above transform http://rise4fun.com/Z3/Pmsh Differential Revision: http://reviews.llvm.org/D3717 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208848 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-15Fix some dyslexia in an assert messageJonathan Roelofs1-2/+2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208842 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-15Fix typosAlp Toker12-20/+20
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208839 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-15[ARM64] Support aggressive fastcc/tailcallopt breaking ABI by popping out ↵Jiangning Liu8-105/+553
argument stack from callee. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208837 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-15Remove unused functions setting MCOptions from TargetMachine.Eric Christopher1-15/+0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208835 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-15Unify command line handling of MCTargetOptions and remove extraEric Christopher4-33/+25
options and code. No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208833 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-15Move the TargetMachine MC options to MCTargetOptions. No functionalEric Christopher4-18/+21
change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208832 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-15InstCombine: Optimize -x s< cstDavid Majnemer2-0/+19
Summary: This gets rid of a sub instruction by moving the negation to the constant when valid. Reviewers: nicholas Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D3773 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208827 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-14DwarfDebug: Don't set frame index locations on abstract variables.David Blaikie1-2/+0
Abstract variables should never have/use locations. In this case the data wasn't used, so no functional change intended here, just simplification. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208820 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-14DebugInfo: Sure up subprogram variable list handling with more assertions ↵David Blaikie20-113/+69
and fewer conditionals. Many old tests using prior schemas still had some brokenness here (both indirect arrays and arrays with single bogus elements). Fixed those up so they don't hit the new assertions. Also reduced nesting in some places, etc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208817 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-14DebugInfo: Assert that a CU's subprogram list contains only subprograms.David Blaikie3-4/+4
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208816 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-14Teach llvm-nm to know about fat archives (aka MachOUniversal filesKevin Enderby5-5/+55
containing archives). First step as other tools will be updated next. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208812 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-14Rename ComputeMaskedBits to computeKnownBits. "Masked" has beenJay Foad44-313/+311
inappropriate since it lost its Mask parameter in r154011. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208811 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-14InstSimplify: Optimize signed icmp of -(zext V)David Majnemer2-0/+82
Summary: We know that -(zext V) will always be <= zero, simplify signed icmps that have these. Uncovered using http://www.cs.utah.edu/~regehr/souper/ Reviewers: nicholas Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D3754 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208809 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-14DebugInfo: Do not delay attaching DW_AT_inline attribute to abstract ↵David Blaikie2-18/+5
definitions. This is just unneccessary - we only create abstract definitions when we're inlining anyway, so there's no reason to delay this to see if we're going to inline anything. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208798 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-14ARM-BE: test files for vector argument passingChristian Pirker3-1/+2543
Reviewed at http://reviews.llvm.org/D3766 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208793 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-14[ARM64-BE] Fix byte order of CIE and FDE frames for exception handlingChristian Pirker2-0/+90
Reviewed at http://reviews.llvm.org/D3741 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208792 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-14Fix ARM EHABI when function has landingpad and nounwind.Logan Chien2-8/+68
If the function has the landingpad instruction, then the handlerdata should be emitted even if the function has nouwnind attribute. Otherwise, following code will not work: void test1() noexcept { try { throw_exception(); } catch (...) { log_unexpected_exception(); } } Since the cantunwind was incorrectly emitted and the LSDA is not available. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208791 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-14More test case for r208715.Logan Chien1-0/+59
The commit r208166 will cause some regression on ARM EHABI. This fix has been committed in r208715, and an assertion failure test case has been committed in r208770. This commit further extends the unittest so that the actual value in the handlerdata will be checked. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208790 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-14X86: If we have an instruction that sets a flag and a zero test on the input ↵Benjamin Kramer2-4/+138
of that instruction try to eliminate the test. For example tzcntl %edi, %ebx testl %edi, %edi je .label can be rewritten into tzcntl %edi, %ebx jb .label A minor complication is that tzcnt sets CF instead of ZF when the input is zero, we have to rewrite users of the flags from ZF to CF. Currently we recognize patterns using lzcnt, tzcnt and popcnt. Differential Revision: http://reviews.llvm.org/D3454 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208788 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-14[mips] Test that IAS for -mcpu=mips5 does not accept MIPS64 insns and ↵Daniel Sanders4-19/+97
-mcpu=mips(5|64) does not accept MIPS64r2 Summary: To limit the number of tests required, only one 64-bit ISA prior to MIPS64 are tested. rdhwr has been deliberately left without an ISA annotation for now. This is because the assembler and CodeGen disagree on when the instruction is available. Strictly speaking, it is only available in MIPS32r2 and MIPS64r2. However, it is emulated by a kernel trap on earlier ISA's and is necessary for TLS so CodeGen should emit it on older ISA's too. Depends on D3697 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3698 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208785 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-14[mips][mips64r6] Add sel.s and sel.dDaniel Sanders4-4/+56
Summary: Also use named constants for common opcode fields. Depends on D3669 Reviewers: vmedic, zoran.jovanovic, jkolek Reviewed By: jkolek Differential Revision: http://reviews.llvm.org/D3670 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208784 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-14ARM64: remove unneeded InstPrinter hacksTim Northover1-32/+0
Now that TableGen handles aliases, these are unneeded. Hopefully more will be able to go soon. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208781 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-14Regression test for ARM EHABI breakage in r208166.Evgeniy Stepanov1-0/+50
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208770 91177308-0d34-0410-b5e6-96231b3b80d8
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