summaryrefslogtreecommitdiff
AgeCommit message (Expand)AuthorFilesLines
2013-03-01XXX: It workssi-computeTom Stellard6-29/+155
2013-02-22R600: Clean up datalayout strings so they better match hardware capabilitiesTom Stellard2-12/+23
2013-02-22XXXX:Tom Stellard7-34/+91
2013-02-22XXXTom Stellard1-0/+1
2013-02-22XXXTom Stellard1-0/+7
2013-02-22XXX: WIP SI COMPUTETom Stellard5-2/+89
2013-02-22XXXTom Stellard1-0/+1
2013-02-22SI: Simplify MUBUF helper class for loadsTom Stellard4-23/+26
2013-02-22SI: Use same names for corresponding MUBUF operands and encoding fieldsTom Stellard2-26/+26
2013-02-22Made it more explicit that the self-referential llvm.loop identifier metadata Pekka Jaaskelainen1-1/+7
2013-02-22R600/SI: Add pattern for sign extension of i1 to i32.Michel Danzer1-0/+5
2013-02-22R600/SI: Add pattern for logical or of i1 values.Michel Danzer1-0/+4
2013-02-22R600/SI: Add pattern for fceil.Michel Danzer1-1/+3
2013-02-22Make ARMAsmPrinter generate the correct alignment specifier syntax in instruc...Kristof Beyls28-409/+408
2013-02-22Use references to attribute groups on the call/invoke instructions.Bill Wendling40-158/+248
2013-02-22Fix a nomenclature mistake. Slt->Slti in the functions. The "i" refersReed Kotler2-8/+8
2013-02-22Expand mips16 SelT form pseudso/macros.Reed Kotler10-4/+166
2013-02-22Fix isa<> check which could never be true.Pete Cooper2-1/+33
2013-02-22Remove code copied from GenRegisterInfo.inc.Andrew Trick2-57/+0
2013-02-22Code cleanup: pass Offset by pointer to parseInstruction to more explicitlyEli Bendersky1-29/+33
2013-02-22Remove warning about default covering no cases.Bill Wendling1-3/+2
2013-02-22Add a bitmask for NoBuiltin. This should *not* be used.Bill Wendling1-1/+2
2013-02-22Implement the NoBuiltin attribute.Bill Wendling10-35/+66
2013-02-21Stop relying on physical register kill flags in isKilled() in the two-addressCameron Zwarich1-3/+10
2013-02-21Previously, parsing capability of the .debug_frame section was addedEli Bendersky3-6/+184
2013-02-21Limit cast machinery to preserve const and not accept temporariesDavid Blaikie1-5/+47
2013-02-21Allow GlobalValues to vectorize with AliasAnalysisRenato Golin2-35/+510
2013-02-21Re-apply r175688, with the changes suggested by Jakob in PR15320.Lang Hames1-24/+15
2013-02-21Remove dead code and whitespace.Chad Rosier1-10/+0
2013-02-21Clear the whole table including the tombstones, since the tombstone count willPedro Artigas1-1/+1
2013-02-21Move the eliminateCallFramePseudoInstr method from TargetRegisterInfoEli Bendersky56-587/+558
2013-02-21Don't assert on empty attributes.Bill Wendling1-2/+2
2013-02-21Hexagon: Expand cttz, ctlz, and ctpop for now.Anshuman Dasgupta2-0/+39
2013-02-21Make RAFast::UsedInInstr indexed by register units.Jakob Stoklund Olesen3-22/+45
2013-02-21Radar numbers don't belong in source code.Evan Cheng3-4/+1
2013-02-21Trivial cleanupBill Schmidt1-2/+2
2013-02-21add missing space which prevented the llvm.loop code-block from appearing in thePaul Redmond1-0/+1
2013-02-21Large code model support for PowerPC.Bill Schmidt15-109/+227
2013-02-21Revert r175688 - It broke a test case (see PR15320).Lang Hames1-13/+25
2013-02-21getX86SubSuperRegister has a special mode with High=true for i64 whichEli Bendersky1-17/+9
2013-02-21DAGCombiner: Make the post-legalize vector op optimization more aggressive.Benjamin Kramer2-12/+0
2013-02-21R600/SI: inline V_ADD|SUB_F32 patternsChristian Konig1-9/+5
2013-02-21R600/SI: replace IMPLICIT_DEF with SIOperand.ZEROChristian Konig1-1/+1
2013-02-21R600/SI: replace SI_V_CNDLT with a patternChristian Konig3-31/+5
2013-02-21R600/SI: use patterns for clamp, fabs, fnegChristian Konig2-40/+22
2013-02-21R600/SI: add all the other missing asm operands v2Christian Konig2-22/+29
2013-02-21R600/SI: add the missing M*BUF|IMG asm operandsChristian Konig1-4/+8
2013-02-21R600/SI: add the missing S_* asm operandsChristian Konig1-18/+34
2013-02-21R600/SI: rework VOP3 classesChristian Konig1-14/+14
2013-02-21R600/SI: simplify VOPC_* pattern v2Christian Konig3-255/+217
generated by cgit v1.2.1 (git 2.18.0) at 2020-10-29 11:42:41 +0000