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2012-05-10Add MCRegisterInfo parameter to createMCCodeEmitter functionsr600-tablegen-hwregTom Stellard13-8/+29
2012-05-10AMDIL: Use new HWEncoding field in tablegen register classTom Stellard12-5045/+2076
2012-05-10TableGen: Add HWEncoding field to Register classTom Stellard3-5/+42
2012-05-10R600: Remove AsmTransCBE referenceTom Stellard1-2/+0
2012-05-10R600: Fix some miscompiles with R600ISelLowering.cppTom Stellard2-18/+6
2012-05-10R600: Regen R600RegisterInfo.tdTom Stellard1-1/+1
2012-05-10AMDIL: Remove SubRegClasses field from Register ClassesTom Stellard4-8/+1
2012-05-10R600: Regen filesTom Stellard3-159/+152
2012-05-10R600: Remove R600ShaderPatterns.tdTom Stellard1-4109/+0
2012-05-10R600: Remove AMDGPUConstants.pmTom Stellard2-45/+23
2012-05-10R600: Don't rely on tablegen for lowering int_AMDGPU_load_constTom Stellard3-34/+20
2012-05-10R600: Make sure the LOAD_CONST def uses the isSI predicateTom Stellard2-7/+7
2012-05-10AMDIL: Remove deleted files from CMakeLists.txtTom Stellard1-4/+0
2012-05-10R600: Remove AMDILUtilityFunctions.cppTom Stellard12-1040/+400
2012-05-10R600: Remove some unused functions from AMDILInstrInfoTom Stellard2-164/+0
2012-05-10R600: Add some comments and fix coding styleTom Stellard8-42/+41
2012-05-10R600: Remove the EXPORT_REG instructionTom Stellard8-108/+6
2012-05-10R600: Use a custom inserter to lower RESERVE_REGTom Stellard8-21/+80
2012-05-10R600: Use a custom inserter to lower STORE_OUTPUTTom Stellard4-34/+23
2012-05-10R600: Remove AMDGPULowerShaderInstructions classTom Stellard5-85/+4
2012-05-10R600: Use a custom inserter to lower LOAD_INPUTTom Stellard4-39/+15
2012-05-10R600: Remove the ReorderPreloadInstructions passTom Stellard8-99/+4
2012-05-10R600: Remove old comment from AMDIL.hTom Stellard1-5/+0
2012-05-10R600: add support for CUBE ALU instructionVadim Girlin5-21/+63
2012-05-10R600: add support for some ALU instructionsVadim Girlin3-12/+57
2012-05-10R600: add missing cases for BREAK/CONTINUEVadim Girlin2-0/+3
2012-05-10R600: add support for AHSR/LSHR/LSHL instructionsVadim Girlin3-0/+21
2012-05-10R600: add support for TXQ/TXF/DDX/DDY instructionsVadim Girlin3-0/+29
2012-05-10R600: fix live-in handling for inputsVadim Girlin2-2/+3
2012-05-10R600: add support for v4i32Vadim Girlin4-5/+20
2012-05-10R600: fix ABS_i32 instruction loweringVadim Girlin1-2/+2
2012-05-10R600: Lower ULT A, B, C to SETGT_UINT A, C, BTom Stellard1-0/+7
2012-05-10R600: Fix MachineInstr dumpTom Stellard1-1/+2
2012-05-10R600: Fix build for updated LLVM 3.1 release branchTom Stellard2-18/+18
2012-05-10R600: Add subtarget feature: DumpCodeTom Stellard4-6/+8
2012-05-10R600: Remove unnecessary dynamic castsDragomir Ivanov1-5/+5
2012-05-10R600: Add pattern for llvm.AMDGPU.kill v2Dragomir Ivanov2-1/+6
2012-05-10R600: Fix handling of MASK_WRITE instructionsTom Stellard2-1/+3
2012-05-10Build script changes for R600/SI CodegenTom Stellard6-11/+17
2012-05-10include/llvm: Add R600 IntrinsicsTom Stellard2-0/+37
2012-05-10test/CodeGen/R600: Add some basic testsTom Stellard27-0/+251
2012-05-10AMDIL: Add Function passes for R600/SI codegenTom Stellard21-0/+7667
2012-05-10AMDIL: Add R600/SI Tablegen definitions and generated filesTom Stellard44-0/+25104
2012-05-10AMDIL: Add core backend files for R600/SI codegenTom Stellard70-0/+13364
2012-05-10Fix merge-typo and cleanupNadav Rotem1-5/+3
2012-05-10AVX2: Add an additional broadcast idiom.Nadav Rotem2-2/+17
2012-05-10Generate AVX/AVX2 shuffles even when there is a memory op somewhere else in t...Nadav Rotem2-4/+17
2012-05-10Fix TableGen's RegPressureSet weight normalization to handle subreg DAGS.Andrew Trick1-4/+9
2012-05-10ExecutionEngine: Check for NULL ErrorStr before using it.Jim Grosbach1-2/+3
2012-05-09Fix warning text.Jakob Stoklund Olesen1-1/+1