AgeCommit message (Expand)AuthorFilesLines
2012-09-14R600: Fix lowering of vbuildr600-review-v10Tom Stellard7-93/+19
2012-09-14R600: Support fmul on SITom Stellard1-1/+4
2012-09-14R600: Fix operand order of V_CNDMASK in custom inserterTom Stellard1-1/+1
2012-09-14R600: Ignore special registers when calculating reg countTom Stellard1-0/+2
2012-09-14radeonsi: Handle position input parameter for pixel shaders v2Tom Stellard2-0/+22
2012-09-14R600: Coding style fixesTom Stellard4-31/+31
2012-09-14radeonsi: Move interpolation mode check into the compilerTom Stellard1-1/+12
2012-09-14R600: Add SHADER_TYPE instructionTom Stellard8-1/+32
2012-09-14R600: Match fexp2 for SI.Michel Dänzer1-1/+3
2012-09-14AMDGPU: Fix register assembly for SITom Stellard1-2/+2
2012-09-14AMDGPU: Add license to InstPrinter filesTom Stellard2-0/+16
2012-09-14AMDGPU: Don't print the default predicate stateTom Stellard2-2/+7
2012-09-14AMDGPU: Fix register namesTom Stellard1-3/+3
2012-09-14test/CodeGen/R600: Add checks for register operandsTom Stellard13-15/+15
2012-09-14AMDGPU: Use modern tablegen features in *RegisterInfo.tdTom Stellard4-2414/+111
2012-09-14AMDGPU: Use new OperandWithDefaultOps for DOT* instructionsTom Stellard1-10/+5
2012-09-14AMDGPU: Updates for new tablegen property inferencesTom Stellard7-19/+72
2012-09-14test/CodeGen/R600: Add some basic testsTom Stellard14-0/+227
2012-09-14include/llvm: Add R600 IntrinsicsTom Stellard2-0/+37
2012-09-14AMDGPU: Add core backend files for R600/SI codegenTom Stellard109-1/+21852
2012-09-14Add in comments that explain what the indexing and the size of the arrays is ...mvillmow1-1/+10
2012-09-14DAG post-process for Hexagon MI schedulerslarin2-0/+34
2012-09-14Fix Doxygen issues:gribozavr30-95/+113
2012-09-14SROA: Silence unused variable warnings in Release builds.d0k1-1/+8
2012-09-14Remove redundant private field.d0k2-3/+2
2012-09-14Rework the computation of a sub-structure natural type. There werechandlerc1-10/+20
2012-09-14Rely on the recursive check for pointer types rather than adding anchandlerc1-3/+0
2012-09-14Be a bit more aggressive in bailing out of this routine. Spotted bychandlerc1-1/+1
2012-09-14Add some comments clarifying that the GEP analysis for vector GEPs ischandlerc1-1/+4
2012-09-14Move an instance variable to a local variable based on review by Duncan.chandlerc1-9/+16
2012-09-14Add a comment about debug intrinsics that I *really* don't want tochandlerc1-0/+2
2012-09-14Add two asserts that Duncan thought would help ensure things don't rotchandlerc1-0/+2
2012-09-14Actually keep the flag default-off for now. =/ That's what I get forchandlerc1-1/+1
2012-09-14Remove some dead, commented out code Duncan spotted in review.chandlerc1-4/+0
2012-09-14Wrap the dumping and printing routines in NDEBUG and LLVM_ENABLE_DUMP macros.chandlerc1-0/+6
2012-09-14Lots of comment fixes and cleanups from Duncan's review.chandlerc1-10/+12
2012-09-14SROA.cpp: Unbreak gcc, sorry!chapuni1-2/+2
2012-09-14SROA.cpp: Appease msvc. LLVM_ATTRIBUTE(s) should come front of "const".chapuni1-2/+2
2012-09-14Speculative change to try to fix older GCC versions that can't handlechandlerc1-2/+2
2012-09-14Introduce a new SROA implementation.chandlerc10-2/+3907
2012-09-14Remove silly dead store. Patch by Ettl Martin.baldrick1-2/+1
2012-09-14Allow the second opcode info table to be 8, 16, or 32-bits as needed to repre...ctopper1-38/+32
2012-09-14Reduce size of register name index tables by using uint16_t for all in tree t...ctopper2-4/+6
2012-09-14misched: Generic tablegen classes for the new machine model.atrick1-7/+291
2012-09-14mips16 fixes.ahatanak2-2/+16
2012-09-13Patch by Sean Silva!gkistanova3-143/+92
2012-09-13Fix both the test for zero and what we do if we have a zero forechristo2-1/+54
2012-09-13Reformat, remove a couple unused variables and move some variablesechristo1-8/+8