AgeCommit message (Collapse)AuthorFilesLines
2012-04-25Build script changes for R600/SI Codegenr600-initial-reviewTom Stellard6-10/+17
2012-04-25include/llvm: Add R600 IntrinsicsTom Stellard2-0/+37
2012-04-25test/CodeGen/R600: Add some basic testsTom Stellard27-0/+251
2012-04-25AMDIL: Add Function passes for R600/SI codegenTom Stellard21-0/+7667
2012-04-25AMDIL: Add R600/SI Tablegen definitions and generated filesTom Stellard44-0/+24842
The following files are generated by perl scripts: => AMDGPUInstrEnums.include => AMDGPUInstrEnums.h.include => => => => R600HwRegInfo.include => => SIRegisterGetHWRegNum.include
2012-04-25AMDIL: Add core backend files for R600/SI codegenTom Stellard70-0/+13364
2012-04-25Reapply the SmallMap patch with a fix.Benjamin Kramer5-0/+1124
Comparing ~0UL with an unsigned will always return false when long is 64 bits long. git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-25Print IV chain numbers while collecting them.Jakob Stoklund Olesen1-4/+5
git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-25Remove more dead code.Jakob Stoklund Olesen3-24/+0
git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-25Unify internal representation of ARM instructions with a register ↵Richard Barton2-4/+10
right-shifted by #32. These are stored as shifts by #0 in the MCInst and correctly marshalled when transforming from or to assembly representation. git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-25Revert "First implementation of:"Eric Christopher5-1124/+0
This reverts commit 76271a3366731d4c372fdebcd8d3437e6e09a61b. as it's breaking the bots. git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-25First implementation of:Stepan Dyatkovskiy5-0/+1124
- FlatArrayMap. Very simple map container that uses flat array inside. - MultiImplMap. Map container interface, that has two modes, one for small amount of elements and one for big amount. - SmallMap. SmallMap is DenseMap compatible MultiImplMap. It uses FlatArrayMap for small mode, and DenseMap for big mode. Also added unittests for new classes and update for ProgrammersManual. For more details about new classes see ProgrammersManual and comments in sourcecode. git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-25Simplify LiveIntervals::getApproximateInstructionCount().Jakob Stoklund Olesen1-2/+1
This function is only used for a heuristic during -join-physregs. It doesn't need floating point. git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-25Remove a dead function.Jakob Stoklund Olesen1-6/+0
git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-25Remove the -disable-cross-class-join option.Jakob Stoklund Olesen1-13/+4
Cross-class joins have been normal and fully supported for a while now. With TableGen generating the getMatchingSuperRegClass() hook, they are unlikely to cause problems again. git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-25Cross-class joining is winning.Jakob Stoklund Olesen1-66/+0
Remove the heuristic for disabling cross-class joins. The greedy register allocator can handle the narrow register classes, and when it splits a live range, it can pick a larger register class. Benchmarks were unaffected by this change. <rdar://problem/11302212> git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-25Add ifdef around getSubtargetFeatureName in tablegen output file so that ↵Craig Topper2-3/+8
only targets that want the function get it. This prevents other targets from getting an unused function warning. git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-25Use vector_shuffles instead of target specific unpack nodes for AVX ↵Craig Topper1-18/+20
ZERO_EXTEND/ANY_EXTEND combine. These will be converted to target specific nodes during lowering. This is more consistent with other code. git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-25openbsd doesn't support soname, patch by Brad Smith!Chris Lattner1-0/+3
git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-25Actually delete now-empty file.Chandler Carruth1-0/+0
git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-25Reverting r155468. Chris and Chandler have convinced me that it's dangerous andLang Hames2-103/+0
in poor taste. Talking through some alternate solutions with Chandler. git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-25Do not use $gp as a dedicated global register if the target ABI is not O32. Akira Hatanaka3-7/+8
git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-25typo in declaration from earlier todayAndrew Trick1-1/+1
git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-25Simplify the known retain count tracking; use a boolean state insteadDan Gohman1-41/+34
of a precise count. Also, move RRInfo's Partial field into PtrState, now that it won't increase the size. git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24Build custom predecessor and successor lists for each basic block.Dan Gohman1-115/+101
These lists exclude invoke unwind edges and loop backedges which are being ignored. This makes it easier to ignore them consistently. git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24ARM: improved assembler diagnostics for missing CPU features.Jim Grosbach5-35/+83
When an instruction match is found, but the subtarget features it requires are not available (missing floating point unit, or thumb vs arm mode, for example), issue a diagnostic that identifies what the feature mismatch is. rdar://11257547 git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24Fix a naughty header include that breaks "installed" builds.Andrew Trick2-6/+16
git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24ConstantFoldSelectInstruction swapped the operands of the select.Nadav Rotem2-1/+14
Fix 12592. Patch by Matt Pharr. git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24Fix the testcase. We do expect two vblendw on XMMs.Nadav Rotem1-5/+6
git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24Add a testcase for 155440Nadav Rotem1-0/+13
git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24MachineBasicBlock::SplitCriticalEdge() should follow LLVM IR variant and ↵Evan Cheng2-0/+76
refuse to break edge to EH landing pad. rdar://11300144 git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24Add support for llvm.arm.neon.vmull* intrinsics to InstCombine. This fixesLang Hames2-0/+103
<rdar://problem/11291436>. git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24Fix a crash on valid (if UB) bitcode that is produced for some globalChandler Carruth2-3/+16
constants in C++11 mode. I have no idea why it required such particular circumstances to get here, the code seems clearly to rely upon unchecked assumptions. Specifically, when we decide to form an index into a struct type, we may have gone through (at least one) zero-length array indexing round, which would have left the offset un-adjusted, and thus not necessarily valid for use when indexing the struct type. This is just an canonicalization step, so the correct thing is to refuse to canonicalize nonsensical GEPs of this form. Implemented, and test case added. Fixes PR12642. Pair debugged and coded with Richard Smith. =] I credit him with most of the debugging, and preventing me from writing the wrong code. git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24ARM: Nuke remnant bogus code.Jim Grosbach1-2/+0
r154362 was supposed to delete this bit, but obviously didn't. rdar://11305594 git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24Related to PR1255. Let's begin. I'll commit classes that corresponds to our ↵Stepan Dyatkovskiy2-0/+524
latest PR1255 discussion posts in llvm-commits. Strategy. 0. Implement new classes. Classes doesn't affect anything. They still work with ConstantInt base values at this stage. 1. Fictitious replacement of current ConstantInt case values with ConstantRangesSet. Case ranges set will still hold single value, and ConstantInt *getCaseValue() will return it. But additionally implement new method in SwitchInst that allows to work with case ranges. Currenly I think it should be some wrapper that returns either single value or ConstantRangesSet object. 2. Step-by-step replacement of old "ConstantInt* getCaseValue()" with new alternative. Modify algorithms for all passes that works with SwitchInst. But don't modify LLParser and BitcodeReader/Writer. Still hold single value in each ConstantRangesSet object. On this stage some parts of LLVM will use old-style methods, and some ones new-style. 3. After all getCaseValue() usages will removed and whole LLVM and its clients will work in new style - modify LLParser, Reader and Writer. Remove getCaseValue(). 4. Replace ConstantInt*-based case ranges set items with APInt ones. Currently we are on Zero Stage: New classes. ConstantRangesSet. I selected ConstantArrays as case ranges set "holder" object (it is a temporary decision, I'll explain why below). The array items are may be ConstantVectors with single item, and ConstantVectors with two items (that means single number and range respectively). The ConstantInt will used as basic value representation. It will replaced with APInt then. Of course ConstantArray and ConstantVector will go away after ConstantInt => APInt replacement. New class mandatory features: - bool isSatisfies(ConstantInt *V) method (need better name?). Returns true if the given value satisfies this case. - Case's ranges and values enumeration. In some passes we need to analize each case (SwitchLowering for example). Factory + unified clusterify. I also propose to implement the factory that allows to build case object with user friendly way. I called it CRSBuilder by now. Currenly I implemented the factory that allows add,remove pairs of range+successor. It also allows add existing ConstantRangesSet decompiling it to separated ranges. Factory can emit either clusters set (single case range + successor) or the set of "ConstantRangesSet + Successor" pairs. So you can use it either as builder for new cases set for SwitchInst, or for clusterification of existing cases set. Just call Factory.optimize() and it emits optimized and sorted clusters collection for you! I tested clusterification on SelectionDAGBuilder - it works fine. Don't worry it was not included in this patch. Just new classes. Factory is a template. There are two params: SuccessorClass and IsReadonly. So you can specify what successor you need (BB or MBB). And you can also restrict your factory to use values in read-only mode (SelectionDAGBuilder need IsReadonly=true). Read-only factory couldn't build the cases ranges. git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24AVX: Add additional vbroadcast replacement sequences for integers.Nadav Rotem1-3/+30
Remove the v2f64 patterns because it does not match any vbroadcast instruction. git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24cmake: new fileAndrew Trick1-0/+1
git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24misched: DAG builder must special case earlyclobberAndrew Trick1-0/+9
git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24misched: try (not too hard) to place debug values where they belongAndrew Trick1-0/+25
git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24misched: ignore debug values during schedulingAndrew Trick1-6/+31
git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24misched: DAG builder support for tracking register pressure within the ↵Andrew Trick4-7/+65
current scheduling region. The DAG builder is a convenient place to do it. Hopefully this is more efficient than a separate traversal over the same region. git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24RegisterPressure: A utility for computing register pressure within aAndrew Trick2-0/+718
MachineInstr sequence. This uses the new target interface for tracking register pressure using pressure sets to model overlapping register classes and subregisters. RegisterPressure results can be tracked incrementally or stored at region boundaries. Global register pressure can be deduced from local RegisterPressure results if desired. This is an early, somewhat untested implementation. I'm working on testing it within the context of a register pressure reducing MachineScheduler. git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24Add missing test cases for ARM VLD3 (single 3-element structure to all lanes)Kevin Enderby2-0/+38
instructions. git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24Add missing test cases for ARM VLD4 (single 4-element structure to all lanes)Kevin Enderby2-0/+49
instructions. git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24AVX2: The BLENDPW instruction selects between vectors of v16i16 using an i8Nadav Rotem1-6/+0
immediate. We can't use it here because the shuffle code does not check that the lower part of the word is identical to the upper part. git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24Refactor Thumb ITState handling in ARM Disassembler to more efficiently use ↵Richard Barton1-31/+69
its vector git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24AVX: We lower VECTOR_SHUFFLE and BUILD_VECTOR nodes into vbroadcast instructionsNadav Rotem2-5/+83
using the pattern (vbroadcast (i32load src)). In some cases, after we generate this pattern new users are added to the load node, which prevent the selection of the blend pattern. This commit provides fallback patterns which perform in-vector broadcast (using in-vector vbroadcast in AVX2 and pshufd on AVX1). git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24Look for the 'Is Simulated' module flag. This indicates that the program is ↵Bill Wendling1-4/+5
compiled to run on a simulator. git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24FileCheck-ize tests.Bill Wendling7-11/+31
git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-24FileCheck-ize these tests.Bill Wendling2-3/+9
git-svn-id: 91177308-0d34-0410-b5e6-96231b3b80d8