index
:
~tstellar/llvm
9.1-abi-fix
Nov13-test
Oct18-backup
assembler
assembler-Jan-06-2015
assembler-push
backup-Oct15
backup-Oct18
bfgminer
bfgminer-perf
cayman-only-bfgminer
clover-elf
clover-elf-v2
hazard-rec
hsa
image-support
indirect-addressing
indirect-wip
indirect-wip-2
indirect-wip-3
indirect-wip-4
indirect-wip-5
kernel-args-WIP
lds
lds-v2
long-alu
madk
master
master-testing
master-testing-patches
master-testing-patches-v2
master-testing-si
master-testing-v2
mi-sched-experimental
native
opencv-Sep18-patches
perf-Dec31-2014
perf-Jan-08-2015
push-jan16
r600
r600-May09
r600-alu-encoding
r600-final-push
r600-gen-fixes
r600-imm-flags
r600-initial-review
r600-initial-review-May11
r600-master
r600-private-mem-fixes
r600-private-memory
r600-review-v10
r600-review-v3
r600-review-v7
r600-review-v8
r600-review-v9
r600-rewrite-pats
r600-structurizer
r600-structurizer-v2
r600-tablegen-hwreg
r600-tablegen-reg-encoding
r600-vliw
remove-fold-operands
sched-fixes
sched-perf-Mar-27-2015
si-compute
si-compute-v3
si-fold
si-lowercase
si-scheduler
si-scheduler-v2
si-scheduler-v3
si-sgpr-copies
si-spill-fixes
si-spill-fixes-v2
si-spill-fixes-v3
si-spill-fixes-v4
smrd-cluster
struct-divergence
struct-divergence-v1
vgpr-spilling-Jan07-2014
vinterp-fix
vliw5-rebase
vlj-bottom-up
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tstellar
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tree
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2013-06-04
R600: Fix the fetch limits for R600 generation GPUs
r600-gen-fixes
Tom Stellard
6
-27
/
+159
2013-06-04
R600: Move Subtarget feature definitions into AMDGPU.td
Tom Stellard
2
-64
/
+66
2013-06-04
R600: Remove unnecessary include
Tom Stellard
3
-2
/
+4
2013-06-05
R600: Make sure to schedule AR register uses and defs in the same clause
Tom Stellard
4
-4
/
+72
2013-06-05
Don't print default values for NumberOfAuxSymbols and AuxiliaryData.
Rafael Espindola
3
-2
/
+11
2013-06-05
Handle (at least don't crash on) relocations with no symbols.
Rafael Espindola
1
-6
/
+11
2013-06-05
Move BinaryRef to a new include/llvm/Object/YAML.h file.
Rafael Espindola
6
-51
/
+99
2013-06-05
Revert "R600: Add a pass that merge Vector Register"
Rafael Espindola
5
-400
/
+0
2013-06-05
Handle relocations that don't point to symbols.
Rafael Espindola
19
-73
/
+62
2013-06-04
[docs] Replace non-existent LLVM_YAML_UNIQUE_TYPE() macro
Sean Silva
1
-1
/
+1
2013-06-04
R600: Add a pass that merge Vector Register
Vincent Lejeune
5
-0
/
+400
2013-06-04
R600: Const/Neg/Abs can be folded to dot4
Vincent Lejeune
6
-47
/
+213
2013-06-04
Cortex-R5 can issue Thumb2 integer division instructions.
Evan Cheng
3
-21
/
+25
2013-06-04
Revert series of sched model patches until I figure out what is going on.
Arnold Schwaighofer
9
-1278
/
+208
2013-06-04
ARM sched model: Add VFP div instruction on Swift
Arnold Schwaighofer
1
-0
/
+16
2013-06-04
ARM sched model: Add SIMD/VFP load/store instructions on Swift
Arnold Schwaighofer
1
-0
/
+364
2013-06-04
ARM sched model: Add integer VFP/SIMD instructions on Swift
Arnold Schwaighofer
1
-0
/
+120
2013-06-04
ARM sched model: Add integer load/store instructions on Swift
Arnold Schwaighofer
1
-0
/
+209
2013-06-04
ARM sched model: Add integer arithmetic instructions on Swift
Arnold Schwaighofer
1
-0
/
+155
2013-06-04
ARM sched model: Cortex A9 - More InstRW sched resources
Arnold Schwaighofer
1
-4
/
+45
2013-06-04
ARM sched model: Add branch thumb instructions
Arnold Schwaighofer
1
-18
/
+21
2013-06-04
ARM sched model: Add branch thumb2 instructions
Arnold Schwaighofer
1
-11
/
+15
2013-06-04
ARM sched model: Add branch instructions
Arnold Schwaighofer
1
-27
/
+35
2013-06-04
ARM sched model: Add preload thumb2 instructions
Arnold Schwaighofer
1
-3
/
+6
2013-06-04
ARM sched model: Add preload instructions
Arnold Schwaighofer
1
-2
/
+4
2013-06-04
ARM sched model: Add more ALU and CMP thumb instructions
Arnold Schwaighofer
1
-46
/
+61
2013-06-04
ARM sched model: Add more ALU and CMP thumb2 instructions
Arnold Schwaighofer
1
-52
/
+86
2013-06-04
ARM sched model: Add more ALU and CMP instructions
Arnold Schwaighofer
1
-37
/
+49
2013-06-04
ARM sched model: Add divsion, loads, branches, vfp cvt
Arnold Schwaighofer
4
-7
/
+89
2013-06-04
ARMInstrInfo: Improve isSwiftFastImmShift
Arnold Schwaighofer
1
-0
/
+2
2013-06-04
SubtargetEmitter fix
Arnold Schwaighofer
1
-1
/
+1
2013-06-04
Fix link.
Richard Smith
1
-1
/
+1
2013-06-04
Sparc: No functionality change. Cleanup whitespaces, comment formatting etc.,
Venkatraman Govindaraju
19
-154
/
+157
2013-06-04
IndVarSimplify: check if loop invariant expansion can trap
David Majnemer
2
-1
/
+33
2013-06-04
ARM: Fix crash in ARM backend inside of ARMConstantIslandPass
David Majnemer
2
-0
/
+15
2013-06-04
Remove "-Wl,-seg1addr -Wl,0xE0000000" from link options.
Bob Wilson
3
-6
/
+3
2013-06-04
R600: Swizzle texture/export instructions
Vincent Lejeune
3
-25
/
+131
2013-06-04
R600: Add a test for r183108
Vincent Lejeune
1
-0
/
+2
2013-06-04
Second part of pr16069
Rafael Espindola
2
-5
/
+24
2013-06-04
Typo: s/caes/cases/ in SimplifyCFG
Hans Wennborg
1
-1
/
+1
2013-06-04
Preserve const correctness.
Benjamin Kramer
1
-3
/
+3
2013-06-04
Test commit for user vmedic, to verify commit access. One line of comment is ...
Vladimir Medic
1
-1
/
+1
2013-06-04
[llvm-symbolizer] Avoid calling slow getSymbolSize for Mach-O files. Assume t...
Alexey Samsonov
3
-9
/
+25
2013-06-04
We are now in 3.4 land. We don't need the 3.3 releaese notes in ToT anymore.
Bill Wendling
2
-283
/
+9
2013-06-04
IEEE-754R 5.7.2 General Operations is* operations (except for isCanonical).
Michael Gottesman
2
-7
/
+103
2013-06-04
Silencing an MSVC warning about mixing bool and unsigned int.
Aaron Ballman
1
-1
/
+1
2013-06-04
Silencing an MSVC warning about */ being found outside of a comment.
Aaron Ballman
1
-2
/
+2
2013-06-04
Fix a defect in code-layout pass, improving Benchmarks/Olden/em3d/em3d by abo...
Shuxin Yang
1
-1
/
+25
2013-06-03
Delete dead safety check.
Nick Lewycky
1
-6
/
+1
2013-06-03
SimplifyCFG: Do not transform PHI to select if doing so would be unsafe
David Majnemer
2
-2
/
+33
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