AgeCommit message (Expand)AuthorFilesLines
2014-12-10ScheduleDAGInstrs: Consider sub-registers when computing vreg def dependenciesmi-sched-experimentalTom Stellard1-1/+2
2014-12-10MachineRegisterInfo: Add SubIdx argument to hasOneDef()Tom Stellard2-6/+23
2014-11-25TargetRegisterInfo: Add target query subRegWriteClobbersSuperReg()Tom Stellard1-0/+13
2014-11-25XXX: Load clustering fix.Tom Stellard1-10/+41
2014-11-24R600/SI: Remove unused register classTom Stellard1-7/+0
2014-11-24XXX: Maystore = 0 on MUBUF loadsTom Stellard1-1/+1
2014-11-24XXX: Sched improvementsTom Stellard1-1/+3
2014-11-24R600/SI: Define a schedule model and enable the generic machine schedulerTom Stellard8-25/+217
2014-11-24Added comment about llvm_execute_on_thread waiting for thread to complete.Yaron Keren1-1/+2
2014-11-24[mips][microMIPS] Implement LBU16, LHU16, LW16, SB16, SH16 and SW16 instructionsJozef Kolek7-0/+209
2014-11-24[mips][microMIPS] Implement 16-bit instructions registers including ZERO inst...Jozef Kolek3-0/+41
2014-11-24[Mips] Update MIPS relocations listSimon Atanasyan1-0/+28
2014-11-24Replace a comment that says 'unreachable' with llvm_unreachable in TableGen A...Craig Topper1-1/+1
2014-11-24Removing a variable that is initialized but never read. The original author h...Aaron Ballman1-6/+2
2014-11-24[mips][microMIPS] Implement disassembler support for 16-bit instructionsJozef Kolek4-14/+147
2014-11-24[X86] Improved target specific combine on VSELECT dag nodes.Andrea Di Biagio3-153/+192
2014-11-24InstCombine: Don't assume DataLayout is always availableDavid Majnemer2-1/+22
2014-11-24Support: Add *cast_or_null<> for pointer wrappersDuncan P. N. Exon Smith2-0/+130
2014-11-24Detect best type for some static index tables instead of just using uint32_t ...Craig Topper1-15/+24
2014-11-23Converted back to Unix format (after my last commit 222632)Elena Demikhovsky1-3241/+3241
2014-11-23[X86] Fixes bug in build_vector v4x32 loweringMichael Kuperstein2-3/+23
2014-11-23Add missing override keywords.Craig Topper1-2/+2
2014-11-23Tablegen output formatting fixes.Craig Topper1-2/+4
2014-11-23Masked Vector Load and Store Intrinsics.Elena Demikhovsky32-3154/+4418
2014-11-23R600: Fix extloads of i1 on R600/EvergreenMatt Arsenault2-13/+33
2014-11-23R600: Fix assert on copy of an i1 on pre-SIMatt Arsenault1-1/+2
2014-11-23R600/SI: Add additional tests for i1 loadsMatt Arsenault1-1/+22
2014-11-23R600/SI: Fix broken check lines and modernize prefixesMatt Arsenault2-48/+50
2014-11-23R600/SI: Fix missing -verify-machineinstrs on a testMatt Arsenault1-1/+1
2014-11-22InstCombine: Propagate exact for (sdiv X, Pow2) -> (udiv X, Pow2)David Majnemer2-2/+15
2014-11-22InstCombine: Propagate exact for (sdiv X, Y) -> (udiv X, Y)David Majnemer2-1/+13
2014-11-22InstCombine: Propagate exact for (sdiv -X, C) -> (sdiv X, -C)David Majnemer2-4/+15
2014-11-22Tidied up target triple OS detection. NFCSimon Pilgrim6-14/+25
2014-11-22Reduce size of some tables in tablegen register info output.Craig Topper2-50/+54
2014-11-22InstCombine: Propagate exact in (udiv (lshr X,C1),C2) -> (udiv x,C1<<C2)David Majnemer2-2/+16
2014-11-22[x86] Teach the vector shuffle yet another step of canonicalization.Chandler Carruth1-2/+13
2014-11-22InstCombine: Propagate NSW/NUW for X*(1<<Y) -> X<<YDavid Majnemer2-4/+33
2014-11-22InstCombine: Propagate NSW for -X * -Y -> X * YDavid Majnemer2-3/+19
2014-11-22InstSimplify: Simplify (sub 0, X) -> X if it's NUWDavid Majnemer2-11/+10
2014-11-22InstCombine: Silence a parenthesis warningDavid Majnemer1-1/+1
2014-11-22[x86] Add some tests for a common unpack pattern of vector shuffle thatChandler Carruth3-0/+72
2014-11-22InstCombine: Preserve nsw when folding X*(2^C) -> X << CDavid Majnemer3-5/+7
2014-11-22InstCombine: Preserve nsw/nuw for ((X << C2)*C1) -> (X * (C1 << C2))David Majnemer2-3/+28
2014-11-22InstCombine: Preserve nsw for (mul %V, -1) -> (sub 0, %V)David Majnemer2-2/+14
2014-11-21[InstCombine] Re-commit of r218721 (Optimize icmp-select-icmp sequence)Gerolf Hoflehner9-11/+428
2014-11-21Fix transformation of add with pc argument to adr for non-immediateJoerg Sonnenberger2-7/+33
2014-11-21[asan] remove old experimental codeKostya Serebryany2-61/+0
2014-11-21R600/SI: Add a failing test case for offset order in ds_read2 instructionsTom Stellard1-0/+44
2014-11-21R600/SI: Add an s_mov_b32 to patterns which use the M0RegClassTom Stellard2-24/+8
2014-11-21R600/SI: Emit s_mov_b32 m0, -1 before every DS instructionTom Stellard7-41/+30