summaryrefslogtreecommitdiff
AgeCommit message (Collapse)AuthorFilesLines
2012-12-21R600: Support for indirect addressingindirect-wip-5Tom Stellard26-62/+1236
2012-12-11R600: Add an intrinsic to handle stream outputs.Vincent Lejeune6-0/+102
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2012-12-11R600: Add a field for Export node (compMask) and factorise code handling ↵Vincent Lejeune2-42/+58
store intrinsic Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2012-12-11R600: Split Word0 and Word1 in Export instructionVincent Lejeune3-49/+60
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2012-12-11AMDGPU/SI: Only allow selecting VGPRs with V_CNDMASK_B32.Michel Dänzer1-4/+4
VALU instructions can only read from one SGPR, and that's the condition code mask in this case. Fixes a number of radeonsi piglit regressions from Vincent's max/min changes (which means the matching to AMDGPUfmax/min doesn't work for some reason). Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
2012-12-11AMDGPU: Match fdiv for SI.Michel Dänzer1-0/+5
Fixes hundreds of radeonsi piglit regressions from commit 62c8e1ec4a93b28c55c1c7accb6cbd64952e59c2 ('AMDGPU: replace int_AMDGPU_rcp by fdiv (1.0, x) in RECIP pattern'). Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
2012-12-11R600: Add support for i8 and i16 function argumentsTom Stellard5-15/+92
2012-12-11R600: Improve assembly output for VTX instructionsTom Stellard4-7/+13
2012-12-11AMDGPU: Promote floating-point load/store to integer load/storeTom Stellard4-60/+37
This will reduce the number of tablegen patterns we need.
2012-12-11LegalizeDAG: Allow promotion of scalar loadsTom Stellard1-3/+2
2012-12-11LegalizeDAG: Allow type promotion for scalar storesTom Stellard1-3/+4
2012-12-11R600: Convert global store address to dword offset during iselTom Stellard7-14/+46
Reviewed-by: Vincent Lejeune <vljn at ovi.com>
2012-12-05R600: Fix use iterator in custom select of ISD::ConstantTom Stellard1-2/+3
The use list may change during the execution of the loop, so we need to manually keep track of the next item in the list.
2012-12-05AMDGPU: add a pattern for min/maxTom Stellard6-8/+79
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2012-12-05AMDGPU: replace int_AMDGPU_rcp by fdiv (1.0, x) in RECIP patternVincent Lejeune3-4/+4
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2012-12-05AMDGPU: Match AMDGPU.cube intrinsic for SI.Michel Dänzer1-0/+21
Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Reviewed by: Christian König <christian.koenig@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
2012-12-05AMDGPU: Doxygen fixesTom Stellard72-517/+572
- Add \file to every file - Use \brief, \returns, \param, etc. where necessary - Remove duplicate function / class names from doxygen comments
2012-12-05AMDGPU: Various coding style fixesTom Stellard46-518/+452
- Fix more coding style errors with braces on their own line Found using: grep -rn '^[ ]*{$' - Remove underscore from start of macro defs - Remove all tabs - Remove "end of" comments that don't refer to namespaces. - Fix an issue with parens being on the wrong line. - Fix warnings from building with clang
2012-11-29R600: Fold immediates into ALU instructions when possible v2Tom Stellard9-6/+153
v2: - Fold the immediates using the SelectionDAG Reviewed-by: Vincent Lejeune <vljn at ovi.com>
2012-11-29AMDGPU: Remove or document commented out codeTom Stellard4-92/+13
Reviewed-by: Vincent Lejeune <vljn at ovi.com>
2012-11-29AMDGPU: Fix 4-space indentationTom Stellard3-73/+73
Reviewed-by: Vincent Lejeune <vljn at ovi.com>
2012-11-29AMDGPU: Remove unused macros v2Tom Stellard6-100/+19
v2: - Fix alignment of case statements Reviewed-by: Vincent Lejeune <vljn at ovi.com>
2012-11-29AMDGPU: Coding style - put braces on same line as function headersTom Stellard27-458/+229
Reviewed-by: Vincent Lejeune <vljn at ovi.com>
2012-11-29AMDGPU: Simplify SI control flow loweringChristian König1-41/+38
By using the S_*_SAVEEXEC_b64 instructions. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Reviewed-and-tested-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Christian König <deathsimple@vodafone.de>
2012-11-29AMDGPU: Fix S_*_SAVEEXEC_B64 definesChristian König1-2/+8
Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Reviewed-and-tested-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Christian König <deathsimple@vodafone.de>
2012-11-29R600: rename if/break operator to improve readabilityVincent Lejeune4-61/+29
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2012-11-29R600: do not use magic number for resourceIdVincent Lejeune4-53/+60
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2012-11-29R600: add fsqrt pattern for r600/r700Vincent Lejeune1-0/+3
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2012-11-29R600: Valid pixel mode and EOP were inverted in exportVincent Lejeune1-2/+2
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2012-11-29SI: Use IMAGE_SAMPLE_L for the SI.sample.lod intrinsic.Michel Dänzer1-2/+2
Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
2012-11-16AMDGPU: Fix name of SI control flow lowering source file.Michel Dänzer1-1/+1
Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
2012-11-16AMDGPU: Don't allow using SI SGPRs 102 and 103 directly.Michel Dänzer1-2/+2
Two SGPRs are used for VCC, so it's not possible to use these and VCC together. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
2012-11-16AMDGPU: Fix string concatenation in AMDGPUInstPrinter::printRel().Michel Dänzer1-1/+1
Pointed out by compiler warning: /home/daenzer/src/llvm-git/llvm/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp:96:16: warning: adding 'int64_t' (aka 'long') to a string does not append to the string [-Wstring-plus-int] O << " + " + Op.getImm(); ~~~~~~^~~~~~~~~~~~~ /home/daenzer/src/llvm-git/llvm/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp:96:16: note: use array indexing to silence this warning O << " + " + Op.getImm(); ^ & [ ] 1 warning generated. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
2012-11-16R600: replaces fragment input with negative index with undef valuesVincent Lejeune1-3/+9
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2012-11-16R600: Fix operand index table for OP3 instructionsTom Stellard1-1/+1
Reviewed-by: Vincent Lejeune <vljn at ovi.com>
2012-11-16AMDGPU: Print integer and floating point values for literalsTom Stellard3-1/+13
Reviewed-by: Vincent Lejeune <vljn at ovi.com>
2012-11-16R600: Add helper function for setting instruction modifiersTom Stellard3-9/+16
Reviewed-by: Vincent Lejeune <vljn at ovi.com>
2012-11-13AMDGPU: Fix builds with -DNDEBUGtstellar1-0/+2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@167845 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13R600: Fix sampler->resource_id mappingtstellar1-2/+2
Patch by: Vadim Girlin Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@167844 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13SI: s/flow control/control flow/g .tstellar4-15/+15
Patch by: Michel Dänzer Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@167843 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13SI: fix SGPR liveness v4tstellar4-0/+191
SGPRs are not affected by control flow. v2: don't use liveness analyse any more, handle partial dominated end notes. v3: fix old pass name in CMakeLists.txt v4: remove unnecessary successor handling and kill handling Patch by: Christian König Signed-off-by: Christian König <deathsimple@vodafone.de> Tested-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@167842 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13SI: Add intrinsic for sampling with explicit LOD.tstellar2-1/+9
Patch by: Michel Dänzer Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@167841 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13SI: Add intrinsic for sampling with bias.tstellar2-1/+9
Patch by: Michel Dänzer Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@167840 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13SI: Update flow control comments to match current code.tstellar1-4/+5
Patch by: Michel Dänzer Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@167839 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13Merge master branchtstellar599-7650/+20056
Build with clang checkouts: SVN: r167547 Git Mirror: b578aee665aad5ed1a46a26217c730fdfbfc8c2e git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@167838 91177308-0d34-0410-b5e6-96231b3b80d8
2012-11-13SI: Only allow SGPR for the first operand of VOP3 instructions.tstellar2-4/+4
This is technically too strict: While a VOP3 instruction can only use one SGPR, it can be used for any operand, even for several operands at the same. But for now this is a simple solution which fixes the problem (e.g. causing broken linear fog with radeonsi) at little extra cost (in the form of V_MOV_* from SGPR to VGPR). Patch by: Michel Dänzer Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@167837 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-31SI: Enable control flow pass againtstellar1-2/+1
radeonsi can run piglit reliably with it now. It fixes hundreds of tests and prevents many more from crashing. Patch by: Michel Dänzer Reviewed-by: Tom Stellard <thomas.stellar@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@167129 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-31SI: Handle kilp intrinsictstellar1-0/+5
Patch by: Michel Dänzer Reviewed-by: Tom Stellard <thomas.stellar@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@167128 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-31SI: Use SReg_1 class for SI_IF_(N)Z condition code operandtstellar1-3/+3
Patch by: Michel Dänzer Reviewed-by: Tom Stellard <thomas.stellar@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@167127 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-31SI: Prevent instructions modifying the EXEC register from being movedtstellar2-0/+6
Patch by: Michel Dänzer Reviewed-by: Tom Stellard <thomas.stellar@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@167126 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.2.3 (git 2.39.1) at 2024-04-18 06:01:07 +0000