AgeCommit message (Expand)AuthorFilesLines
2012-10-23XXX:indirect-addressingTom Stellard8-8/+228
2012-10-22R600: Cayman uses vector instruction for SIN/COS/RECIP_CLAMPED_RECIPSQRT_IEEEtstellar1-10/+20
2012-10-22R600: turn select into select_cctstellar2-0/+17
2012-10-22R600: add support for vector setCCtstellar1-4/+2
2012-10-22R600: Remove input.face and input.position intrinsicststellar3-40/+0
2012-10-22R600: Add super reg to reserved reg listtstellar1-0/+3
2012-10-22R600: interp instructions emits native outputststellar3-38/+27
2012-10-22R600: Fix llvm.pow.ll testtstellar1-1/+1
2012-10-22AMDGPU: Fix build after mergetstellar1-1/+1
2012-10-22Merge master branchtstellar164-783/+5586
2012-10-19R600: Remove deprecated code from R600MCCodeEmittertstellar1-129/+9
2012-10-19R600: Use native operands for KILLGT instructiontstellar4-38/+29
2012-10-19R600: Use native operands for CUBE*, DOT4* instructionststellar3-68/+46
2012-10-19R600: Organize pseudo instruction in R600Instructions.tdtstellar1-27/+10
2012-10-19R600: Add support for the AMDGPU::BREAK instructiontstellar1-1/+17
2012-10-19R600: Lower PRED_X to a native instruction prior to codegentstellar9-50/+111
2012-10-19R600: Use native operands for R600_OP3 instructionststellar1-34/+64
2012-10-19R600: Use native operands for R600_2OP instructionststellar4-123/+79
2012-10-19R600: Use native operands for MOV_IMM_* instructionststellar4-23/+42
2012-10-19R600: Use native operands for the MOV Instructiontstellar7-47/+60
2012-10-19R600: Use native operands for R600_1OP instructionststellar9-140/+469
2012-10-19R600: Emit CONTINUE instructions correctlytstellar1-3/+2
2012-10-19R600: Prevent the CFG Structurizer from emitting extra ENDIFststellar1-1/+0
2012-10-19AMDGPU: Remove unused llvm.AMDGPU.ssg intrinsictstellar2-8/+0
2012-10-19R600: Fix DIV_Common pattern usetstellar1-1/+3
2012-10-19R600: Set FlagOperandIdx for RECIP_IEEEtstellar1-5/+5
2012-10-19R600: Cayman now uses vector version of EXP_IEEE, LOG_IEEE and RECIPSQRT_CLAMPEDtstellar1-9/+19
2012-10-19R600: Lower fpow(A, B) to fexp(mul(B, flog(A))) at DAG leveltstellar3-2/+13
2012-10-16AMDGPU: Fix build after mergetstellar1-8/+0
2012-10-16Merge master branchtstellar381-4194/+18653
2012-10-15R600: use ceil intrinsic instead of llvm.AMDIL.round.posinftstellar2-4/+0
2012-10-15R600: use floor intrinsic instead of llvm.AMDIL.floortstellar5-5/+5
2012-10-15R600: use llvm fabs intrinsictstellar3-5/+3
2012-10-15R600: use llvm intrinsic for flog2tstellar3-3/+2
2012-10-15R600: add support for cos/sin intrinsictstellar4-14/+17
2012-10-15R600: add a pattern for fsqrttstellar1-0/+3
2012-10-15R600: Store channel index in the register's HWEncoding fieldtstellar8-1117/+31
2012-10-11AMDGPU: Fix lowering of UREMtstellar1-5/+4
2012-10-11AMDGPU: Fix build after merging of DataLayout changeststellar3-5/+5
2012-10-11Merge master branchtstellar602-8117/+12984
2012-10-10R600: Fix typo in SETGE_UINT patterntstellar1-1/+1
2012-10-09R600: Disable SI flow control again for nowtstellar1-1/+2
2012-10-09R600: Handle reversed true/false values in selectcctstellar2-6/+26
2012-10-09R600: Prefer lowering SELECT_CC to CND* instructions over SET* instructionststellar2-42/+66
2012-10-09R600: Fix lowering of fcmptstellar4-7/+55
2012-10-09R600: Add a pattern for: (selectcc i32, -1, i32, i32, SETGT)tstellar2-0/+28
2012-10-09R600: Add a comment explaining why we use TRUNC before FLT_TO_*INTtstellar1-0/+10
2012-10-09R600: Add store v4i32 testtstellar1-0/+9
2012-10-09R600: Add tests for a few vector operationststellar7-0/+106
2012-10-03SI: Mark the V_CMPX* instructions as having side effectststellar1-0/+32