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2012-10-17R600: Organize pseudo instruction in R600Instructions.tdbackup-Oct18Tom Stellard1-27/+10
2012-10-17R600: Lower PRED_X to a native instruction prior to codegenTom Stellard9-50/+119
2012-10-17R600: Use native operands for R600_OP3 instructionsTom Stellard1-34/+64
2012-10-17R600: Use native operands for R600_2OP instructionsTom Stellard4-123/+79
2012-10-17R600: Use native operands for MOV_IMM_* instructionsTom Stellard4-23/+42
2012-10-17R600: Use native operands for the MOV InstructionTom Stellard7-47/+60
2012-10-17R600: Use native operands for R600_1OP instructionsTom Stellard8-128/+444
2012-10-17R600: Emit CONTINUE instructions correctlyTom Stellard1-3/+2
The finalizer in mesa was incorrectly handling conditional continue instructions and the backend wasn't generating code for the unconditional version at all. This patch enables code generation for the unconditional continue and disables it for conditional continue.
2012-10-17AMDGPU: Remove unused llvm.AMDGPU.ssg intrinsicTom Stellard2-8/+0
2012-10-16AMDGPU: Fix build after mergetstellar1-8/+0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@166034 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-16Merge master branchtstellar381-4194/+18653
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@166033 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-15R600: use ceil intrinsic instead of llvm.AMDIL.round.posinftstellar2-4/+0
Patch by: Vincent Lejeune Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@165971 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-15R600: use floor intrinsic instead of llvm.AMDIL.floortstellar5-5/+5
Patch by: Vincent Lejeune Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@165970 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-15R600: use llvm fabs intrinsictstellar3-5/+3
Patch by: Vincent Lejeune Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@165969 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-15R600: use llvm intrinsic for flog2tstellar3-3/+2
Patch by: Vincent Lejeune Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@165968 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-15R600: add support for cos/sin intrinsictstellar4-14/+17
Patch by: Vincent Lejeune Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@165967 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-15R600: add a pattern for fsqrttstellar1-0/+3
Patch by: Vincent Lejeune Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@165966 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-15R600: Store channel index in the register's HWEncoding fieldtstellar8-1117/+31
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@165965 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-11AMDGPU: Fix lowering of UREMtstellar1-5/+4
We now use ISD::MergeValues for creating a UDIVREM Node with 2 results, rather than SelectionDAG::ReplaceAllUsesWith(), which was not working for the second result. Fixes piglit test: Program/Execute/Scalar arithmetic uint git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@165750 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-11AMDGPU: Fix build after merging of DataLayout changeststellar3-5/+5
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@165749 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-11Merge master branchtstellar602-8117/+12984
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@165748 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-10R600: Fix typo in SETGE_UINT patterntstellar1-1/+1
The operands to SETGE_UINT were reversed. Fixes piglit test: Program/Execute/Scalar comparison uint git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@165622 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-09R600: Disable SI flow control again for nowtstellar1-1/+2
It makes piglit unreliable due to VM protection faults and GPU lockups. Patch by: Michel Dänzer Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@165529 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-09R600: Handle reversed true/false values in selectcctstellar2-6/+26
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@165528 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-09R600: Prefer lowering SELECT_CC to CND* instructions over SET* instructionststellar2-42/+66
SET* instructions are more expensive, because in some cases they require additional instructions to convert their result to the correct type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@165527 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-09R600: Fix lowering of fcmptstellar4-7/+55
In most cases, R600 requires that all operands of SELECT_CC nodes have the same type. However, we were incorrectly converting between floating point true(1.0f) / false(0.0f) and interger true(-1) / false(0), which was causing miscompiles for fcmp instructions that were lowered to SELECT_CC nodes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@165526 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-09R600: Add a pattern for: (selectcc i32, -1, i32, i32, SETGT)tstellar2-0/+28
This is now lowered to a CNDGE_INT instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@165525 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-09R600: Add a comment explaining why we use TRUNC before FLT_TO_*INTtstellar1-0/+10
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@165524 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-09R600: Add store v4i32 testtstellar1-0/+9
This was supposed to be committed with: "R600: Add support for v4i32 global stores" git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@165523 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-09R600: Add tests for a few vector operationststellar7-0/+106
These were supposed to be commited with: "R600: Handle more vector arithmetic instructions" git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@165522 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-03SI: Mark the V_CMPX* instructions as having side effectststellar1-0/+32
The side effect is that they write the EXEC register. This prevents them from being dead code eliminated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@165155 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-03R600: Handle more vector arithmetic instructionststellar1-0/+8
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@165154 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-03R600: Implement getSetCCResultType in R600TargetLowering clasststellar2-0/+8
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@165153 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-03R600: Add support for v4i32 global storeststellar1-0/+6
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@165152 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-03SI: Fix crash in unused register search in LowerFlowControl pasststellar1-4/+4
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@165115 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-03SI: S_WAITCNT has side effectststellar1-0/+2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@165114 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-03SI: Set the section in the Asm Printer before emitting program infotstellar1-1/+1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@165113 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-03SI: Fix bug in loops where iterators may be deletedtstellar2-2/+4
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@165112 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-03SI: Add sanity testtstellar1-0/+37
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@165111 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-02Merge master branchtstellar36-121/+423
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@165014 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-02R600: improve select_cc lowering to generate CND* more oftentstellar5-42/+110
Patch by: Vincent Lejeune v2: - Simplify isZero() - Remove a unused function prototype - Clean whitespace trails Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@165013 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-02R600: Fix instruction encoding for r600 family GPUststellar3-15/+15
Tested-by: Michel Dänzer <michel.daenzer@amd.com> https://bugs.freedesktop.org/show_bug.cgi?id=55217 git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@165012 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-02Merge master branchtstellar237-2024/+11083
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@165011 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-02Merge TOTtstellar33-168/+699
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@165010 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-25R600: Fix typo in R600RegisterInfo.tdtstellar1-1/+1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@164603 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-25AMDGPU: Fix register encodingtstellar3-12/+6
The register encodings weren't being defined correctly in the .td files, so they were all encoded as 0. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@164602 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-24R600: support for interpolation intrinsicststellar9-1/+307
Patch by Vincent Lejeune. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@164538 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-24R600: Handle loads from the constants address space.tstellar3-0/+19
Reading from constant memory is not supported yet, so constant reads use global memory. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@164537 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-24R600: Expand vector fadd and fmul on R600tstellar3-0/+33
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@164536 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-24R600: Add support for v4f32 stores on R600tstellar4-9/+36
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/R600/@164535 91177308-0d34-0410-b5e6-96231b3b80d8