AgeCommit message (Expand)AuthorFilesLines
2012-10-17R600: Organize pseudo instruction in R600Instructions.tdbackup-Oct18Tom Stellard1-27/+10
2012-10-17R600: Lower PRED_X to a native instruction prior to codegenTom Stellard9-50/+119
2012-10-17R600: Use native operands for R600_OP3 instructionsTom Stellard1-34/+64
2012-10-17R600: Use native operands for R600_2OP instructionsTom Stellard4-123/+79
2012-10-17R600: Use native operands for MOV_IMM_* instructionsTom Stellard4-23/+42
2012-10-17R600: Use native operands for the MOV InstructionTom Stellard7-47/+60
2012-10-17R600: Use native operands for R600_1OP instructionsTom Stellard8-128/+444
2012-10-17R600: Emit CONTINUE instructions correctlyTom Stellard1-3/+2
2012-10-17AMDGPU: Remove unused llvm.AMDGPU.ssg intrinsicTom Stellard2-8/+0
2012-10-16AMDGPU: Fix build after mergetstellar1-8/+0
2012-10-16Merge master branchtstellar381-4194/+18653
2012-10-15R600: use ceil intrinsic instead of llvm.AMDIL.round.posinftstellar2-4/+0
2012-10-15R600: use floor intrinsic instead of llvm.AMDIL.floortstellar5-5/+5
2012-10-15R600: use llvm fabs intrinsictstellar3-5/+3
2012-10-15R600: use llvm intrinsic for flog2tstellar3-3/+2
2012-10-15R600: add support for cos/sin intrinsictstellar4-14/+17
2012-10-15R600: add a pattern for fsqrttstellar1-0/+3
2012-10-15R600: Store channel index in the register's HWEncoding fieldtstellar8-1117/+31
2012-10-11AMDGPU: Fix lowering of UREMtstellar1-5/+4
2012-10-11AMDGPU: Fix build after merging of DataLayout changeststellar3-5/+5
2012-10-11Merge master branchtstellar602-8117/+12984
2012-10-10R600: Fix typo in SETGE_UINT patterntstellar1-1/+1
2012-10-09R600: Disable SI flow control again for nowtstellar1-1/+2
2012-10-09R600: Handle reversed true/false values in selectcctstellar2-6/+26
2012-10-09R600: Prefer lowering SELECT_CC to CND* instructions over SET* instructionststellar2-42/+66
2012-10-09R600: Fix lowering of fcmptstellar4-7/+55
2012-10-09R600: Add a pattern for: (selectcc i32, -1, i32, i32, SETGT)tstellar2-0/+28
2012-10-09R600: Add a comment explaining why we use TRUNC before FLT_TO_*INTtstellar1-0/+10
2012-10-09R600: Add store v4i32 testtstellar1-0/+9
2012-10-09R600: Add tests for a few vector operationststellar7-0/+106
2012-10-03SI: Mark the V_CMPX* instructions as having side effectststellar1-0/+32
2012-10-03R600: Handle more vector arithmetic instructionststellar1-0/+8
2012-10-03R600: Implement getSetCCResultType in R600TargetLowering clasststellar2-0/+8
2012-10-03R600: Add support for v4i32 global storeststellar1-0/+6
2012-10-03SI: Fix crash in unused register search in LowerFlowControl pasststellar1-4/+4
2012-10-03SI: S_WAITCNT has side effectststellar1-0/+2
2012-10-03SI: Set the section in the Asm Printer before emitting program infotstellar1-1/+1
2012-10-03SI: Fix bug in loops where iterators may be deletedtstellar2-2/+4
2012-10-03SI: Add sanity testtstellar1-0/+37
2012-10-02Merge master branchtstellar36-121/+423
2012-10-02R600: improve select_cc lowering to generate CND* more oftentstellar5-42/+110
2012-10-02R600: Fix instruction encoding for r600 family GPUststellar3-15/+15
2012-10-02Merge master branchtstellar237-2024/+11083
2012-10-02Merge TOTtstellar33-168/+699
2012-09-25R600: Fix typo in R600RegisterInfo.tdtstellar1-1/+1
2012-09-25AMDGPU: Fix register encodingtstellar3-12/+6
2012-09-24R600: support for interpolation intrinsicststellar9-1/+307
2012-09-24R600: Handle loads from the constants address space.tstellar3-0/+19
2012-09-24R600: Expand vector fadd and fmul on R600tstellar3-0/+33
2012-09-24R600: Add support for v4f32 stores on R600tstellar4-9/+36