diff options
Diffstat (limited to 'test')
107 files changed, 2494 insertions, 251 deletions
diff --git a/test/Assembler/2008-09-02-FunctionNotes2.ll b/test/Assembler/2008-09-02-FunctionNotes2.ll index 97351e2a571..47eb011343f 100644 --- a/test/Assembler/2008-09-02-FunctionNotes2.ll +++ b/test/Assembler/2008-09-02-FunctionNotes2.ll @@ -1,5 +1,5 @@ ; Test function notes -; RUN: not llvm-as %s -o /dev/null 2>&1 | grep "Attributes noinline alwaysinline are incompatible" +; RUN: not llvm-as %s -o /dev/null 2>&1 | grep "Attributes 'noinline and alwaysinline' are incompatible" define void @fn1() alwaysinline noinline { ret void } diff --git a/test/Bindings/Ocaml/ipo_opts.ml b/test/Bindings/Ocaml/ipo_opts.ml index 3a362319a73..d4537e4413f 100644 --- a/test/Bindings/Ocaml/ipo_opts.ml +++ b/test/Bindings/Ocaml/ipo_opts.ml @@ -43,10 +43,10 @@ let test_transforms () = ignore (build_ret (build_call fn [| |] "" b) b); end; - let td = TargetData.create (target_triple m) in + let td = DataLayout.create (target_triple m) in ignore (PassManager.create () - ++ TargetData.add td + ++ DataLayout.add td ++ add_argument_promotion ++ add_constant_merge ++ add_dead_arg_elimination @@ -63,7 +63,7 @@ let test_transforms () = ++ PassManager.run_module m ++ PassManager.dispose); - TargetData.dispose td + DataLayout.dispose td (*===-- Driver ------------------------------------------------------------===*) diff --git a/test/Bindings/Ocaml/scalar_opts.ml b/test/Bindings/Ocaml/scalar_opts.ml index 34a7a6a01bd..0760dad4ad0 100644 --- a/test/Bindings/Ocaml/scalar_opts.ml +++ b/test/Bindings/Ocaml/scalar_opts.ml @@ -38,10 +38,10 @@ let test_transforms () = let fn = define_function "fn" fty m in ignore (build_ret_void (builder_at_end context (entry_block fn))); - let td = TargetData.create (target_triple m) in + let td = DataLayout.create (target_triple m) in ignore (PassManager.create_function m - ++ TargetData.add td + ++ DataLayout.add td ++ add_verifier ++ add_constant_propagation ++ add_sccp @@ -78,7 +78,7 @@ let test_transforms () = ++ PassManager.finalize ++ PassManager.dispose); - TargetData.dispose td + DataLayout.dispose td (*===-- Driver ------------------------------------------------------------===*) diff --git a/test/Bindings/Ocaml/target.ml b/test/Bindings/Ocaml/target.ml index 1b6b71e2759..7a35a790ab3 100644 --- a/test/Bindings/Ocaml/target.ml +++ b/test/Bindings/Ocaml/target.ml @@ -33,10 +33,10 @@ let m = create_module context filename (*===-- Target Data -------------------------------------------------------===*) let test_target_data () = - let td = TargetData.create (target_triple m) in + let td = DataLayout.create (target_triple m) in let sty = struct_type context [| i32_type; i64_type |] in - ignore (TargetData.as_string td); + ignore (DataLayout.as_string td); ignore (byte_order td); ignore (pointer_size td); ignore (intptr_type td); @@ -49,7 +49,7 @@ let test_target_data () = ignore (element_at_offset td sty (Int64.of_int 1)); ignore (offset_of_element td sty 1); - TargetData.dispose td + DataLayout.dispose td (*===-- Driver ------------------------------------------------------------===*) diff --git a/test/CMakeLists.txt b/test/CMakeLists.txt index b9b223713f2..bc226ca2283 100644 --- a/test/CMakeLists.txt +++ b/test/CMakeLists.txt @@ -7,6 +7,11 @@ configure_lit_site_cfg( ${CMAKE_CURRENT_BINARY_DIR}/Unit/lit.site.cfg ) +# Don't include check-llvm into check-all without LLVM_BUILD_TOOLS. +if(NOT LLVM_BUILD_TOOLS) + set(EXCLUDE_FROM_ALL ON) +endif() + add_lit_testsuite(check-llvm "Running the LLVM regression tests" ${CMAKE_CURRENT_BINARY_DIR} PARAMS llvm_site_config=${CMAKE_CURRENT_BINARY_DIR}/lit.site.cfg diff --git a/test/CodeGen/ARM/2012-10-04-FixedFrame-vs-byval.ll b/test/CodeGen/ARM/2012-10-04-FixedFrame-vs-byval.ll new file mode 100644 index 00000000000..478048d0960 --- /dev/null +++ b/test/CodeGen/ARM/2012-10-04-FixedFrame-vs-byval.ll @@ -0,0 +1,19 @@ +; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi | FileCheck %s + +@.str = private unnamed_addr constant [12 x i8] c"val.a = %f\0A\00" +%struct_t = type { double, double, double } +@static_val = constant %struct_t { double 1.0, double 2.0, double 3.0 } + +declare i32 @printf(i8*, ...) + +; CHECK: test_byval_usage_scheduling: +; CHECK: str r3, [sp, #12] +; CHECK: str r2, [sp, #8] +; CHECK: vldr d16, [sp, #8] +define void @test_byval_usage_scheduling(i32 %n1, i32 %n2, %struct_t* byval %val) nounwind { +entry: + %a = getelementptr inbounds %struct_t* %val, i32 0, i32 0 + %0 = load double* %a + %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([12 x i8]* @.str, i32 0, i32 0), double %0) + ret void +} diff --git a/test/CodeGen/ARM/2012-10-04-LDRB_POST_IMM-Crash.ll b/test/CodeGen/ARM/2012-10-04-LDRB_POST_IMM-Crash.ll new file mode 100644 index 00000000000..6eb8fcb2db9 --- /dev/null +++ b/test/CodeGen/ARM/2012-10-04-LDRB_POST_IMM-Crash.ll @@ -0,0 +1,23 @@ +; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi | FileCheck %s +; Check that LDRB_POST_IMM instruction emitted properly. + +%my_struct_t = type { double, double, double } +@main.val = private unnamed_addr constant %my_struct_t { double 1.0, double 2.0, double 3.0 }, align 8 + +declare void @f(i32 %n1, %my_struct_t* byval %val); + + +; CHECK: main: +define i32 @main() nounwind { +entry: + %val = alloca %my_struct_t, align 8 + %0 = bitcast %my_struct_t* %val to i8* + +; CHECK: ldrb {{(r[0-9]+)}}, {{(\[r[0-9]+\])}}, #1 + call void @llvm.memcpy.p0i8.p0i8.i32(i8* %0, i8* bitcast (%my_struct_t* @main.val to i8*), i32 24, i32 8, i1 false) + + call void @f(i32 555, %my_struct_t* byval %val) + ret i32 0 +} + +declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, i1) nounwind diff --git a/test/CodeGen/ARM/coalesce-subregs.ll b/test/CodeGen/ARM/coalesce-subregs.ll index 8d7ded5be06..6e1f17dced1 100644 --- a/test/CodeGen/ARM/coalesce-subregs.ll +++ b/test/CodeGen/ARM/coalesce-subregs.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mcpu=cortex-a9 -new-coalescer | FileCheck %s +; RUN: llc < %s -mcpu=cortex-a9 -verify-coalescing | FileCheck %s target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32" target triple = "thumbv7-apple-ios0.0.0" @@ -189,3 +189,28 @@ if.end: ; preds = %entry, %if.then declare <4 x float> @llvm.arm.neon.vld1.v4f32(i8*, i32) nounwind readonly declare void @llvm.arm.neon.vst1.v4f32(i8*, <4 x float>, i32) nounwind + +; CHECK: pr13999 +define void @pr13999() nounwind readonly { +entry: + br i1 true, label %outer_loop, label %loop.end + +outer_loop: + %d = phi double [ 0.0, %entry ], [ %add, %after_inner_loop ] + %0 = insertelement <2 x double> <double 0.0, double 0.0>, double %d, i32 0 + br i1 undef, label %after_inner_loop, label %inner_loop + +inner_loop: + br i1 true, label %after_inner_loop, label %inner_loop + +after_inner_loop: + %1 = phi <2 x double> [ %0, %outer_loop ], [ <double 0.0, double 0.0>, +%inner_loop ] + %2 = extractelement <2 x double> %1, i32 1 + %add = fadd double 1.0, %2 + br i1 false, label %loop.end, label %outer_loop + +loop.end: + %d.end = phi double [ 0.0, %entry ], [ %add, %after_inner_loop ] + ret void +} diff --git a/test/CodeGen/ARM/darwin-section-order.ll b/test/CodeGen/ARM/darwin-section-order.ll new file mode 100644 index 00000000000..701028c0a53 --- /dev/null +++ b/test/CodeGen/ARM/darwin-section-order.ll @@ -0,0 +1,21 @@ +; RUN: llc < %s -mtriple=armv7-apple-darwin | FileCheck %s + +; CHECK: .section __TEXT,__text,regular,pure_instructions +; CHECK: .section __TEXT,myprecious +; CHECK: .section __TEXT,__textcoal_nt,coalesced,pure_instructions +; CHECK: .section __TEXT,__const_coal,coalesced +; CHECK: .section __TEXT,__picsymbolstub4,symbol_stubs,none,16 +; CHECK: .section __TEXT,__StaticInit,regular,pure_instructions + + +define void @normal() nounwind readnone { +; CHECK: .section __TEXT,__text,regular,pure_instructions +; CHECK: _normal: + ret void +} + +define void @special() nounwind readnone section "__TEXT,myprecious" { +; CHECK: .section __TEXT,myprecious +; CHECK: _special: + ret void +} diff --git a/test/CodeGen/ARM/deps-fix.ll b/test/CodeGen/ARM/deps-fix.ll new file mode 100644 index 00000000000..288697a4dc7 --- /dev/null +++ b/test/CodeGen/ARM/deps-fix.ll @@ -0,0 +1,22 @@ +; RUN: llc < %s -march=arm -mcpu=cortex-a9 -mattr=+neon,+neonfp -float-abi=hard -mtriple armv7-linux-gnueabi | FileCheck %s + +;; This test checks that the ExecutionDepsFix pass performs the domain changes +;; even when some dependencies are propagated through implicit definitions. + +; CHECK: fun_a +define <4 x float> @fun_a(<4 x float> %in, <4 x float> %x, float %y) nounwind { +; CHECK: vext +; CHECK: vext +; CHECK: vadd.f32 + %1 = insertelement <4 x float> %in, float %y, i32 0 + %2 = fadd <4 x float> %1, %x + ret <4 x float> %2 +} +; CHECK: fun_b +define <4 x i32> @fun_b(<4 x i32> %in, <4 x i32> %x, i32 %y) nounwind { +; CHECK: vmov.32 +; CHECK: vadd.i32 + %1 = insertelement <4 x i32> %in, i32 %y, i32 0 + %2 = add <4 x i32> %1, %x + ret <4 x i32> %2 +} diff --git a/test/CodeGen/CellSPU/icmp16.ll b/test/CodeGen/CellSPU/icmp16.ll index 2f9b091faea..853ae1db160 100644 --- a/test/CodeGen/CellSPU/icmp16.ll +++ b/test/CodeGen/CellSPU/icmp16.ll @@ -534,7 +534,7 @@ entry: define i16 @icmp_slt_immed04_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind { ; CHECK: icmp_slt_immed04_i16: ; CHECK: lr -; CHECK-NETX: bi +; CHECK-NEXT: bi entry: %A = icmp slt i16 %arg1, 32768 @@ -559,7 +559,7 @@ define i1 @icmp_sle_setcc_i16(i16 %arg1, i16 %arg2, i16 %val1, i16 %val2) nounwi ; CHECK: ilhu ; CHECK: xorhi ; CHECK: iohl -; CHECK-NETX: bi +; CHECK: bi entry: %A = icmp sle i16 %arg1, %arg2 diff --git a/test/CodeGen/Mips/mul.ll b/test/CodeGen/Mips/mul.ll new file mode 100644 index 00000000000..4ce801b1c9f --- /dev/null +++ b/test/CodeGen/Mips/mul.ll @@ -0,0 +1,17 @@ +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 + +@iiii = global i32 5, align 4 +@jjjj = global i32 -6, align 4 +@kkkk = common global i32 0, align 4 + +define void @test() nounwind { +entry: + %0 = load i32* @iiii, align 4 + %1 = load i32* @jjjj, align 4 + %mul = mul nsw i32 %1, %0 +; 16: mult ${{[0-9]+}}, ${{[0-9]+}} +; 16: mflo ${{[0-9]+}} + + store i32 %mul, i32* @kkkk, align 4 + ret void +} diff --git a/test/CodeGen/Mips/mulll.ll b/test/CodeGen/Mips/mulll.ll new file mode 100644 index 00000000000..e37b9197df8 --- /dev/null +++ b/test/CodeGen/Mips/mulll.ll @@ -0,0 +1,21 @@ +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 + +@iiii = global i64 5, align 8 +@jjjj = global i64 -6, align 8 +@kkkk = common global i64 0, align 8 + +define void @test() nounwind { +entry: + %0 = load i64* @iiii, align 8 + %1 = load i64* @jjjj, align 8 + %mul = mul nsw i64 %1, %0 + store i64 %mul, i64* @kkkk, align 8 +; 16: multu ${{[0-9]+}}, ${{[0-9]+}} +; 16: mfhi ${{[0-9]+}} +; 16: mult ${{[0-9]+}}, ${{[0-9]+}} +; 16: mflo ${{[0-9]+}} +; 16: mult ${{[0-9]+}}, ${{[0-9]+}} +; 16: mflo ${{[0-9]+}} + + ret void +} diff --git a/test/CodeGen/Mips/mulull.ll b/test/CodeGen/Mips/mulull.ll new file mode 100644 index 00000000000..4d23c693184 --- /dev/null +++ b/test/CodeGen/Mips/mulull.ll @@ -0,0 +1,21 @@ +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 + +@iiii = global i64 5, align 8 +@jjjj = global i64 6, align 8 +@kkkk = common global i64 0, align 8 +@.str = private unnamed_addr constant [20 x i8] c"%lld * %lld = %lld\0A\00", align 1 + +define void @test() nounwind { +entry: + %0 = load i64* @iiii, align 8 + %1 = load i64* @jjjj, align 8 + %mul = mul nsw i64 %1, %0 + store i64 %mul, i64* @kkkk, align 8 +; 16: multu ${{[0-9]+}}, ${{[0-9]+}} +; 16: mfhi ${{[0-9]+}} +; 16: mult ${{[0-9]+}}, ${{[0-9]+}} +; 16: mflo ${{[0-9]+}} +; 16: mult ${{[0-9]+}}, ${{[0-9]+}} +; 16: mflo ${{[0-9]+}} + ret void +} diff --git a/test/CodeGen/Mips/return-vector.ll b/test/CodeGen/Mips/return-vector.ll new file mode 100644 index 00000000000..739c43c68a5 --- /dev/null +++ b/test/CodeGen/Mips/return-vector.ll @@ -0,0 +1,244 @@ +; RUN: llc -march=mipsel < %s | FileCheck %s + + +; Check that function accesses vector return value from stack in cases when +; vector can't be returned in registers. Also check that caller passes in +; register $4 stack address where the vector should be placed. + + +declare <8 x i32> @i8(...) +declare <4 x float> @f4(...) +declare <4 x double> @d4(...) + +define i32 @call_i8() { +entry: + %call = call <8 x i32> (...)* @i8() + %v0 = extractelement <8 x i32> %call, i32 0 + %v1 = extractelement <8 x i32> %call, i32 1 + %v2 = extractelement <8 x i32> %call, i32 2 + %v3 = extractelement <8 x i32> %call, i32 3 + %v4 = extractelement <8 x i32> %call, i32 4 + %v5 = extractelement <8 x i32> %call, i32 5 + %v6 = extractelement <8 x i32> %call, i32 6 + %v7 = extractelement <8 x i32> %call, i32 7 + %add1 = add i32 %v0, %v1 + %add2 = add i32 %v2, %v3 + %add3 = add i32 %v4, %v5 + %add4 = add i32 %v6, %v7 + %add5 = add i32 %add1, %add2 + %add6 = add i32 %add3, %add4 + %add7 = add i32 %add5, %add6 + ret i32 %add7 + +; CHECK: call_i8: +; CHECK: call16(i8) +; CHECK: addiu $4, $sp, 32 +; CHECK: lw $[[R0:[a-z0-9]+]], 60($sp) +; CHECK: lw $[[R1:[a-z0-9]+]], 56($sp) +; CHECK: lw $[[R2:[a-z0-9]+]], 52($sp) +; CHECK: lw $[[R3:[a-z0-9]+]], 48($sp) +; CHECK: lw $[[R4:[a-z0-9]+]], 44($sp) +; CHECK: lw $[[R5:[a-z0-9]+]], 40($sp) +; CHECK: lw $[[R6:[a-z0-9]+]], 36($sp) +; CHECK: lw $[[R7:[a-z0-9]+]], 32($sp) +} + + +define float @call_f4() { +entry: + %call = call <4 x float> (...)* @f4() + %v0 = extractelement <4 x float> %call, i32 0 + %v1 = extractelement <4 x float> %call, i32 1 + %v2 = extractelement <4 x float> %call, i32 2 + %v3 = extractelement <4 x float> %call, i32 3 + %add1 = fadd float %v0, %v1 + %add2 = fadd float %v2, %v3 + %add3 = fadd float %add1, %add2 + ret float %add3 + +; CHECK: call_f4: +; CHECK: call16(f4) +; CHECK: addiu $4, $sp, 16 +; CHECK: lwc1 $[[R0:[a-z0-9]+]], 28($sp) +; CHECK: lwc1 $[[R1:[a-z0-9]+]], 24($sp) +; CHECK: lwc1 $[[R3:[a-z0-9]+]], 20($sp) +; CHECK: lwc1 $[[R4:[a-z0-9]+]], 16($sp) +} + + +define double @call_d4() { +entry: + %call = call <4 x double> (...)* @d4() + %v0 = extractelement <4 x double> %call, i32 0 + %v1 = extractelement <4 x double> %call, i32 1 + %v2 = extractelement <4 x double> %call, i32 2 + %v3 = extractelement <4 x double> %call, i32 3 + %add1 = fadd double %v0, %v1 + %add2 = fadd double %v2, %v3 + %add3 = fadd double %add1, %add2 + ret double %add3 + +; CHECK: call_d4: +; CHECK: call16(d4) +; CHECK: addiu $4, $sp, 32 +; CHECK: ldc1 $[[R0:[a-z0-9]+]], 56($sp) +; CHECK: ldc1 $[[R1:[a-z0-9]+]], 48($sp) +; CHECK: ldc1 $[[R3:[a-z0-9]+]], 40($sp) +; CHECK: ldc1 $[[R4:[a-z0-9]+]], 32($sp) +} + + + +; Check that function accesses vector return value from registers in cases when +; vector can be returned in registers + + +declare <4 x i32> @i4(...) +declare <2 x float> @f2(...) +declare <2 x double> @d2(...) + +define i32 @call_i4() { +entry: + %call = call <4 x i32> (...)* @i4() + %v0 = extractelement <4 x i32> %call, i32 0 + %v1 = extractelement <4 x i32> %call, i32 1 + %v2 = extractelement <4 x i32> %call, i32 2 + %v3 = extractelement <4 x i32> %call, i32 3 + %add1 = add i32 %v0, %v1 + %add2 = add i32 %v2, %v3 + %add3 = add i32 %add1, %add2 + ret i32 %add3 + +; CHECK: call_i4: +; CHECK: call16(i4) +; CHECK-NOT: lw +; CHECK: addu $[[R2:[a-z0-9]+]], $[[R0:[a-z0-9]+]], $[[R1:[a-z0-9]+]] +; CHECK: addu $[[R5:[a-z0-9]+]], $[[R3:[a-z0-9]+]], $[[R4:[a-z0-9]+]] +; CHECK: addu $[[R6:[a-z0-9]+]], $[[R5]], $[[R2]] +} + + +define float @call_f2() { +entry: + %call = call <2 x float> (...)* @f2() + %v0 = extractelement <2 x float> %call, i32 0 + %v1 = extractelement <2 x float> %call, i32 1 + %add1 = fadd float %v0, %v1 + ret float %add1 + +; CHECK: call_f2: +; CHECK: call16(f2) +; CHECK-NOT: lwc1 +; CHECK: add.s $[[R2:[a-z0-9]+]], $[[R0:[a-z0-9]+]], $[[R1:[a-z0-9]+]] +} + + +define double @call_d2() { +entry: + %call = call <2 x double> (...)* @d2() + %v0 = extractelement <2 x double> %call, i32 0 + %v1 = extractelement <2 x double> %call, i32 1 + %add1 = fadd double %v0, %v1 + ret double %add1 + +; CHECK: call_d2: +; CHECK: call16(d2) +; CHECK-NOT: ldc1 +; CHECK: add.d $[[R2:[a-z0-9]+]], $[[R0:[a-z0-9]+]], $[[R1:[a-z0-9]+]] +} + + + +; Check that function returns vector on stack in cases when vector can't be +; returned in registers. Also check that vector is placed on stack starting +; from the address in register $4. + + +define <8 x i32> @return_i8() { +entry: + ret <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> + +; CHECK: return_i8: +; CHECK: sw $[[R0:[a-z0-9]+]], 28($4) +; CHECK: sw $[[R1:[a-z0-9]+]], 24($4) +; CHECK: sw $[[R2:[a-z0-9]+]], 20($4) +; CHECK: sw $[[R3:[a-z0-9]+]], 16($4) +; CHECK: sw $[[R4:[a-z0-9]+]], 12($4) +; CHECK: sw $[[R5:[a-z0-9]+]], 8($4) +; CHECK: sw $[[R6:[a-z0-9]+]], 4($4) +; CHECK: sw $[[R7:[a-z0-9]+]], 0($4) +} + + +define <4 x float> @return_f4(float %a, float %b, float %c, float %d) { +entry: + %vecins1 = insertelement <4 x float> undef, float %a, i32 0 + %vecins2 = insertelement <4 x float> %vecins1, float %b, i32 1 + %vecins3 = insertelement <4 x float> %vecins2, float %c, i32 2 + %vecins4 = insertelement <4 x float> %vecins3, float %d, i32 3 + ret <4 x float> %vecins4 + +; CHECK: return_f4: +; CHECK: lwc1 $[[R0:[a-z0-9]+]], 16($sp) +; CHECK: swc1 $[[R0]], 12($4) +; CHECK: sw $7, 8($4) +; CHECK: sw $6, 4($4) +; CHECK: sw $5, 0($4) +} + + +define <4 x double> @return_d4(double %a, double %b, double %c, double %d) { +entry: + %vecins1 = insertelement <4 x double> undef, double %a, i32 0 + %vecins2 = insertelement <4 x double> %vecins1, double %b, i32 1 + %vecins3 = insertelement <4 x double> %vecins2, double %c, i32 2 + %vecins4 = insertelement <4 x double> %vecins3, double %d, i32 3 + ret <4 x double> %vecins4 + +; CHECK: return_d4: +; CHECK: sdc1 $[[R0:[a-z0-9]+]], 24($4) +; CHECK: sdc1 $[[R1:[a-z0-9]+]], 16($4) +; CHECK: sdc1 $[[R2:[a-z0-9]+]], 8($4) +; CHECK: sdc1 $[[R3:[a-z0-9]+]], 0($4) +} + + + +; Check that function returns vector in registers in cases when vector can be +; returned in registers. + + +define <4 x i32> @return_i4() { +entry: + ret <4 x i32> <i32 0, i32 1, i32 2, i32 3> + +; CHECK: return_i4: +; CHECK: addiu $2, $zero, 0 +; CHECK: addiu $3, $zero, 1 +; CHECK: addiu $4, $zero, 2 +; CHECK: addiu $5, $zero, 3 +} + + +define <2 x float> @return_f2(float %a, float %b) { +entry: + %vecins1 = insertelement <2 x float> undef, float %a, i32 0 + %vecins2 = insertelement <2 x float> %vecins1, float %b, i32 1 + ret <2 x float> %vecins2 + +; CHECK: return_f2: +; CHECK: mov.s $f0, $f12 +; CHECK: mov.s $f2, $f14 +} + + +define <2 x double> @return_d2(double %a, double %b) { +entry: + %vecins1 = insertelement <2 x double> undef, double %a, i32 0 + %vecins2 = insertelement <2 x double> %vecins1, double %b, i32 1 + ret <2 x double> %vecins2 + +; CHECK: return_d2: +; CHECK: mov.d $f0, $f12 +; CHECK: mov.d $f2, $f14 +} diff --git a/test/CodeGen/PowerPC/ppc64-toc.ll b/test/CodeGen/PowerPC/ppc64-toc.ll index b992ab1ad33..a29bdcb2503 100644 --- a/test/CodeGen/PowerPC/ppc64-toc.ll +++ b/test/CodeGen/PowerPC/ppc64-toc.ll @@ -1,68 +1,68 @@ -; RUN: llc < %s | FileCheck %s
-target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
-target triple = "powerpc64-unknown-linux-gnu"
-
-@double_array = global [32 x double] zeroinitializer, align 8
-@number64 = global i64 10, align 8
-@internal_static_var.x = internal unnamed_addr global i64 0, align 8
-
-define i64 @access_int64(i64 %a) nounwind readonly {
-entry:
-; CHECK: access_int64:
-; CHECK-NEXT: .align 3
-; CHECK-NEXT: .quad .L.access_int64
-; CHECK-NEXT: .quad .TOC.@tocbase
-; CHECK-NEXT: .quad 0
-; CHECK-NEXT: .text
- %0 = load i64* @number64, align 8
-; CHECK: ld {{[0-9]+}}, .LC{{[0-9]+}}@toc(2)
- %cmp = icmp eq i64 %0, %a
- %conv1 = zext i1 %cmp to i64
- ret i64 %conv1
-}
-
-define i64 @internal_static_var(i64 %a) nounwind {
-entry:
-; CHECK: internal_static_var:
-; CHECK: ld {{[0-9]+}}, .LC{{[0-9]+}}@toc(2)
- %0 = load i64* @internal_static_var.x, align 8
- %cmp = icmp eq i64 %0, %a
- %conv1 = zext i1 %cmp to i64
- ret i64 %conv1
-}
-
-define i32 @access_double(double %a) nounwind readnone {
-entry:
-; CHECK: access_double:
-; CHECK: ld {{[0-9]+}}, .LC{{[0-9]+}}@toc(2)
- %cmp = fcmp oeq double %a, 2.000000e+00
- %conv = zext i1 %cmp to i32
- ret i32 %conv
-}
-
-
-define i32 @access_double_array(double %a, i32 %i) nounwind readonly {
-entry:
-; CHECK: access_double_array:
- %idxprom = sext i32 %i to i64
- %arrayidx = getelementptr inbounds [32 x double]* @double_array, i64 0, i64 %idxprom
- %0 = load double* %arrayidx, align 8
-; CHECK: ld {{[0-9]+}}, .LC{{[0-9]+}}@toc(2)
- %cmp = fcmp oeq double %0, %a
- %conv = zext i1 %cmp to i32
- ret i32 %conv
-}
-
-; Check the creation of 4 .tc entries:
-; * int64_t global 'number64'
-; * double constant 2.0
-; * double array 'double_array'
-; * static int64_t 'x' accessed within '@internal_static_var'
-; CHECK: .LC{{[0-9]+}}:
-; CHECK-NEXT: .tc {{[\._a-zA-Z0-9]+}}[TC],{{[\._a-zA-Z0-9]+}}
-; CHECK-NEXT: .LC{{[0-9]+}}:
-; CHECK-NEXT: .tc {{[\._a-zA-Z0-9]+}}[TC],{{[\._a-zA-Z0-9]+}}
-; CHECK-NEXT: .LC{{[0-9]+}}:
-; CHECK-NEXT: .tc {{[\._a-zA-Z0-9]+}}[TC],{{[\._a-zA-Z0-9]+}}
-; CHECK-NEXT: .LC{{[0-9]+}}:
-; CHECK-NEXT: .tc {{[\._a-zA-Z0-9]+}}[TC],{{[\._a-zA-Z0-9]+}}
+; RUN: llc < %s | FileCheck %s +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +@double_array = global [32 x double] zeroinitializer, align 8 +@number64 = global i64 10, align 8 +@internal_static_var.x = internal unnamed_addr global i64 0, align 8 + +define i64 @access_int64(i64 %a) nounwind readonly { +entry: +; CHECK: access_int64: +; CHECK-NEXT: .align 3 +; CHECK-NEXT: .quad .L.access_int64 +; CHECK-NEXT: .quad .TOC.@tocbase +; CHECK-NEXT: .quad 0 +; CHECK-NEXT: .text + %0 = load i64* @number64, align 8 +; CHECK: ld {{[0-9]+}}, .LC{{[0-9]+}}@toc(2) + %cmp = icmp eq i64 %0, %a + %conv1 = zext i1 %cmp to i64 + ret i64 %conv1 +} + +define i64 @internal_static_var(i64 %a) nounwind { +entry: +; CHECK: internal_static_var: +; CHECK: ld {{[0-9]+}}, .LC{{[0-9]+}}@toc(2) + %0 = load i64* @internal_static_var.x, align 8 + %cmp = icmp eq i64 %0, %a + %conv1 = zext i1 %cmp to i64 + ret i64 %conv1 +} + +define i32 @access_double(double %a) nounwind readnone { +entry: +; CHECK: access_double: +; CHECK: ld {{[0-9]+}}, .LC{{[0-9]+}}@toc(2) + %cmp = fcmp oeq double %a, 2.000000e+00 + %conv = zext i1 %cmp to i32 + ret i32 %conv +} + + +define i32 @access_double_array(double %a, i32 %i) nounwind readonly { +entry: +; CHECK: access_double_array: + %idxprom = sext i32 %i to i64 + %arrayidx = getelementptr inbounds [32 x double]* @double_array, i64 0, i64 %idxprom + %0 = load double* %arrayidx, align 8 +; CHECK: ld {{[0-9]+}}, .LC{{[0-9]+}}@toc(2) + %cmp = fcmp oeq double %0, %a + %conv = zext i1 %cmp to i32 + ret i32 %conv +} + +; Check the creation of 4 .tc entries: +; * int64_t global 'number64' +; * double constant 2.0 +; * double array 'double_array' +; * static int64_t 'x' accessed within '@internal_static_var' +; CHECK: .LC{{[0-9]+}}: +; CHECK-NEXT: .tc {{[\._a-zA-Z0-9]+}}[TC],{{[\._a-zA-Z0-9]+}} +; CHECK-NEXT: .LC{{[0-9]+}}: +; CHECK-NEXT: .tc {{[\._a-zA-Z0-9]+}}[TC],{{[\._a-zA-Z0-9]+}} +; CHECK-NEXT: .LC{{[0-9]+}}: +; CHECK-NEXT: .tc {{[\._a-zA-Z0-9]+}}[TC],{{[\._a-zA-Z0-9]+}} +; CHECK-NEXT: .LC{{[0-9]+}}: +; CHECK-NEXT: .tc {{[\._a-zA-Z0-9]+}}[TC],{{[\._a-zA-Z0-9]+}} diff --git a/test/CodeGen/PowerPC/vec_cmp.ll b/test/CodeGen/PowerPC/vec_cmp.ll new file mode 100644 index 00000000000..b2b59db8f18 --- /dev/null +++ b/test/CodeGen/PowerPC/vec_cmp.ll @@ -0,0 +1,191 @@ +; RUN: llc -mattr=+altivec < %s | FileCheck %s + +; Check vector comparisons using altivec. + + +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +define <2 x i8> @v2si8_cmp(<2 x i8> %x, <2 x i8> %y) nounwind readnone { + %cmp = icmp eq <2 x i8> %x, %y + %sext = sext <2 x i1> %cmp to <2 x i8> + ret <2 x i8> %sext +} +; CHECK: v2si8_cmp: +; CHECK: vcmpequb {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} + + +define <4 x i8> @v4si8_cmp(<4 x i8> %x, <4 x i8> %y) nounwind readnone { + %cmp = icmp eq <4 x i8> %x, %y + %sext = sext <4 x i1> %cmp to <4 x i8> + ret <4 x i8> %sext +} +; CHECK: v4si8_cmp: +; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} + + +define <8 x i8> @v8si8_cmp(<8 x i8> %x, <8 x i8> %y) nounwind readnone { + %cmp = icmp eq <8 x i8> %x, %y + %sext = sext <8 x i1> %cmp to <8 x i8> + ret <8 x i8> %sext +} +; CHECK: v8si8_cmp: +; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} + + +define <16 x i8> @v16si8_cmp(<16 x i8> %x, <16 x i8> %y) nounwind readnone { + %cmp = icmp eq <16 x i8> %x, %y + %sext = sext <16 x i1> %cmp to <16 x i8> + ret <16 x i8> %sext +} +; CHECK: v16si8_cmp: +; CHECK: vcmpequb {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} + + +define <32 x i8> @v32si8_cmp(<32 x i8> %x, <32 x i8> %y) nounwind readnone { + %cmp = icmp eq <32 x i8> %x, %y + %sext = sext <32 x i1> %cmp to <32 x i8> + ret <32 x i8> %sext +} +; CHECK: v32si8_cmp: +; CHECK: vcmpequb {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} +; CHECK: vcmpequb {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} + + +define <2 x i16> @v2si16_cmp(<2 x i16> %x, <2 x i16> %y) nounwind readnone { + %cmp = icmp eq <2 x i16> %x, %y + %sext = sext <2 x i1> %cmp to <2 x i16> + ret <2 x i16> %sext +} +; CHECK: v2si16_cmp: +; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} + + +define <4 x i16> @v4si16_cmp(<4 x i16> %x, <4 x i16> %y) nounwind readnone { + %cmp = icmp eq <4 x i16> %x, %y + %sext = sext <4 x i1> %cmp to <4 x i16> + ret <4 x i16> %sext +} +; CHECK: v4si16_cmp: +; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} + + +define <8 x i16> @v8si16_cmp(<8 x i16> %x, <8 x i16> %y) nounwind readnone { + %cmp = icmp eq <8 x i16> %x, %y + %sext = sext <8 x i1> %cmp to <8 x i16> + ret <8 x i16> %sext +} +; CHECK: v8si16_cmp: +; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} + + +define <16 x i16> @v16si16_cmp(<16 x i16> %x, <16 x i16> %y) nounwind readnone { + %cmp = icmp eq <16 x i16> %x, %y + %sext = sext <16 x i1> %cmp to <16 x i16> + ret <16 x i16> %sext +} +; CHECK: v16si16_cmp: +; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} +; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} + + +define <32 x i16> @v32si16_cmp(<32 x i16> %x, <32 x i16> %y) nounwind readnone { + %cmp = icmp eq <32 x i16> %x, %y + %sext = sext <32 x i1> %cmp to <32 x i16> + ret <32 x i16> %sext +} +; CHECK: v32si16_cmp: +; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} +; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} +; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} +; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} + + +define <2 x i32> @v2si32_cmp(<2 x i32> %x, <2 x i32> %y) nounwind readnone { + %cmp = icmp eq <2 x i32> %x, %y + %sext = sext <2 x i1> %cmp to <2 x i32> + ret <2 x i32> %sext +} +; CHECK: v2si32_cmp: +; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} + + +define <4 x i32> @v4si32_cmp(<4 x i32> %x, <4 x i32> %y) nounwind readnone { + %cmp = icmp eq <4 x i32> %x, %y + %sext = sext <4 x i1> %cmp to <4 x i32> + ret <4 x i32> %sext +} +; CHECK: v4si32_cmp: +; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} + + +define <8 x i32> @v8si32_cmp(<8 x i32> %x, <8 x i32> %y) nounwind readnone { + %cmp = icmp eq <8 x i32> %x, %y + %sext = sext <8 x i1> %cmp to <8 x i32> + ret <8 x i32> %sext +} +; CHECK: v8si32_cmp: +; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} +; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} + + +define <16 x i32> @v16si32_cmp(<16 x i32> %x, <16 x i32> %y) nounwind readnone { + %cmp = icmp eq <16 x i32> %x, %y + %sext = sext <16 x i1> %cmp to <16 x i32> + ret <16 x i32> %sext +} +; CHECK: v16si32_cmp: +; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} +; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} +; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} +; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} + + +define <32 x i32> @v32si32_cmp(<32 x i32> %x, <32 x i32> %y) nounwind readnone { + %cmp = icmp eq <32 x i32> %x, %y + %sext = sext <32 x i1> %cmp to <32 x i32> + ret <32 x i32> %sext +} +; CHECK: v32si32_cmp: +; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} +; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} +; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} +; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} +; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} +; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} +; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} +; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} + + +define <2 x float> @v2f32_cmp(<2 x float> %x, <2 x float> %y) nounwind readnone { +entry: + %cmp = fcmp oeq <2 x float> %x, %y + %sext = sext <2 x i1> %cmp to <2 x i32> + %0 = bitcast <2 x i32> %sext to <2 x float> + ret <2 x float> %0 +} +; CHECK: v2f32_cmp: +; CHECK: vcmpeqfp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} + + +define <4 x float> @v4f32_cmp(<4 x float> %x, <4 x float> %y) nounwind readnone { +entry: + %cmp = fcmp oeq <4 x float> %x, %y + %sext = sext <4 x i1> %cmp to <4 x i32> + %0 = bitcast <4 x i32> %sext to <4 x float> + ret <4 x float> %0 +} +; CHECK: v4f32_cmp: +; CHECK: vcmpeqfp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} + + +define <8 x float> @v8f32_cmp(<8 x float> %x, <8 x float> %y) nounwind readnone { +entry: + %cmp = fcmp oeq <8 x float> %x, %y + %sext = sext <8 x i1> %cmp to <8 x i32> + %0 = bitcast <8 x i32> %sext to <8 x float> + ret <8 x float> %0 +} +; CHECK: v8f32_cmp: +; CHECK: vcmpeqfp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} +; CHECK: vcmpeqfp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} diff --git a/test/CodeGen/PowerPC/vec_conv.ll b/test/CodeGen/PowerPC/vec_conv.ll new file mode 100644 index 00000000000..a475e9499df --- /dev/null +++ b/test/CodeGen/PowerPC/vec_conv.ll @@ -0,0 +1,57 @@ +; RUN: llc -mattr=+altivec < %s | FileCheck %s + +; Check vector float/int conversion using altivec. + +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +@cte_float = global <4 x float> <float 6.5e+00, float 6.5e+00, float 6.5e+00, float 6.5e+00>, align 16 +@cte_int = global <4 x i32> <i32 6, i32 6, i32 6, i32 6>, align 16 + + +define void @v4f32_to_v4i32(<4 x float> %x, <4 x i32>* nocapture %y) nounwind { +entry: + %0 = load <4 x float>* @cte_float, align 16 + %mul = fmul <4 x float> %0, %x + %1 = fptosi <4 x float> %mul to <4 x i32> + store <4 x i32> %1, <4 x i32>* %y, align 16 + ret void +} +;CHECK: v4f32_to_v4i32: +;CHECK: vctsxs {{[0-9]+}}, {{[0-9]+}}, 0 + + +define void @v4f32_to_v4u32(<4 x float> %x, <4 x i32>* nocapture %y) nounwind { +entry: + %0 = load <4 x float>* @cte_float, align 16 + %mul = fmul <4 x float> %0, %x + %1 = fptoui <4 x float> %mul to <4 x i32> + store <4 x i32> %1, <4 x i32>* %y, align 16 + ret void +} +;CHECK: v4f32_to_v4u32: +;CHECK: vctuxs {{[0-9]+}}, {{[0-9]+}}, 0 + + +define void @v4i32_to_v4f32(<4 x i32> %x, <4 x float>* nocapture %y) nounwind { +entry: + %0 = load <4 x i32>* @cte_int, align 16 + %mul = mul <4 x i32> %0, %x + %1 = sitofp <4 x i32> %mul to <4 x float> + store <4 x float> %1, <4 x float>* %y, align 16 + ret void +} +;CHECK: v4i32_to_v4f32: +;CHECK: vcfsx {{[0-9]+}}, {{[0-9]+}}, 0 + + +define void @v4u32_to_v4f32(<4 x i32> %x, <4 x float>* nocapture %y) nounwind { +entry: + %0 = load <4 x i32>* @cte_int, align 16 + %mul = mul <4 x i32> %0, %x + %1 = uitofp <4 x i32> %mul to <4 x float> + store <4 x float> %1, <4 x float>* %y, align 16 + ret void +} +;CHECK: v4u32_to_v4f32: +;CHECK: vcfux {{[0-9]+}}, {{[0-9]+}}, 0 diff --git a/test/CodeGen/SPARC/2011-01-11-CC.ll b/test/CodeGen/SPARC/2011-01-11-CC.ll index 3ceda958de6..f676fd83694 100755 --- a/test/CodeGen/SPARC/2011-01-11-CC.ll +++ b/test/CodeGen/SPARC/2011-01-11-CC.ll @@ -54,7 +54,7 @@ entry: ; V8: {{be|bne}} ; V9: test_select_dfp_icc ; V9: subcc -; V9=NOT: {{be|bne}} +; V9-NOT: {{be|bne}} ; V9: fmovd{{e|ne}} %icc %0 = icmp eq i32 %a, 0 %1 = select i1 %0, double %f1, double %f2 diff --git a/test/CodeGen/X86/2012-10-02-DAGCycle.ll b/test/CodeGen/X86/2012-10-02-DAGCycle.ll new file mode 100644 index 00000000000..8d914db3315 --- /dev/null +++ b/test/CodeGen/X86/2012-10-02-DAGCycle.ll @@ -0,0 +1,52 @@ +; RUN: llc -mtriple=i386-apple-macosx -relocation-model=pic < %s +; RUN: llc -mtriple=x86_64-apple-macosx -relocation-model=pic < %s + +; rdar://12393897 + +%TRp = type { i32, %TRH*, i32, i32 } +%TRH = type { i8*, i8*, i8*, i8*, {}* } + +define i32 @t(%TRp* inreg %rp) nounwind optsize ssp { +entry: + %handler = getelementptr inbounds %TRp* %rp, i32 0, i32 1 + %0 = load %TRH** %handler, align 4 + %sync = getelementptr inbounds %TRH* %0, i32 0, i32 4 + %sync12 = load {}** %sync, align 4 + %1 = bitcast {}* %sync12 to i32 (%TRp*)* + %call = tail call i32 %1(%TRp* inreg %rp) nounwind optsize + ret i32 %call +} + +%btConeShape = type { %btConvexInternalShape, float, float, float, [3 x i32] } +%btConvexInternalShape = type { %btConvexShape, %btVector, %btVector, float, float } +%btConvexShape = type { %btCollisionShape } +%btCollisionShape = type { i32 (...)**, i32, i8* } +%btVector = type { [4 x float] } + +define { <2 x float>, <2 x float> } @t2(%btConeShape* %this) unnamed_addr uwtable ssp align 2 { +entry: + %0 = getelementptr inbounds %btConeShape* %this, i64 0, i32 0 + br i1 undef, label %if.then, label %if.end17 + +if.then: ; preds = %entry + %vecnorm.sroa.2.8.copyload = load float* undef, align 4 + %cmp4 = fcmp olt float undef, 0x3D10000000000000 + %vecnorm.sroa.2.8.copyload36 = select i1 %cmp4, float -1.000000e+00, float %vecnorm.sroa.2.8.copyload + %call.i.i.i = tail call float @sqrtf(float 0.000000e+00) nounwind readnone + %div.i.i = fdiv float 1.000000e+00, %call.i.i.i + %mul7.i.i.i = fmul float %div.i.i, %vecnorm.sroa.2.8.copyload36 + %1 = load float (%btConvexInternalShape*)** undef, align 8 + %call12 = tail call float %1(%btConvexInternalShape* %0) + %mul7.i.i = fmul float %call12, %mul7.i.i.i + %retval.sroa.0.4.insert = insertelement <2 x float> zeroinitializer, float undef, i32 1 + %add13.i = fadd float undef, %mul7.i.i + %retval.sroa.1.8.insert = insertelement <2 x float> undef, float %add13.i, i32 0 + br label %if.end17 + +if.end17: ; preds = %if.then, %entry + %retval.sroa.1.8.load3338 = phi <2 x float> [ %retval.sroa.1.8.insert, %if.then ], [ undef, %entry ] + %retval.sroa.0.0.load3137 = phi <2 x float> [ %retval.sroa.0.4.insert, %if.then ], [ undef, %entry ] + ret { <2 x float>, <2 x float> } undef +} + +declare float @sqrtf(float) nounwind readnone diff --git a/test/CodeGen/X86/2012-10-03-DAGCycle.ll b/test/CodeGen/X86/2012-10-03-DAGCycle.ll new file mode 100644 index 00000000000..72083c7115e --- /dev/null +++ b/test/CodeGen/X86/2012-10-03-DAGCycle.ll @@ -0,0 +1,31 @@ +; RUN: llc -mtriple=x86_64-apple-macosx -mcpu=corei7 < %s + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target triple = "x86_64-apple-macosx10.8.0" + +%struct.pluto.0 = type { %struct.bar.1, %struct.hoge.368* } +%struct.bar.1 = type { %i8* } +%i8 = type { i8 } +%struct.hoge.368 = type { i32, i32 } +%struct.widget.375 = type { i32, i32, %i8*, %struct.hoge.368* } + +define fastcc void @bar(%struct.pluto.0* %arg) nounwind uwtable ssp align 2 { +bb: + %tmp1 = alloca %struct.widget.375, align 8 + %tmp2 = getelementptr inbounds %struct.pluto.0* %arg, i64 0, i32 1 + %tmp3 = load %struct.hoge.368** %tmp2, align 8 + store %struct.pluto.0* %arg, %struct.pluto.0** undef, align 8 + %tmp = getelementptr inbounds %struct.widget.375* %tmp1, i64 0, i32 2 + %tmp4 = getelementptr %struct.pluto.0* %arg, i64 0, i32 0, i32 0 + %tmp5 = load %i8** %tmp4, align 8 + store %i8* %tmp5, %i8** %tmp, align 8 + %tmp6 = getelementptr inbounds %struct.widget.375* %tmp1, i64 0, i32 3 + store %struct.hoge.368* %tmp3, %struct.hoge.368** %tmp6, align 8 + br i1 undef, label %bb8, label %bb7 + +bb7: ; preds = %bb + unreachable + +bb8: ; preds = %bb + unreachable +} diff --git a/test/CodeGen/X86/MergeConsecutiveStores.ll b/test/CodeGen/X86/MergeConsecutiveStores.ll new file mode 100644 index 00000000000..64825bac971 --- /dev/null +++ b/test/CodeGen/X86/MergeConsecutiveStores.ll @@ -0,0 +1,305 @@ +; RUN: llc -march=x86-64 -mcpu=corei7 -mattr=+avx < %s | FileCheck %s + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target triple = "x86_64-apple-macosx10.8.0" + +%struct.A = type { i8, i8, i8, i8, i8, i8, i8, i8 } +%struct.B = type { i32, i32, i32, i32, i32, i32, i32, i32 } + +; CHECK: merge_const_store +; save 1,2,3 ... as one big integer. +; CHECK: movabsq $578437695752307201 +; CHECK: ret +define void @merge_const_store(i32 %count, %struct.A* nocapture %p) nounwind uwtable noinline ssp { + %1 = icmp sgt i32 %count, 0 + br i1 %1, label %.lr.ph, label %._crit_edge +.lr.ph: + %i.02 = phi i32 [ %10, %.lr.ph ], [ 0, %0 ] + %.01 = phi %struct.A* [ %11, %.lr.ph ], [ %p, %0 ] + %2 = getelementptr inbounds %struct.A* %.01, i64 0, i32 0 + store i8 1, i8* %2, align 1 + %3 = getelementptr inbounds %struct.A* %.01, i64 0, i32 1 + store i8 2, i8* %3, align 1 + %4 = getelementptr inbounds %struct.A* %.01, i64 0, i32 2 + store i8 3, i8* %4, align 1 + %5 = getelementptr inbounds %struct.A* %.01, i64 0, i32 3 + store i8 4, i8* %5, align 1 + %6 = getelementptr inbounds %struct.A* %.01, i64 0, i32 4 + store i8 5, i8* %6, align 1 + %7 = getelementptr inbounds %struct.A* %.01, i64 0, i32 5 + store i8 6, i8* %7, align 1 + %8 = getelementptr inbounds %struct.A* %.01, i64 0, i32 6 + store i8 7, i8* %8, align 1 + %9 = getelementptr inbounds %struct.A* %.01, i64 0, i32 7 + store i8 8, i8* %9, align 1 + %10 = add nsw i32 %i.02, 1 + %11 = getelementptr inbounds %struct.A* %.01, i64 1 + %exitcond = icmp eq i32 %10, %count + br i1 %exitcond, label %._crit_edge, label %.lr.ph +._crit_edge: + ret void +} + +; Move the constants using a single vector store. +; CHECK: merge_const_store_vec +; CHECK: vmovups %ymm0, (%rsi) +; CHECK: ret +define void @merge_const_store_vec(i32 %count, %struct.B* nocapture %p) nounwind uwtable noinline ssp { + %1 = icmp sgt i32 %count, 0 + br i1 %1, label %.lr.ph, label %._crit_edge +.lr.ph: + %i.02 = phi i32 [ %10, %.lr.ph ], [ 0, %0 ] + %.01 = phi %struct.B* [ %11, %.lr.ph ], [ %p, %0 ] + %2 = getelementptr inbounds %struct.B* %.01, i64 0, i32 0 + store i32 0, i32* %2, align 4 + %3 = getelementptr inbounds %struct.B* %.01, i64 0, i32 1 + store i32 0, i32* %3, align 4 + %4 = getelementptr inbounds %struct.B* %.01, i64 0, i32 2 + store i32 0, i32* %4, align 4 + %5 = getelementptr inbounds %struct.B* %.01, i64 0, i32 3 + store i32 0, i32* %5, align 4 + %6 = getelementptr inbounds %struct.B* %.01, i64 0, i32 4 + store i32 0, i32* %6, align 4 + %7 = getelementptr inbounds %struct.B* %.01, i64 0, i32 5 + store i32 0, i32* %7, align 4 + %8 = getelementptr inbounds %struct.B* %.01, i64 0, i32 6 + store i32 0, i32* %8, align 4 + %9 = getelementptr inbounds %struct.B* %.01, i64 0, i32 7 + store i32 0, i32* %9, align 4 + %10 = add nsw i32 %i.02, 1 + %11 = getelementptr inbounds %struct.B* %.01, i64 1 + %exitcond = icmp eq i32 %10, %count + br i1 %exitcond, label %._crit_edge, label %.lr.ph +._crit_edge: + ret void +} + +; Move the first 4 constants as a single vector. Move the rest as scalars. +; CHECK: merge_nonconst_store +; CHECK: movl $67305985 +; CHECK: movb +; CHECK: movb +; CHECK: movb +; CHECK: movb +; CHECK: ret +define void @merge_nonconst_store(i32 %count, i8 %zz, %struct.A* nocapture %p) nounwind uwtable noinline ssp { + %1 = icmp sgt i32 %count, 0 + br i1 %1, label %.lr.ph, label %._crit_edge +.lr.ph: + %i.02 = phi i32 [ %10, %.lr.ph ], [ 0, %0 ] + %.01 = phi %struct.A* [ %11, %.lr.ph ], [ %p, %0 ] + %2 = getelementptr inbounds %struct.A* %.01, i64 0, i32 0 + store i8 1, i8* %2, align 1 + %3 = getelementptr inbounds %struct.A* %.01, i64 0, i32 1 + store i8 2, i8* %3, align 1 + %4 = getelementptr inbounds %struct.A* %.01, i64 0, i32 2 + store i8 3, i8* %4, align 1 + %5 = getelementptr inbounds %struct.A* %.01, i64 0, i32 3 + store i8 4, i8* %5, align 1 + %6 = getelementptr inbounds %struct.A* %.01, i64 0, i32 4 + store i8 %zz, i8* %6, align 1 ; <----------- Not a const; + %7 = getelementptr inbounds %struct.A* %.01, i64 0, i32 5 + store i8 6, i8* %7, align 1 + %8 = getelementptr inbounds %struct.A* %.01, i64 0, i32 6 + store i8 7, i8* %8, align 1 + %9 = getelementptr inbounds %struct.A* %.01, i64 0, i32 7 + store i8 8, i8* %9, align 1 + %10 = add nsw i32 %i.02, 1 + %11 = getelementptr inbounds %struct.A* %.01, i64 1 + %exitcond = icmp eq i32 %10, %count + br i1 %exitcond, label %._crit_edge, label %.lr.ph +._crit_edge: + ret void +} + + +;CHECK: merge_loads_i16 +; load: +;CHECK: movw +; store: +;CHECK: movw +;CHECK: ret +define void @merge_loads_i16(i32 %count, %struct.A* noalias nocapture %q, %struct.A* noalias nocapture %p) nounwind uwtable noinline ssp { + %1 = icmp sgt i32 %count, 0 + br i1 %1, label %.lr.ph, label %._crit_edge + +.lr.ph: ; preds = %0 + %2 = getelementptr inbounds %struct.A* %q, i64 0, i32 0 + %3 = getelementptr inbounds %struct.A* %q, i64 0, i32 1 + br label %4 + +; <label>:4 ; preds = %4, %.lr.ph + %i.02 = phi i32 [ 0, %.lr.ph ], [ %9, %4 ] + %.01 = phi %struct.A* [ %p, %.lr.ph ], [ %10, %4 ] + %5 = load i8* %2, align 1 + %6 = load i8* %3, align 1 + %7 = getelementptr inbounds %struct.A* %.01, i64 0, i32 0 + store i8 %5, i8* %7, align 1 + %8 = getelementptr inbounds %struct.A* %.01, i64 0, i32 1 + store i8 %6, i8* %8, align 1 + %9 = add nsw i32 %i.02, 1 + %10 = getelementptr inbounds %struct.A* %.01, i64 1 + %exitcond = icmp eq i32 %9, %count + br i1 %exitcond, label %._crit_edge, label %4 + +._crit_edge: ; preds = %4, %0 + ret void +} + +; The loads and the stores are interleved. Can't merge them. +;CHECK: no_merge_loads +;CHECK: movb +;CHECK: movb +;CHECK: movb +;CHECK: movb +;CHECK: ret +define void @no_merge_loads(i32 %count, %struct.A* noalias nocapture %q, %struct.A* noalias nocapture %p) nounwind uwtable noinline ssp { + %1 = icmp sgt i32 %count, 0 + br i1 %1, label %.lr.ph, label %._crit_edge + +.lr.ph: ; preds = %0 + %2 = getelementptr inbounds %struct.A* %q, i64 0, i32 0 + %3 = getelementptr inbounds %struct.A* %q, i64 0, i32 1 + br label %a4 + +a4: ; preds = %4, %.lr.ph + %i.02 = phi i32 [ 0, %.lr.ph ], [ %a9, %a4 ] + %.01 = phi %struct.A* [ %p, %.lr.ph ], [ %a10, %a4 ] + %a5 = load i8* %2, align 1 + %a7 = getelementptr inbounds %struct.A* %.01, i64 0, i32 0 + store i8 %a5, i8* %a7, align 1 + %a8 = getelementptr inbounds %struct.A* %.01, i64 0, i32 1 + %a6 = load i8* %3, align 1 + store i8 %a6, i8* %a8, align 1 + %a9 = add nsw i32 %i.02, 1 + %a10 = getelementptr inbounds %struct.A* %.01, i64 1 + %exitcond = icmp eq i32 %a9, %count + br i1 %exitcond, label %._crit_edge, label %a4 + +._crit_edge: ; preds = %4, %0 + ret void +} + + +;CHECK: merge_loads_integer +; load: +;CHECK: movq +; store: +;CHECK: movq +;CHECK: ret +define void @merge_loads_integer(i32 %count, %struct.B* noalias nocapture %q, %struct.B* noalias nocapture %p) nounwind uwtable noinline ssp { + %1 = icmp sgt i32 %count, 0 + br i1 %1, label %.lr.ph, label %._crit_edge + +.lr.ph: ; preds = %0 + %2 = getelementptr inbounds %struct.B* %q, i64 0, i32 0 + %3 = getelementptr inbounds %struct.B* %q, i64 0, i32 1 + br label %4 + +; <label>:4 ; preds = %4, %.lr.ph + %i.02 = phi i32 [ 0, %.lr.ph ], [ %9, %4 ] + %.01 = phi %struct.B* [ %p, %.lr.ph ], [ %10, %4 ] + %5 = load i32* %2 + %6 = load i32* %3 + %7 = getelementptr inbounds %struct.B* %.01, i64 0, i32 0 + store i32 %5, i32* %7 + %8 = getelementptr inbounds %struct.B* %.01, i64 0, i32 1 + store i32 %6, i32* %8 + %9 = add nsw i32 %i.02, 1 + %10 = getelementptr inbounds %struct.B* %.01, i64 1 + %exitcond = icmp eq i32 %9, %count + br i1 %exitcond, label %._crit_edge, label %4 + +._crit_edge: ; preds = %4, %0 + ret void +} + + +;CHECK: merge_loads_vector +; load: +;CHECK: movups +; store: +;CHECK: movups +;CHECK: ret +define void @merge_loads_vector(i32 %count, %struct.B* noalias nocapture %q, %struct.B* noalias nocapture %p) nounwind uwtable noinline ssp { + %a1 = icmp sgt i32 %count, 0 + br i1 %a1, label %.lr.ph, label %._crit_edge + +.lr.ph: ; preds = %0 + %a2 = getelementptr inbounds %struct.B* %q, i64 0, i32 0 + %a3 = getelementptr inbounds %struct.B* %q, i64 0, i32 1 + %a4 = getelementptr inbounds %struct.B* %q, i64 0, i32 2 + %a5 = getelementptr inbounds %struct.B* %q, i64 0, i32 3 + br label %block4 + +block4: ; preds = %4, %.lr.ph + %i.02 = phi i32 [ 0, %.lr.ph ], [ %c9, %block4 ] + %.01 = phi %struct.B* [ %p, %.lr.ph ], [ %c10, %block4 ] + %a7 = getelementptr inbounds %struct.B* %.01, i64 0, i32 0 + %a8 = getelementptr inbounds %struct.B* %.01, i64 0, i32 1 + %a9 = getelementptr inbounds %struct.B* %.01, i64 0, i32 2 + %a10 = getelementptr inbounds %struct.B* %.01, i64 0, i32 3 + %b1 = load i32* %a2 + %b2 = load i32* %a3 + %b3 = load i32* %a4 + %b4 = load i32* %a5 + store i32 %b1, i32* %a7 + store i32 %b2, i32* %a8 + store i32 %b3, i32* %a9 + store i32 %b4, i32* %a10 + %c9 = add nsw i32 %i.02, 1 + %c10 = getelementptr inbounds %struct.B* %.01, i64 1 + %exitcond = icmp eq i32 %c9, %count + br i1 %exitcond, label %._crit_edge, label %block4 + +._crit_edge: ; preds = %4, %0 + ret void +} + +;CHECK: merge_loads_no_align +; load: +;CHECK: movl +;CHECK: movl +;CHECK: movl +;CHECK: movl +; store: +;CHECK: movl +;CHECK: movl +;CHECK: movl +;CHECK: movl +;CHECK: ret +define void @merge_loads_no_align(i32 %count, %struct.B* noalias nocapture %q, %struct.B* noalias nocapture %p) nounwind uwtable noinline ssp { + %a1 = icmp sgt i32 %count, 0 + br i1 %a1, label %.lr.ph, label %._crit_edge + +.lr.ph: ; preds = %0 + %a2 = getelementptr inbounds %struct.B* %q, i64 0, i32 0 + %a3 = getelementptr inbounds %struct.B* %q, i64 0, i32 1 + %a4 = getelementptr inbounds %struct.B* %q, i64 0, i32 2 + %a5 = getelementptr inbounds %struct.B* %q, i64 0, i32 3 + br label %block4 + +block4: ; preds = %4, %.lr.ph + %i.02 = phi i32 [ 0, %.lr.ph ], [ %c9, %block4 ] + %.01 = phi %struct.B* [ %p, %.lr.ph ], [ %c10, %block4 ] + %a7 = getelementptr inbounds %struct.B* %.01, i64 0, i32 0 + %a8 = getelementptr inbounds %struct.B* %.01, i64 0, i32 1 + %a9 = getelementptr inbounds %struct.B* %.01, i64 0, i32 2 + %a10 = getelementptr inbounds %struct.B* %.01, i64 0, i32 3 + %b1 = load i32* %a2, align 1 + %b2 = load i32* %a3, align 1 + %b3 = load i32* %a4, align 1 + %b4 = load i32* %a5, align 1 + store i32 %b1, i32* %a7, align 1 + store i32 %b2, i32* %a8, align 1 + store i32 %b3, i32* %a9, align 1 + store i32 %b4, i32* %a10, align 1 + %c9 = add nsw i32 %i.02, 1 + %c10 = getelementptr inbounds %struct.B* %.01, i64 1 + %exitcond = icmp eq i32 %c9, %count + br i1 %exitcond, label %._crit_edge, label %block4 + +._crit_edge: ; preds = %4, %0 + ret void +} + diff --git a/test/CodeGen/X86/atomic-minmax-i6432.ll b/test/CodeGen/X86/atomic-minmax-i6432.ll index 01a926489be..e3ef605f7f1 100644 --- a/test/CodeGen/X86/atomic-minmax-i6432.ll +++ b/test/CodeGen/X86/atomic-minmax-i6432.ll @@ -1,51 +1,67 @@ -; RUN: llc -march=x86 -mattr=+cmov -mtriple=i386-pc-linux < %s | FileCheck %s +; RUN: llc -march=x86 -mattr=+cmov -mtriple=i386-pc-linux < %s | FileCheck %s -check-prefix=LINUX +; RUN: llc -march=x86 -mtriple=i386-macosx -relocation-model=pic < %s | FileCheck %s -check-prefix=PIC + @sc64 = external global i64 define void @atomic_maxmin_i6432() { -; CHECK: atomic_maxmin_i6432 +; LINUX: atomic_maxmin_i6432 %1 = atomicrmw max i64* @sc64, i64 5 acquire -; CHECK: [[LABEL:.LBB[0-9]+_[0-9]+]] -; CHECK: cmpl -; CHECK: setl -; CHECK: cmpl -; CHECK: setl -; CHECK: cmovne -; CHECK: cmovne -; CHECK: lock -; CHECK-NEXT: cmpxchg8b -; CHECK: jne [[LABEL]] +; LINUX: [[LABEL:.LBB[0-9]+_[0-9]+]] +; LINUX: cmpl +; LINUX: setl +; LINUX: cmpl +; LINUX: setl +; LINUX: cmovne +; LINUX: cmovne +; LINUX: lock +; LINUX-NEXT: cmpxchg8b +; LINUX: jne [[LABEL]] %2 = atomicrmw min i64* @sc64, i64 6 acquire -; CHECK: [[LABEL:.LBB[0-9]+_[0-9]+]] -; CHECK: cmpl -; CHECK: setg -; CHECK: cmpl -; CHECK: setg -; CHECK: cmovne -; CHECK: cmovne -; CHECK: lock -; CHECK-NEXT: cmpxchg8b -; CHECK: jne [[LABEL]] +; LINUX: [[LABEL:.LBB[0-9]+_[0-9]+]] +; LINUX: cmpl +; LINUX: setg +; LINUX: cmpl +; LINUX: setg +; LINUX: cmovne +; LINUX: cmovne +; LINUX: lock +; LINUX-NEXT: cmpxchg8b +; LINUX: jne [[LABEL]] %3 = atomicrmw umax i64* @sc64, i64 7 acquire -; CHECK: [[LABEL:.LBB[0-9]+_[0-9]+]] -; CHECK: cmpl -; CHECK: setb -; CHECK: cmpl -; CHECK: setb -; CHECK: cmovne -; CHECK: cmovne -; CHECK: lock -; CHECK-NEXT: cmpxchg8b -; CHECK: jne [[LABEL]] +; LINUX: [[LABEL:.LBB[0-9]+_[0-9]+]] +; LINUX: cmpl +; LINUX: setb +; LINUX: cmpl +; LINUX: setb +; LINUX: cmovne +; LINUX: cmovne +; LINUX: lock +; LINUX-NEXT: cmpxchg8b +; LINUX: jne [[LABEL]] %4 = atomicrmw umin i64* @sc64, i64 8 acquire -; CHECK: [[LABEL:.LBB[0-9]+_[0-9]+]] -; CHECK: cmpl -; CHECK: seta -; CHECK: cmpl -; CHECK: seta -; CHECK: cmovne -; CHECK: cmovne -; CHECK: lock -; CHECK-NEXT: cmpxchg8b -; CHECK: jne [[LABEL]] +; LINUX: [[LABEL:.LBB[0-9]+_[0-9]+]] +; LINUX: cmpl +; LINUX: seta +; LINUX: cmpl +; LINUX: seta +; LINUX: cmovne +; LINUX: cmovne +; LINUX: lock +; LINUX-NEXT: cmpxchg8b +; LINUX: jne [[LABEL]] + ret void +} + +; rdar://12453106 +@id = internal global i64 0, align 8 + +define void @tf_bug(i8* %ptr) nounwind { +; PIC: tf_bug: +; PIC: movl _id-L1$pb( +; PIC: movl (_id-L1$pb)+4( + %tmp1 = atomicrmw add i64* @id, i64 1 seq_cst + %tmp2 = add i64 %tmp1, 1 + %tmp3 = bitcast i8* %ptr to i64* + store i64 %tmp2, i64* %tmp3, align 4 ret void } diff --git a/test/CodeGen/X86/cmov-fp.ll b/test/CodeGen/X86/cmov-fp.ll new file mode 100644 index 00000000000..ca91f9ea2c2 --- /dev/null +++ b/test/CodeGen/X86/cmov-fp.ll @@ -0,0 +1,451 @@ +; RUN: llc -march x86 -mcpu pentium4 < %s | FileCheck %s -check-prefix=SSE +; RUN: llc -march x86 -mcpu pentium3 < %s | FileCheck %s -check-prefix=NOSSE2 +; RUN: llc -march x86 -mcpu pentium2 < %s | FileCheck %s -check-prefix=NOSSE1 +; RUN: llc -march x86 -mcpu pentium < %s | FileCheck %s -check-prefix=NOCMOV +; PR14035 + +define double @test1(i32 %a, i32 %b, double %x) nounwind { + %cmp = icmp ugt i32 %a, %b + %sel = select i1 %cmp, double 99.0, double %x + ret double %sel + +; SSE: test1: +; SSE: movsd + +; NOSSE2: test1: +; NOSSE2: fcmovnbe + +; NOSSE1: test1: +; NOSSE1: fcmovnbe + +; NOCMOV: test1: +; NOCMOV: fstp + +} + +define double @test2(i32 %a, i32 %b, double %x) nounwind { + %cmp = icmp uge i32 %a, %b + %sel = select i1 %cmp, double 99.0, double %x + ret double %sel + +; SSE: test2: +; SSE: movsd + +; NOSSE2: test2: +; NOSSE2: fcmovnb + +; NOSSE1: test2: +; NOSSE1: fcmovnb + +; NOCMOV: test2: +; NOCMOV: fstp +} + +define double @test3(i32 %a, i32 %b, double %x) nounwind { + %cmp = icmp ult i32 %a, %b + %sel = select i1 %cmp, double 99.0, double %x + ret double %sel + +; SSE: test3: +; SSE: movsd + +; NOSSE2: test3: +; NOSSE2: fcmovb + +; NOSSE1: test3: +; NOSSE1: fcmovb + +; NOCMOV: test3: +; NOCMOV: fstp +} + +define double @test4(i32 %a, i32 %b, double %x) nounwind { + %cmp = icmp ule i32 %a, %b + %sel = select i1 %cmp, double 99.0, double %x + ret double %sel + +; SSE: test4: +; SSE: movsd + +; NOSSE2: test4: +; NOSSE2: fcmovbe + +; NOSSE1: test4: +; NOSSE1: fcmovbe + +; NOCMOV: test4: +; NOCMOV: fstp +} + +define double @test5(i32 %a, i32 %b, double %x) nounwind { + %cmp = icmp sgt i32 %a, %b + %sel = select i1 %cmp, double 99.0, double %x + ret double %sel + +; SSE: test5: +; SSE: movsd + +; NOSSE2: test5: +; NOSSE2: fstp + +; NOSSE1: test5: +; NOSSE1: fstp + +; NOCMOV: test5: +; NOCMOV: fstp +} + +define double @test6(i32 %a, i32 %b, double %x) nounwind { + %cmp = icmp sge i32 %a, %b + %sel = select i1 %cmp, double 99.0, double %x + ret double %sel + +; SSE: test6: +; SSE: movsd + +; NOSSE2: test6: +; NOSSE2: fstp + +; NOSSE1: test6: +; NOSSE1: fstp + +; NOCMOV: test6: +; NOCMOV: fstp +} + +define double @test7(i32 %a, i32 %b, double %x) nounwind { + %cmp = icmp slt i32 %a, %b + %sel = select i1 %cmp, double 99.0, double %x + ret double %sel + +; SSE: test7: +; SSE: movsd + +; NOSSE2: test7: +; NOSSE2: fstp + +; NOSSE1: test7: +; NOSSE1: fstp + +; NOCMOV: test7: +; NOCMOV: fstp +} + +define double @test8(i32 %a, i32 %b, double %x) nounwind { + %cmp = icmp sle i32 %a, %b + %sel = select i1 %cmp, double 99.0, double %x + ret double %sel + +; SSE: test8: +; SSE: movsd + +; NOSSE2: test8: +; NOSSE2: fstp + +; NOSSE1: test8: +; NOSSE1: fstp + +; NOCMOV: test8: +; NOCMOV: fstp +} + +define float @test9(i32 %a, i32 %b, float %x) nounwind { + %cmp = icmp ugt i32 %a, %b + %sel = select i1 %cmp, float 99.0, float %x + ret float %sel + +; SSE: test9: +; SSE: movss + +; NOSSE2: test9: +; NOSSE2: movss + +; NOSSE1: test9: +; NOSSE1: fcmovnbe + +; NOCMOV: test9: +; NOCMOV: fstp +} + +define float @test10(i32 %a, i32 %b, float %x) nounwind { + %cmp = icmp uge i32 %a, %b + %sel = select i1 %cmp, float 99.0, float %x + ret float %sel + +; SSE: test10: +; SSE: movss + +; NOSSE2: test10: +; NOSSE2: movss + +; NOSSE1: test10: +; NOSSE1: fcmovnb + +; NOCMOV: test10: +; NOCMOV: fstp +} + +define float @test11(i32 %a, i32 %b, float %x) nounwind { + %cmp = icmp ult i32 %a, %b + %sel = select i1 %cmp, float 99.0, float %x + ret float %sel + +; SSE: test11: +; SSE: movss + +; NOSSE2: test11: +; NOSSE2: movss + +; NOSSE1: test11: +; NOSSE1: fcmovb + +; NOCMOV: test11: +; NOCMOV: fstp +} + +define float @test12(i32 %a, i32 %b, float %x) nounwind { + %cmp = icmp ule i32 %a, %b + %sel = select i1 %cmp, float 99.0, float %x + ret float %sel + +; SSE: test12: +; SSE: movss + +; NOSSE2: test12: +; NOSSE2: movss + +; NOSSE1: test12: +; NOSSE1: fcmovbe + +; NOCMOV: test12: +; NOCMOV: fstp +} + +define float @test13(i32 %a, i32 %b, float %x) nounwind { + %cmp = icmp sgt i32 %a, %b + %sel = select i1 %cmp, float 99.0, float %x + ret float %sel + +; SSE: test13: +; SSE: movss + +; NOSSE2: test13: +; NOSSE2: movss + +; NOSSE1: test13: +; NOSSE1: fstp + +; NOCMOV: test13: +; NOCMOV: fstp +} + +define float @test14(i32 %a, i32 %b, float %x) nounwind { + %cmp = icmp sge i32 %a, %b + %sel = select i1 %cmp, float 99.0, float %x + ret float %sel + +; SSE: test14: +; SSE: movss + +; NOSSE2: test14: +; NOSSE2: movss + +; NOSSE1: test14: +; NOSSE1: fstp + +; NOCMOV: test14: +; NOCMOV: fstp +} + +define float @test15(i32 %a, i32 %b, float %x) nounwind { + %cmp = icmp slt i32 %a, %b + %sel = select i1 %cmp, float 99.0, float %x + ret float %sel + +; SSE: test15: +; SSE: movss + +; NOSSE2: test15: +; NOSSE2: movss + +; NOSSE1: test15: +; NOSSE1: fstp + +; NOCMOV: test15: +; NOCMOV: fstp +} + +define float @test16(i32 %a, i32 %b, float %x) nounwind { + %cmp = icmp sle i32 %a, %b + %sel = select i1 %cmp, float 99.0, float %x + ret float %sel + +; SSE: test16: +; SSE: movss + +; NOSSE2: test16: +; NOSSE2: movss + +; NOSSE1: test16: +; NOSSE1: fstp + +; NOCMOV: test16: +; NOCMOV: fstp +} + +define x86_fp80 @test17(i32 %a, i32 %b, x86_fp80 %x) nounwind { + %cmp = icmp ugt i32 %a, %b + %sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x + ret x86_fp80 %sel + +; SSE: test17: +; SSE: fcmovnbe + +; NOSSE2: test17: +; NOSSE2: fcmovnbe + +; NOSSE1: test17: +; NOSSE1: fcmovnbe + +; NOCMOV: test17: +; NOCMOV: fstp +} + +define x86_fp80 @test18(i32 %a, i32 %b, x86_fp80 %x) nounwind { + %cmp = icmp uge i32 %a, %b + %sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x + ret x86_fp80 %sel + +; SSE: test18: +; SSE: fcmovnb + +; NOSSE2: test18: +; NOSSE2: fcmovnb + +; NOSSE1: test18: +; NOSSE1: fcmovnb + +; NOCMOV: test18: +; NOCMOV: fstp +} + +define x86_fp80 @test19(i32 %a, i32 %b, x86_fp80 %x) nounwind { + %cmp = icmp ult i32 %a, %b + %sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x + ret x86_fp80 %sel + +; SSE: test19: +; SSE: fcmovb + +; NOSSE2: test19: +; NOSSE2: fcmovb + +; NOSSE1: test19: +; NOSSE1: fcmovb + +; NOCMOV: test19: +; NOCMOV: fstp +} + +define x86_fp80 @test20(i32 %a, i32 %b, x86_fp80 %x) nounwind { + %cmp = icmp ule i32 %a, %b + %sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x + ret x86_fp80 %sel + +; SSE: test20: +; SSE: fcmovbe + +; NOSSE2: test20: +; NOSSE2: fcmovbe + +; NOSSE1: test20: +; NOSSE1: fcmovbe + +; NOCMOV: test20: +; NOCMOV: fstp +} + +define x86_fp80 @test21(i32 %a, i32 %b, x86_fp80 %x) nounwind { + %cmp = icmp sgt i32 %a, %b + %sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x + ret x86_fp80 %sel + +; We don't emit a branch for fp80, why? +; SSE: test21: +; SSE: testb +; SSE: fcmovne + +; NOSSE2: test21: +; NOSSE2: testb +; NOSSE2: fcmovne + +; NOSSE1: test21: +; NOSSE1: testb +; NOSSE1: fcmovne + +; NOCMOV: test21: +; NOCMOV: fstp +} + +define x86_fp80 @test22(i32 %a, i32 %b, x86_fp80 %x) nounwind { + %cmp = icmp sge i32 %a, %b + %sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x + ret x86_fp80 %sel + +; SSE: test22: +; SSE: testb +; SSE: fcmovne + +; NOSSE2: test22: +; NOSSE2: testb +; NOSSE2: fcmovne + +; NOSSE1: test22: +; NOSSE1: testb +; NOSSE1: fcmovne + +; NOCMOV: test22: +; NOCMOV: fstp +} + +define x86_fp80 @test23(i32 %a, i32 %b, x86_fp80 %x) nounwind { + %cmp = icmp slt i32 %a, %b + %sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x + ret x86_fp80 %sel + +; SSE: test23: +; SSE: testb +; SSE: fcmovne + +; NOSSE2: test23: +; NOSSE2: testb +; NOSSE2: fcmovne + +; NOSSE1: test23: +; NOSSE1: testb +; NOSSE1: fcmovne + +; NOCMOV: test23: +; NOCMOV: fstp +} + +define x86_fp80 @test24(i32 %a, i32 %b, x86_fp80 %x) nounwind { + %cmp = icmp sle i32 %a, %b + %sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x + ret x86_fp80 %sel + +; SSE: test24: +; SSE: testb +; SSE: fcmovne + +; NOSSE2: test24: +; NOSSE2: testb +; NOSSE2: fcmovne + +; NOSSE1: test24: +; NOSSE1: testb +; NOSSE1: fcmovne + +; NOCMOV: test24: +; NOCMOV: fstp +} diff --git a/test/CodeGen/X86/early-ifcvt.ll b/test/CodeGen/X86/early-ifcvt.ll index 7883ffabd56..2e1852d3e3a 100644 --- a/test/CodeGen/X86/early-ifcvt.ll +++ b/test/CodeGen/X86/early-ifcvt.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -enable-early-ifcvt -stress-early-ifcvt | FileCheck %s +; RUN: llc < %s -x86-early-ifcvt -stress-early-ifcvt | FileCheck %s target triple = "x86_64-apple-macosx10.8.0" ; CHECK: mm2 @@ -67,3 +67,78 @@ if.end41: } declare void @fprintf(...) nounwind + +; CHECK: BZ2_decompress +; This test case contains irreducible control flow, so MachineLoopInfo doesn't +; recognize the cycle in the CFG. This would confuse MachineTraceMetrics. +define void @BZ2_decompress(i8* %s) nounwind ssp { +entry: + switch i32 undef, label %sw.default [ + i32 39, label %if.end.sw.bb2050_crit_edge + i32 36, label %sw.bb1788 + i32 37, label %if.end.sw.bb1855_crit_edge + i32 40, label %sw.bb2409 + i32 38, label %sw.bb1983 + i32 44, label %if.end.sw.bb3058_crit_edge + ] + +if.end.sw.bb3058_crit_edge: ; preds = %entry + br label %save_state_and_return + +if.end.sw.bb1855_crit_edge: ; preds = %entry + br label %save_state_and_return + +if.end.sw.bb2050_crit_edge: ; preds = %entry + br label %sw.bb2050 + +sw.bb1788: ; preds = %entry + br label %save_state_and_return + +sw.bb1983: ; preds = %entry + br i1 undef, label %save_state_and_return, label %if.then1990 + +if.then1990: ; preds = %sw.bb1983 + br label %while.body2038 + +while.body2038: ; preds = %sw.bb2050, %if.then1990 + %groupPos.8 = phi i32 [ 0, %if.then1990 ], [ %groupPos.9, %sw.bb2050 ] + br i1 undef, label %save_state_and_return, label %if.end2042 + +if.end2042: ; preds = %while.body2038 + br i1 undef, label %if.end2048, label %while.end2104 + +if.end2048: ; preds = %if.end2042 + %bsLive2054.pre = getelementptr inbounds i8* %s, i32 8 + br label %sw.bb2050 + +sw.bb2050: ; preds = %if.end2048, %if.end.sw.bb2050_crit_edge + %groupPos.9 = phi i32 [ 0, %if.end.sw.bb2050_crit_edge ], [ %groupPos.8, %if.end2048 ] + %and2064 = and i32 undef, 1 + br label %while.body2038 + +while.end2104: ; preds = %if.end2042 + br i1 undef, label %save_state_and_return, label %if.end2117 + +if.end2117: ; preds = %while.end2104 + br i1 undef, label %while.body2161.lr.ph, label %while.body2145.lr.ph + +while.body2145.lr.ph: ; preds = %if.end2117 + br label %save_state_and_return + +while.body2161.lr.ph: ; preds = %if.end2117 + br label %save_state_and_return + +sw.bb2409: ; preds = %entry + br label %save_state_and_return + +sw.default: ; preds = %entry + call void @BZ2_bz__AssertH__fail() nounwind + br label %save_state_and_return + +save_state_and_return: + %groupPos.14 = phi i32 [ 0, %sw.default ], [ %groupPos.8, %while.body2038 ], [ %groupPos.8, %while.end2104 ], [ 0, %if.end.sw.bb3058_crit_edge ], [ 0, %if.end.sw.bb1855_crit_edge ], [ %groupPos.8, %while.body2161.lr.ph ], [ %groupPos.8, %while.body2145.lr.ph ], [ 0, %sw.bb2409 ], [ 0, %sw.bb1788 ], [ 0, %sw.bb1983 ] + store i32 %groupPos.14, i32* undef, align 4 + ret void +} + +declare void @BZ2_bz__AssertH__fail() diff --git a/test/CodeGen/X86/fast-isel-x86-64.ll b/test/CodeGen/X86/fast-isel-x86-64.ll index 85a70aad759..cdfaf7f4c13 100644 --- a/test/CodeGen/X86/fast-isel-x86-64.ll +++ b/test/CodeGen/X86/fast-isel-x86-64.ll @@ -291,3 +291,16 @@ entry: } declare void @foo22(i32) + +; PR13563 +define void @test23(i8* noalias sret %result) { + %a = alloca i8 + %b = call i8* @foo23() + ret void +; CHECK: test23: +; CHECK: call +; CHECK: movq %rdi, %rax +; CHECK: ret +} + +declare i8* @foo23() diff --git a/test/CodeGen/X86/ms-inline-asm.ll b/test/CodeGen/X86/ms-inline-asm.ll index cd06fe68a69..59efa8d5477 100644 --- a/test/CodeGen/X86/ms-inline-asm.ll +++ b/test/CodeGen/X86/ms-inline-asm.ll @@ -24,3 +24,17 @@ entry: ; CHECK: .att_syntax ; CHECK: {{## InlineAsm End|#NO_APP}} } + +define void @t3(i32 %V) nounwind { +entry: + %V.addr = alloca i32, align 4 + store i32 %V, i32* %V.addr, align 4 + call void asm sideeffect inteldialect "mov eax, DWORD PTR [$0]", "*m,~{eax},~{dirflag},~{fpsr},~{flags}"(i32* %V.addr) nounwind + ret void +; CHECK: t3 +; CHECK: {{## InlineAsm Start|#APP}} +; CHECK: .intel_syntax +; CHECK: mov eax, DWORD PTR {{[[esp]}} +; CHECK: .att_syntax +; CHECK: {{## InlineAsm End|#NO_APP}} +} diff --git a/test/CodeGen/X86/smul-with-overflow.ll b/test/CodeGen/X86/smul-with-overflow.ll index 7ac3840482a..2d0b2f7aa91 100644 --- a/test/CodeGen/X86/smul-with-overflow.ll +++ b/test/CodeGen/X86/smul-with-overflow.ll @@ -67,3 +67,17 @@ entry: ; CHECK: mull ; CHECK-NEXT: ret } + +declare { i63, i1 } @llvm.smul.with.overflow.i63(i63, i63) nounwind readnone + +define i1 @test5() nounwind { +entry: + %res = call { i63, i1 } @llvm.smul.with.overflow.i63(i63 4, i63 4611686018427387903) + %sum = extractvalue { i63, i1 } %res, 0 + %overflow = extractvalue { i63, i1 } %res, 1 + ret i1 %overflow +; Was returning false, should return true (not constant folded yet though). +; PR13991 +; CHECK: test5: +; CHECK-NOT: xorb +} diff --git a/test/DebugInfo/X86/DW_AT_byte_size.ll b/test/DebugInfo/X86/DW_AT_byte_size.ll index 59280e027f3..25b5f00c6af 100644 --- a/test/DebugInfo/X86/DW_AT_byte_size.ll +++ b/test/DebugInfo/X86/DW_AT_byte_size.ll @@ -4,7 +4,8 @@ ; Checks that we don't emit a size for a pointer type. ; CHECK: DW_TAG_pointer_type ; CHECK-NEXT: DW_AT_type -; CHECK-NOT-NEXT: DW_AT_byte_size +; CHECK-NOT: DW_AT_byte_size +; CHECK: .debug_info contents %struct.A = type { i32 } diff --git a/test/DebugInfo/X86/enum-fwd-decl.ll b/test/DebugInfo/X86/enum-fwd-decl.ll index c2dacea4839..0902430008c 100644 --- a/test/DebugInfo/X86/enum-fwd-decl.ll +++ b/test/DebugInfo/X86/enum-fwd-decl.ll @@ -5,16 +5,14 @@ !llvm.dbg.cu = !{!0} -!0 = metadata !{i32 786449, i32 0, i32 4, metadata !"foo.cpp", metadata !"/Users/echristo/tmp", metadata !"clang version 3.2 (trunk 157772) (llvm/trunk 157761)", i1 true, i1 false, metadata !"", i32 0, metadata !1, metadata !6, metadata !6, metadata !7} ; [ DW_TAG_compile_unit ] +!0 = metadata !{i32 786449, i32 0, i32 4, metadata !"foo.cpp", metadata !"/tmp", metadata !"clang version 3.2 (trunk 165274) (llvm/trunk 165272)", i1 true, i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !1, metadata !3} ; [ DW_TAG_compile_unit ] [/tmp/foo.cpp] [DW_LANG_C_plus_plus] !1 = metadata !{metadata !2} -!2 = metadata !{metadata !3} -!3 = metadata !{i32 786436, null, metadata !"E", metadata !4, i32 1, i64 16, i64 16, i32 0, i32 4, null, metadata !5, i32 0, i32 0} ; [ DW_TAG_enumeration_type ] -!4 = metadata !{i32 786473, metadata !"foo.cpp", metadata !"/Users/echristo/tmp", null} ; [ DW_TAG_file_type ] -!5 = metadata !{i32 0} -!6 = metadata !{metadata !5} -!7 = metadata !{metadata !8} -!8 = metadata !{metadata !9} -!9 = metadata !{i32 786484, i32 0, null, metadata !"e", metadata !"e", metadata !"", metadata !4, i32 2, metadata !3, i32 0, i32 1, i16* @e} ; [ DW_TAG_variable ] +!2 = metadata !{i32 0} +!3 = metadata !{metadata !4} +!4 = metadata !{metadata !5} +!5 = metadata !{i32 786484, i32 0, null, metadata !"e", metadata !"e", metadata !"", metadata !6, i32 2, metadata !7, i32 0, i32 1, i16* @e} ; [ DW_TAG_variable ] [e] [line 2] [def] +!6 = metadata !{i32 786473, metadata !"foo.cpp", metadata !"/tmp", null} ; [ DW_TAG_file_type ] +!7 = metadata !{i32 786436, null, metadata !"E", metadata !6, i32 1, i64 16, i64 16, i32 0, i32 4, null, null, i32 0} ; [ DW_TAG_enumeration_type ] [E] [line 1, size 16, align 16, offset 0] [fwd] [from ] ; CHECK: DW_TAG_enumeration_type ; CHECK-NEXT: DW_AT_name diff --git a/test/DebugInfo/X86/prologue-stack.ll b/test/DebugInfo/X86/prologue-stack.ll new file mode 100644 index 00000000000..929db519026 --- /dev/null +++ b/test/DebugInfo/X86/prologue-stack.ll @@ -0,0 +1,35 @@ +; RUN: llc -disable-fp-elim -O0 %s -mtriple x86_64-unknown-linux-gnu -o - | FileCheck %s + +; int callme(int); +; int isel_line_test2() { +; callme(400); +; return 0; +; } + +define i32 @isel_line_test2() nounwind uwtable { + ; The stack adjustment should be part of the prologue. + ; CHECK: isel_line_test2: + ; CHECK: {{subq|leaq}} {{.*}}, %rsp + ; CHECK: .loc 1 5 3 prologue_end +entry: + %call = call i32 @callme(i32 400), !dbg !10 + ret i32 0, !dbg !12 +} + +declare i32 @callme(i32) + +!llvm.dbg.cu = !{!0} + +!0 = metadata !{i32 786449, i32 0, i32 12, metadata !"bar.c", metadata !"/usr/local/google/home/echristo/tmp", metadata !"clang version 3.2 (trunk 164980) (llvm/trunk 164979)", i1 true, i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1} ; [ DW_TAG_compile_unit ] [/usr/local/google/home/echristo/tmp/bar.c] [DW_LANG_C99] +!1 = metadata !{metadata !2} +!2 = metadata !{i32 0} +!3 = metadata !{metadata !4} +!4 = metadata !{metadata !5} +!5 = metadata !{i32 786478, i32 0, metadata !6, metadata !"isel_line_test2", metadata !"isel_line_test2", metadata !"", metadata !6, i32 3, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 false, i32 ()* @isel_line_test2, null, null, metadata !1, i32 4} ; [ DW_TAG_subprogram ] [line 3] [def] [scope 4] [isel_line_test2] +!6 = metadata !{i32 786473, metadata !"bar.c", metadata !"/usr/local/google/home/echristo/tmp", null} ; [ DW_TAG_file_type ] +!7 = metadata !{i32 786453, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!8 = metadata !{metadata !9} +!9 = metadata !{i32 786468, null, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed] +!10 = metadata !{i32 5, i32 3, metadata !11, null} +!11 = metadata !{i32 786443, metadata !5, i32 4, i32 1, metadata !6, i32 0} ; [ DW_TAG_lexical_block ] [/usr/local/google/home/echristo/tmp/bar.c] +!12 = metadata !{i32 6, i32 3, metadata !11, null} diff --git a/test/ExecutionEngine/2002-12-16-ArgTest.ll b/test/ExecutionEngine/2002-12-16-ArgTest.ll index eb2fe8c0483..4c03519a85a 100644 --- a/test/ExecutionEngine/2002-12-16-ArgTest.ll +++ b/test/ExecutionEngine/2002-12-16-ArgTest.ll @@ -1,4 +1,5 @@ ; RUN: %lli %s > /dev/null +; XFAIL: arm @.LC0 = internal global [10 x i8] c"argc: %d\0A\00" ; <[10 x i8]*> [#uses=1] diff --git a/test/ExecutionEngine/MCJIT/2002-12-16-ArgTest.ll b/test/ExecutionEngine/MCJIT/2002-12-16-ArgTest.ll index 46273d34009..28cc54a8680 100644 --- a/test/ExecutionEngine/MCJIT/2002-12-16-ArgTest.ll +++ b/test/ExecutionEngine/MCJIT/2002-12-16-ArgTest.ll @@ -1,4 +1,4 @@ -; RUN: %lli -use-mcjit %s > /dev/null +; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s > /dev/null @.LC0 = internal global [10 x i8] c"argc: %d\0A\00" ; <[10 x i8]*> [#uses=1] diff --git a/test/ExecutionEngine/MCJIT/2003-01-04-ArgumentBug.ll b/test/ExecutionEngine/MCJIT/2003-01-04-ArgumentBug.ll index 88bfbb3c09b..9f895983fdb 100644 --- a/test/ExecutionEngine/MCJIT/2003-01-04-ArgumentBug.ll +++ b/test/ExecutionEngine/MCJIT/2003-01-04-ArgumentBug.ll @@ -1,4 +1,4 @@ -; RUN: %lli -use-mcjit %s > /dev/null +; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s > /dev/null define i32 @foo(i32 %X, i32 %Y, double %A) { %cond212 = fcmp une double %A, 1.000000e+00 ; <i1> [#uses=1] diff --git a/test/ExecutionEngine/MCJIT/2003-01-04-LoopTest.ll b/test/ExecutionEngine/MCJIT/2003-01-04-LoopTest.ll index d5f860d1704..997b2a9037e 100644 --- a/test/ExecutionEngine/MCJIT/2003-01-04-LoopTest.ll +++ b/test/ExecutionEngine/MCJIT/2003-01-04-LoopTest.ll @@ -1,4 +1,4 @@ -; RUN: %lli -use-mcjit %s > /dev/null +; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s > /dev/null define i32 @main() { call i32 @mylog( i32 4 ) ; <i32>:1 [#uses=0] diff --git a/test/ExecutionEngine/MCJIT/2003-01-04-PhiTest.ll b/test/ExecutionEngine/MCJIT/2003-01-04-PhiTest.ll index 721f2e8859d..ba35b5bcc43 100644 --- a/test/ExecutionEngine/MCJIT/2003-01-04-PhiTest.ll +++ b/test/ExecutionEngine/MCJIT/2003-01-04-PhiTest.ll @@ -1,4 +1,4 @@ -; RUN: %lli -use-mcjit %s > /dev/null +; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s > /dev/null define i32 @main() { ; <label>:0 diff --git a/test/ExecutionEngine/MCJIT/2003-01-09-SARTest.ll b/test/ExecutionEngine/MCJIT/2003-01-09-SARTest.ll index d17df997c81..f3c88adf843 100644 --- a/test/ExecutionEngine/MCJIT/2003-01-09-SARTest.ll +++ b/test/ExecutionEngine/MCJIT/2003-01-09-SARTest.ll @@ -1,4 +1,4 @@ -; RUN: %lli -use-mcjit %s > /dev/null +; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s > /dev/null ; We were accidentally inverting the signedness of right shifts. Whoops. diff --git a/test/ExecutionEngine/MCJIT/2003-01-10-FUCOM.ll b/test/ExecutionEngine/MCJIT/2003-01-10-FUCOM.ll index e55cb06aa1e..f925e79f248 100644 --- a/test/ExecutionEngine/MCJIT/2003-01-10-FUCOM.ll +++ b/test/ExecutionEngine/MCJIT/2003-01-10-FUCOM.ll @@ -1,4 +1,4 @@ -; RUN: %lli -use-mcjit %s > /dev/null +; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s > /dev/null define i32 @main() { %X = fadd double 0.000000e+00, 1.000000e+00 ; <double> [#uses=1] diff --git a/test/ExecutionEngine/MCJIT/2003-01-15-AlignmentTest.ll b/test/ExecutionEngine/MCJIT/2003-01-15-AlignmentTest.ll index 663dc400107..5b426f6c330 100644 --- a/test/ExecutionEngine/MCJIT/2003-01-15-AlignmentTest.ll +++ b/test/ExecutionEngine/MCJIT/2003-01-15-AlignmentTest.ll @@ -1,4 +1,4 @@ -; RUN: %lli -use-mcjit %s > /dev/null +; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s > /dev/null define i32 @bar(i8* %X) { ; pointer should be 4 byte aligned! diff --git a/test/ExecutionEngine/MCJIT/2003-05-06-LivenessClobber.ll b/test/ExecutionEngine/MCJIT/2003-05-06-LivenessClobber.ll index e95294be74a..c0a7393f824 100644 --- a/test/ExecutionEngine/MCJIT/2003-05-06-LivenessClobber.ll +++ b/test/ExecutionEngine/MCJIT/2003-05-06-LivenessClobber.ll @@ -1,6 +1,6 @@ ; This testcase should return with an exit code of 1. ; -; RUN: not %lli -use-mcjit %s +; RUN: not %lli -mtriple=%mcjit_triple -use-mcjit %s @test = global i64 0 ; <i64*> [#uses=1] diff --git a/test/ExecutionEngine/MCJIT/2003-05-07-ArgumentTest.ll b/test/ExecutionEngine/MCJIT/2003-05-07-ArgumentTest.ll index a237194ea48..d3e6204a85b 100644 --- a/test/ExecutionEngine/MCJIT/2003-05-07-ArgumentTest.ll +++ b/test/ExecutionEngine/MCJIT/2003-05-07-ArgumentTest.ll @@ -1,4 +1,4 @@ -; RUN: %lli -use-mcjit %s test +; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s test declare i32 @puts(i8*) diff --git a/test/ExecutionEngine/MCJIT/2003-05-11-PHIRegAllocBug.ll b/test/ExecutionEngine/MCJIT/2003-05-11-PHIRegAllocBug.ll index 70464a3ffcb..55a16975410 100644 --- a/test/ExecutionEngine/MCJIT/2003-05-11-PHIRegAllocBug.ll +++ b/test/ExecutionEngine/MCJIT/2003-05-11-PHIRegAllocBug.ll @@ -1,4 +1,4 @@ -; RUN: %lli -use-mcjit %s > /dev/null +; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s > /dev/null target datalayout = "e-p:32:32" diff --git a/test/ExecutionEngine/MCJIT/2003-06-04-bzip2-bug.ll b/test/ExecutionEngine/MCJIT/2003-06-04-bzip2-bug.ll index 58d423f9244..79c6e7fe4ca 100644 --- a/test/ExecutionEngine/MCJIT/2003-06-04-bzip2-bug.ll +++ b/test/ExecutionEngine/MCJIT/2003-06-04-bzip2-bug.ll @@ -1,4 +1,4 @@ -; RUN: %lli -use-mcjit %s > /dev/null +; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s > /dev/null ; Testcase distilled from 256.bzip2. diff --git a/test/ExecutionEngine/MCJIT/2003-06-05-PHIBug.ll b/test/ExecutionEngine/MCJIT/2003-06-05-PHIBug.ll index a22fe07b085..ffd6df6e5e2 100644 --- a/test/ExecutionEngine/MCJIT/2003-06-05-PHIBug.ll +++ b/test/ExecutionEngine/MCJIT/2003-06-05-PHIBug.ll @@ -1,4 +1,4 @@ -; RUN: %lli -use-mcjit %s > /dev/null +; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s > /dev/null ; Testcase distilled from 256.bzip2. diff --git a/test/ExecutionEngine/MCJIT/2003-08-15-AllocaAssertion.ll b/test/ExecutionEngine/MCJIT/2003-08-15-AllocaAssertion.ll index b3c6d8abbc0..90839e96986 100644 --- a/test/ExecutionEngine/MCJIT/2003-08-15-AllocaAssertion.ll +++ b/test/ExecutionEngine/MCJIT/2003-08-15-AllocaAssertion.ll @@ -1,4 +1,4 @@ -; RUN: %lli -use-mcjit %s > /dev/null +; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s > /dev/null ; This testcase failed to work because two variable sized allocas confused the ; local register allocator. diff --git a/test/ExecutionEngine/MCJIT/2003-08-21-EnvironmentTest.ll b/test/ExecutionEngine/MCJIT/2003-08-21-EnvironmentTest.ll index bd32f3037dd..29ef2c556cd 100644 --- a/test/ExecutionEngine/MCJIT/2003-08-21-EnvironmentTest.ll +++ b/test/ExecutionEngine/MCJIT/2003-08-21-EnvironmentTest.ll @@ -1,4 +1,4 @@ -; RUN: %lli -use-mcjit %s > /dev/null +; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s > /dev/null ; ; Regression Test: EnvironmentTest.ll diff --git a/test/ExecutionEngine/MCJIT/2003-08-23-RegisterAllocatePhysReg.ll b/test/ExecutionEngine/MCJIT/2003-08-23-RegisterAllocatePhysReg.ll index 1959534b877..2adb608acbb 100644 --- a/test/ExecutionEngine/MCJIT/2003-08-23-RegisterAllocatePhysReg.ll +++ b/test/ExecutionEngine/MCJIT/2003-08-23-RegisterAllocatePhysReg.ll @@ -1,4 +1,4 @@ -; RUN: %lli -use-mcjit %s > /dev/null +; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s > /dev/null ; This testcase exposes a bug in the local register allocator where it runs out ; of registers (due to too many overlapping live ranges), but then attempts to diff --git a/test/ExecutionEngine/MCJIT/2003-10-18-PHINode-ConstantExpr-CondCode-Failure.ll b/test/ExecutionEngine/MCJIT/2003-10-18-PHINode-ConstantExpr-CondCode-Failure.ll index 1f8343fc43f..91bde469036 100644 --- a/test/ExecutionEngine/MCJIT/2003-10-18-PHINode-ConstantExpr-CondCode-Failure.ll +++ b/test/ExecutionEngine/MCJIT/2003-10-18-PHINode-ConstantExpr-CondCode-Failure.ll @@ -1,4 +1,4 @@ -; RUN: %lli -use-mcjit %s > /dev/null +; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s > /dev/null @A = global i32 0 ; <i32*> [#uses=1] diff --git a/test/ExecutionEngine/MCJIT/2005-12-02-TailCallBug.ll b/test/ExecutionEngine/MCJIT/2005-12-02-TailCallBug.ll index 79a7d583ce6..a7462d9e698 100644 --- a/test/ExecutionEngine/MCJIT/2005-12-02-TailCallBug.ll +++ b/test/ExecutionEngine/MCJIT/2005-12-02-TailCallBug.ll @@ -1,5 +1,5 @@ ; PR672 -; RUN: %lli -use-mcjit %s +; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s ; XFAIL: mcjit-ia32 define i32 @main() { diff --git a/test/ExecutionEngine/MCJIT/2007-12-10-APIntLoadStore.ll b/test/ExecutionEngine/MCJIT/2007-12-10-APIntLoadStore.ll index 52cef4d35ca..24065966025 100644 --- a/test/ExecutionEngine/MCJIT/2007-12-10-APIntLoadStore.ll +++ b/test/ExecutionEngine/MCJIT/2007-12-10-APIntLoadStore.ll @@ -1,4 +1,4 @@ -; RUN: %lli -use-mcjit -force-interpreter %s +; RUN: %lli -mtriple=%mcjit_triple -use-mcjit -force-interpreter %s ; PR1836 define i32 @main() { diff --git a/test/ExecutionEngine/MCJIT/2008-06-05-APInt-OverAShr.ll b/test/ExecutionEngine/MCJIT/2008-06-05-APInt-OverAShr.ll index a6e917f457b..d429d519e04 100644 --- a/test/ExecutionEngine/MCJIT/2008-06-05-APInt-OverAShr.ll +++ b/test/ExecutionEngine/MCJIT/2008-06-05-APInt-OverAShr.ll @@ -1,4 +1,4 @@ -; RUN: %lli -use-mcjit -force-interpreter=true %s | grep 1 +; RUN: %lli -mtriple=%mcjit_triple -use-mcjit -force-interpreter=true %s | grep 1 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32" target triple = "i686-pc-linux-gnu" diff --git a/test/ExecutionEngine/MCJIT/2010-01-15-UndefValue.ll b/test/ExecutionEngine/MCJIT/2010-01-15-UndefValue.ll index 524a724c474..a6d18e7919c 100644 --- a/test/ExecutionEngine/MCJIT/2010-01-15-UndefValue.ll +++ b/test/ExecutionEngine/MCJIT/2010-01-15-UndefValue.ll @@ -1,4 +1,4 @@ -; RUN: %lli -use-mcjit -force-interpreter=true %s +; RUN: %lli -mtriple=%mcjit_triple -use-mcjit -force-interpreter=true %s > /dev/null define i32 @main() { %a = add i32 0, undef diff --git a/test/ExecutionEngine/MCJIT/fpbitcast.ll b/test/ExecutionEngine/MCJIT/fpbitcast.ll index 9da908f8cff..bb4957e9e66 100644 --- a/test/ExecutionEngine/MCJIT/fpbitcast.ll +++ b/test/ExecutionEngine/MCJIT/fpbitcast.ll @@ -1,4 +1,4 @@ -; RUN: %lli -use-mcjit -force-interpreter=true %s | grep 40091eb8 +; RUN: %lli -mtriple=%mcjit_triple -use-mcjit -force-interpreter=true %s | grep 40091eb8 ; define i32 @test(double %x) { entry: diff --git a/test/ExecutionEngine/MCJIT/hello.ll b/test/ExecutionEngine/MCJIT/hello.ll index a52b6d48af2..ceb9c12ab4b 100644 --- a/test/ExecutionEngine/MCJIT/hello.ll +++ b/test/ExecutionEngine/MCJIT/hello.ll @@ -1,4 +1,4 @@ -; RUN: %lli -use-mcjit %s > /dev/null +; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s > /dev/null @.LC0 = internal global [12 x i8] c"Hello World\00" ; <[12 x i8]*> [#uses=1] diff --git a/test/ExecutionEngine/MCJIT/hello2.ll b/test/ExecutionEngine/MCJIT/hello2.ll index 670a6dd671c..756fcadb1ca 100644 --- a/test/ExecutionEngine/MCJIT/hello2.ll +++ b/test/ExecutionEngine/MCJIT/hello2.ll @@ -1,4 +1,4 @@ -; RUN: %lli -use-mcjit %s > /dev/null +; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s > /dev/null @X = global i32 7 ; <i32*> [#uses=0] @msg = internal global [13 x i8] c"Hello World\0A\00" ; <[13 x i8]*> [#uses=1] diff --git a/test/ExecutionEngine/MCJIT/lit.local.cfg b/test/ExecutionEngine/MCJIT/lit.local.cfg index 2980ce70811..af3d13f7467 100644 --- a/test/ExecutionEngine/MCJIT/lit.local.cfg +++ b/test/ExecutionEngine/MCJIT/lit.local.cfg @@ -16,5 +16,5 @@ else: if root.host_arch not in ['x86', 'x86_64', 'ARM', 'Mips']: config.unsupported = True -if root.host_os in ['Win32', 'Cygwin', 'MingW', 'Windows', 'Darwin']: +if root.host_os in ['Darwin']: config.unsupported = True diff --git a/test/ExecutionEngine/MCJIT/pr13727.ll b/test/ExecutionEngine/MCJIT/pr13727.ll index 5fa68f9b872..c33bf328108 100644 --- a/test/ExecutionEngine/MCJIT/pr13727.ll +++ b/test/ExecutionEngine/MCJIT/pr13727.ll @@ -1,4 +1,4 @@ -; RUN: %lli -use-mcjit -O0 -disable-lazy-compilation=false %s +; RUN: %lli -mtriple=%mcjit_triple -use-mcjit -O0 -disable-lazy-compilation=false %s ; The intention of this test is to verify that symbols mapped to COMMON in ELF ; work as expected. diff --git a/test/ExecutionEngine/MCJIT/simplesttest.ll b/test/ExecutionEngine/MCJIT/simplesttest.ll index a6688c237c0..02ad0061fd1 100644 --- a/test/ExecutionEngine/MCJIT/simplesttest.ll +++ b/test/ExecutionEngine/MCJIT/simplesttest.ll @@ -1,4 +1,4 @@ -; RUN: %lli -use-mcjit %s > /dev/null +; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s > /dev/null define i32 @main() { ret i32 0 diff --git a/test/ExecutionEngine/MCJIT/simpletest.ll b/test/ExecutionEngine/MCJIT/simpletest.ll index 4562aa6012e..958b783067e 100644 --- a/test/ExecutionEngine/MCJIT/simpletest.ll +++ b/test/ExecutionEngine/MCJIT/simpletest.ll @@ -1,4 +1,4 @@ -; RUN: %lli -use-mcjit %s > /dev/null +; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s > /dev/null define i32 @bar() { ret i32 0 diff --git a/test/ExecutionEngine/MCJIT/stubs.ll b/test/ExecutionEngine/MCJIT/stubs.ll index b285b0eadb3..9e5d5b2e418 100644 --- a/test/ExecutionEngine/MCJIT/stubs.ll +++ b/test/ExecutionEngine/MCJIT/stubs.ll @@ -1,4 +1,4 @@ -; RUN: %lli -use-mcjit -disable-lazy-compilation=false %s +; RUN: %lli -mtriple=%mcjit_triple -use-mcjit -disable-lazy-compilation=false %s define i32 @main() nounwind { entry: diff --git a/test/ExecutionEngine/MCJIT/test-arith.ll b/test/ExecutionEngine/MCJIT/test-arith.ll index 31777604d57..b73227fe635 100644 --- a/test/ExecutionEngine/MCJIT/test-arith.ll +++ b/test/ExecutionEngine/MCJIT/test-arith.ll @@ -1,4 +1,4 @@ -; RUN: %lli -use-mcjit %s > /dev/null +; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s > /dev/null define i32 @main() { %A = add i8 0, 12 ; <i8> [#uses=1] diff --git a/test/ExecutionEngine/MCJIT/test-branch.ll b/test/ExecutionEngine/MCJIT/test-branch.ll index 702c1102209..8f3c7279051 100644 --- a/test/ExecutionEngine/MCJIT/test-branch.ll +++ b/test/ExecutionEngine/MCJIT/test-branch.ll @@ -1,4 +1,4 @@ -; RUN: %lli -use-mcjit %s > /dev/null +; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s > /dev/null ; test unconditional branch define i32 @main() { diff --git a/test/ExecutionEngine/MCJIT/test-call-no-external-funcs.ll b/test/ExecutionEngine/MCJIT/test-call-no-external-funcs.ll index 6f284055fd9..20150b2de62 100644 --- a/test/ExecutionEngine/MCJIT/test-call-no-external-funcs.ll +++ b/test/ExecutionEngine/MCJIT/test-call-no-external-funcs.ll @@ -1,4 +1,4 @@ -; RUN: %lli -use-mcjit %s > /dev/null +; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s > /dev/null define i32 @_Z14func_exit_codev() nounwind uwtable { entry: diff --git a/test/ExecutionEngine/MCJIT/test-call.ll b/test/ExecutionEngine/MCJIT/test-call.ll index 7a244ee5058..51d19fe9917 100644 --- a/test/ExecutionEngine/MCJIT/test-call.ll +++ b/test/ExecutionEngine/MCJIT/test-call.ll @@ -1,4 +1,4 @@ -; RUN: %lli -use-mcjit %s > /dev/null +; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s > /dev/null declare void @exit(i32) diff --git a/test/ExecutionEngine/MCJIT/test-cast.ll b/test/ExecutionEngine/MCJIT/test-cast.ll index 75e7d1b423f..dcc97f46656 100644 --- a/test/ExecutionEngine/MCJIT/test-cast.ll +++ b/test/ExecutionEngine/MCJIT/test-cast.ll @@ -1,4 +1,4 @@ -; RUN: %lli -use-mcjit %s > /dev/null +; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s > /dev/null define i32 @foo() { ret i32 0 diff --git a/test/ExecutionEngine/MCJIT/test-common-symbols.ll b/test/ExecutionEngine/MCJIT/test-common-symbols.ll index ac1d9acd954..8c8190291f1 100644 --- a/test/ExecutionEngine/MCJIT/test-common-symbols.ll +++ b/test/ExecutionEngine/MCJIT/test-common-symbols.ll @@ -1,4 +1,4 @@ -; RUN: %lli -use-mcjit -O0 -disable-lazy-compilation=false %s +; RUN: %lli -mtriple=%mcjit_triple -use-mcjit -O0 -disable-lazy-compilation=false %s ; The intention of this test is to verify that symbols mapped to COMMON in ELF ; work as expected. diff --git a/test/ExecutionEngine/MCJIT/test-constantexpr.ll b/test/ExecutionEngine/MCJIT/test-constantexpr.ll index 6b46639c51f..56c1290448a 100644 --- a/test/ExecutionEngine/MCJIT/test-constantexpr.ll +++ b/test/ExecutionEngine/MCJIT/test-constantexpr.ll @@ -1,4 +1,4 @@ -; RUN: %lli -use-mcjit %s > /dev/null +; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s > /dev/null ; This tests to make sure that we can evaluate weird constant expressions diff --git a/test/ExecutionEngine/MCJIT/test-fp-no-external-funcs.ll b/test/ExecutionEngine/MCJIT/test-fp-no-external-funcs.ll index 35491df7917..7af1d8b5391 100644 --- a/test/ExecutionEngine/MCJIT/test-fp-no-external-funcs.ll +++ b/test/ExecutionEngine/MCJIT/test-fp-no-external-funcs.ll @@ -1,4 +1,4 @@ -; RUN: %lli -use-mcjit %s > /dev/null +; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s > /dev/null define double @test(double* %DP, double %Arg) { %D = load double* %DP ; <double> [#uses=1] diff --git a/test/ExecutionEngine/MCJIT/test-fp.ll b/test/ExecutionEngine/MCJIT/test-fp.ll index 6fc5a501f6e..f7e6fb9ba18 100644 --- a/test/ExecutionEngine/MCJIT/test-fp.ll +++ b/test/ExecutionEngine/MCJIT/test-fp.ll @@ -1,4 +1,4 @@ -; RUN: %lli -use-mcjit %s > /dev/null +; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s > /dev/null define double @test(double* %DP, double %Arg) { %D = load double* %DP ; <double> [#uses=1] diff --git a/test/ExecutionEngine/MCJIT/test-global-init-nonzero.ll b/test/ExecutionEngine/MCJIT/test-global-init-nonzero.ll index 4a790c6ff17..ec6cbad2f14 100644 --- a/test/ExecutionEngine/MCJIT/test-global-init-nonzero.ll +++ b/test/ExecutionEngine/MCJIT/test-global-init-nonzero.ll @@ -1,4 +1,4 @@ -; RUN: %lli -use-mcjit %s > /dev/null +; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s > /dev/null @count = global i32 1, align 4 diff --git a/test/ExecutionEngine/MCJIT/test-global.ll b/test/ExecutionEngine/MCJIT/test-global.ll index 94e0250769e..e7972f978e9 100644 --- a/test/ExecutionEngine/MCJIT/test-global.ll +++ b/test/ExecutionEngine/MCJIT/test-global.ll @@ -1,4 +1,4 @@ -; RUN: %lli -use-mcjit %s > /dev/null +; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s > /dev/null @count = global i32 0, align 4 diff --git a/test/ExecutionEngine/MCJIT/test-loadstore.ll b/test/ExecutionEngine/MCJIT/test-loadstore.ll index e9171490e35..f450d0ab528 100644 --- a/test/ExecutionEngine/MCJIT/test-loadstore.ll +++ b/test/ExecutionEngine/MCJIT/test-loadstore.ll @@ -1,4 +1,4 @@ -; RUN: %lli -use-mcjit %s > /dev/null +; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s > /dev/null define void @test(i8* %P, i16* %P.upgrd.1, i32* %P.upgrd.2, i64* %P.upgrd.3) { %V = load i8* %P ; <i8> [#uses=1] diff --git a/test/ExecutionEngine/MCJIT/test-local.ll b/test/ExecutionEngine/MCJIT/test-local.ll index 4f5ae47dd04..d4e9f444e42 100644 --- a/test/ExecutionEngine/MCJIT/test-local.ll +++ b/test/ExecutionEngine/MCJIT/test-local.ll @@ -1,4 +1,4 @@ -; RUN: %lli -use-mcjit %s > /dev/null +; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s > /dev/null define i32 @main() nounwind uwtable { entry: diff --git a/test/ExecutionEngine/MCJIT/test-logical.ll b/test/ExecutionEngine/MCJIT/test-logical.ll index 0540c22fc62..32f45ef119e 100644 --- a/test/ExecutionEngine/MCJIT/test-logical.ll +++ b/test/ExecutionEngine/MCJIT/test-logical.ll @@ -1,4 +1,4 @@ -; RUN: %lli -use-mcjit %s > /dev/null +; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s > /dev/null define i32 @main() { %A = and i8 4, 8 ; <i8> [#uses=2] diff --git a/test/ExecutionEngine/MCJIT/test-loop.ll b/test/ExecutionEngine/MCJIT/test-loop.ll index b1dbf408996..ebc689664d6 100644 --- a/test/ExecutionEngine/MCJIT/test-loop.ll +++ b/test/ExecutionEngine/MCJIT/test-loop.ll @@ -1,4 +1,4 @@ -; RUN: %lli -use-mcjit %s > /dev/null +; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s > /dev/null define i32 @main() { ; <label>:0 diff --git a/test/ExecutionEngine/MCJIT/test-phi.ll b/test/ExecutionEngine/MCJIT/test-phi.ll index fbc080862c8..1408533d7ae 100644 --- a/test/ExecutionEngine/MCJIT/test-phi.ll +++ b/test/ExecutionEngine/MCJIT/test-phi.ll @@ -1,4 +1,4 @@ -; RUN: %lli -use-mcjit %s > /dev/null +; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s > /dev/null ; test phi node @Y = global i32 6 ; <i32*> [#uses=1] diff --git a/test/ExecutionEngine/MCJIT/test-ptr-reloc.ll b/test/ExecutionEngine/MCJIT/test-ptr-reloc.ll new file mode 100644 index 00000000000..93b6a6deffd --- /dev/null +++ b/test/ExecutionEngine/MCJIT/test-ptr-reloc.ll @@ -0,0 +1,16 @@ +; RUN: %lli -mtriple=%mcjit_triple -use-mcjit -O0 %s + +@.str = private unnamed_addr constant [6 x i8] c"data1\00", align 1 +@ptr = global i8* getelementptr inbounds ([6 x i8]* @.str, i32 0, i32 0), align 4 +@.str1 = private unnamed_addr constant [6 x i8] c"data2\00", align 1 +@ptr2 = global i8* getelementptr inbounds ([6 x i8]* @.str1, i32 0, i32 0), align 4 + +define i32 @main(i32 %argc, i8** nocapture %argv) nounwind readonly { +entry: + %0 = load i8** @ptr, align 4 + %1 = load i8** @ptr2, align 4 + %cmp = icmp eq i8* %0, %1 + %. = zext i1 %cmp to i32 + ret i32 %. +} + diff --git a/test/ExecutionEngine/MCJIT/test-ret.ll b/test/ExecutionEngine/MCJIT/test-ret.ll index 1b90ee07506..af282926907 100644 --- a/test/ExecutionEngine/MCJIT/test-ret.ll +++ b/test/ExecutionEngine/MCJIT/test-ret.ll @@ -1,4 +1,4 @@ -; RUN: %lli -use-mcjit %s > /dev/null +; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s > /dev/null ; test return instructions define void @test1() { diff --git a/test/ExecutionEngine/MCJIT/test-return.ll b/test/ExecutionEngine/MCJIT/test-return.ll index 9c399cab38d..67f7107c3d7 100644 --- a/test/ExecutionEngine/MCJIT/test-return.ll +++ b/test/ExecutionEngine/MCJIT/test-return.ll @@ -1,4 +1,4 @@ -; RUN: %lli -use-mcjit %s > /dev/null +; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s > /dev/null define i32 @main() nounwind uwtable { entry: diff --git a/test/ExecutionEngine/MCJIT/test-setcond-fp.ll b/test/ExecutionEngine/MCJIT/test-setcond-fp.ll index 030ff317560..a8f4bd8529f 100644 --- a/test/ExecutionEngine/MCJIT/test-setcond-fp.ll +++ b/test/ExecutionEngine/MCJIT/test-setcond-fp.ll @@ -1,4 +1,4 @@ -; RUN: %lli -use-mcjit %s > /dev/null +; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s > /dev/null define i32 @main() { diff --git a/test/ExecutionEngine/MCJIT/test-setcond-int.ll b/test/ExecutionEngine/MCJIT/test-setcond-int.ll index 1113efee510..ed52b5065c8 100644 --- a/test/ExecutionEngine/MCJIT/test-setcond-int.ll +++ b/test/ExecutionEngine/MCJIT/test-setcond-int.ll @@ -1,4 +1,4 @@ -; RUN: %lli -use-mcjit %s > /dev/null +; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s > /dev/null define i32 @main() { %int1 = add i32 0, 0 ; <i32> [#uses=6] diff --git a/test/ExecutionEngine/MCJIT/test-shift.ll b/test/ExecutionEngine/MCJIT/test-shift.ll index 2da824fecce..5a5c10d5605 100644 --- a/test/ExecutionEngine/MCJIT/test-shift.ll +++ b/test/ExecutionEngine/MCJIT/test-shift.ll @@ -1,4 +1,4 @@ -; RUN: %lli -use-mcjit %s > /dev/null +; RUN: %lli -mtriple=%mcjit_triple -use-mcjit %s > /dev/null define i32 @main() { %shamt = add i8 0, 1 ; <i8> [#uses=8] diff --git a/test/ExecutionEngine/test-fp-no-external-funcs.ll b/test/ExecutionEngine/test-fp-no-external-funcs.ll index 61b12c2abeb..139b2efea57 100644 --- a/test/ExecutionEngine/test-fp-no-external-funcs.ll +++ b/test/ExecutionEngine/test-fp-no-external-funcs.ll @@ -1,4 +1,5 @@ ; RUN: %lli %s > /dev/null +; XFAIL: arm define double @test(double* %DP, double %Arg) { %D = load double* %DP ; <double> [#uses=1] diff --git a/test/ExecutionEngine/test-fp.ll b/test/ExecutionEngine/test-fp.ll index 2bf0210d8b0..c9064500d47 100644 --- a/test/ExecutionEngine/test-fp.ll +++ b/test/ExecutionEngine/test-fp.ll @@ -1,4 +1,5 @@ ; RUN: %lli %s > /dev/null +; XFAIL: arm define double @test(double* %DP, double %Arg) { %D = load double* %DP ; <double> [#uses=1] diff --git a/test/Instrumentation/ThreadSanitizer/atomic.ll b/test/Instrumentation/ThreadSanitizer/atomic.ll index 02bf215c6bf..ed3c821205c 100644 --- a/test/Instrumentation/ThreadSanitizer/atomic.ll +++ b/test/Instrumentation/ThreadSanitizer/atomic.ll @@ -8,7 +8,7 @@ entry: ret i8 %0 } ; CHECK: atomic8_load_unordered -; CHECK: call i8 @__tsan_atomic8_load(i8* %a, i32 1) +; CHECK: call i8 @__tsan_atomic8_load(i8* %a, i32 100501) define i8 @atomic8_load_monotonic(i8* %a) nounwind uwtable { entry: @@ -16,7 +16,7 @@ entry: ret i8 %0 } ; CHECK: atomic8_load_monotonic -; CHECK: call i8 @__tsan_atomic8_load(i8* %a, i32 1) +; CHECK: call i8 @__tsan_atomic8_load(i8* %a, i32 100501) define i8 @atomic8_load_acquire(i8* %a) nounwind uwtable { entry: @@ -24,7 +24,7 @@ entry: ret i8 %0 } ; CHECK: atomic8_load_acquire -; CHECK: call i8 @__tsan_atomic8_load(i8* %a, i32 4) +; CHECK: call i8 @__tsan_atomic8_load(i8* %a, i32 100504) define i8 @atomic8_load_seq_cst(i8* %a) nounwind uwtable { entry: @@ -32,7 +32,7 @@ entry: ret i8 %0 } ; CHECK: atomic8_load_seq_cst -; CHECK: call i8 @__tsan_atomic8_load(i8* %a, i32 32) +; CHECK: call i8 @__tsan_atomic8_load(i8* %a, i32 100532) define void @atomic8_store_unordered(i8* %a) nounwind uwtable { entry: @@ -40,7 +40,7 @@ entry: ret void } ; CHECK: atomic8_store_unordered -; CHECK: call void @__tsan_atomic8_store(i8* %a, i8 0, i32 1) +; CHECK: call void @__tsan_atomic8_store(i8* %a, i8 0, i32 100501) define void @atomic8_store_monotonic(i8* %a) nounwind uwtable { entry: @@ -48,7 +48,7 @@ entry: ret void } ; CHECK: atomic8_store_monotonic -; CHECK: call void @__tsan_atomic8_store(i8* %a, i8 0, i32 1) +; CHECK: call void @__tsan_atomic8_store(i8* %a, i8 0, i32 100501) define void @atomic8_store_release(i8* %a) nounwind uwtable { entry: @@ -56,7 +56,7 @@ entry: ret void } ; CHECK: atomic8_store_release -; CHECK: call void @__tsan_atomic8_store(i8* %a, i8 0, i32 8) +; CHECK: call void @__tsan_atomic8_store(i8* %a, i8 0, i32 100508) define void @atomic8_store_seq_cst(i8* %a) nounwind uwtable { entry: @@ -64,7 +64,7 @@ entry: ret void } ; CHECK: atomic8_store_seq_cst -; CHECK: call void @__tsan_atomic8_store(i8* %a, i8 0, i32 32) +; CHECK: call void @__tsan_atomic8_store(i8* %a, i8 0, i32 100532) define i16 @atomic16_load_unordered(i16* %a) nounwind uwtable { entry: @@ -72,7 +72,7 @@ entry: ret i16 %0 } ; CHECK: atomic16_load_unordered -; CHECK: call i16 @__tsan_atomic16_load(i16* %a, i32 1) +; CHECK: call i16 @__tsan_atomic16_load(i16* %a, i32 100501) define i16 @atomic16_load_monotonic(i16* %a) nounwind uwtable { entry: @@ -80,7 +80,7 @@ entry: ret i16 %0 } ; CHECK: atomic16_load_monotonic -; CHECK: call i16 @__tsan_atomic16_load(i16* %a, i32 1) +; CHECK: call i16 @__tsan_atomic16_load(i16* %a, i32 100501) define i16 @atomic16_load_acquire(i16* %a) nounwind uwtable { entry: @@ -88,7 +88,7 @@ entry: ret i16 %0 } ; CHECK: atomic16_load_acquire -; CHECK: call i16 @__tsan_atomic16_load(i16* %a, i32 4) +; CHECK: call i16 @__tsan_atomic16_load(i16* %a, i32 100504) define i16 @atomic16_load_seq_cst(i16* %a) nounwind uwtable { entry: @@ -96,7 +96,7 @@ entry: ret i16 %0 } ; CHECK: atomic16_load_seq_cst -; CHECK: call i16 @__tsan_atomic16_load(i16* %a, i32 32) +; CHECK: call i16 @__tsan_atomic16_load(i16* %a, i32 100532) define void @atomic16_store_unordered(i16* %a) nounwind uwtable { entry: @@ -104,7 +104,7 @@ entry: ret void } ; CHECK: atomic16_store_unordered -; CHECK: call void @__tsan_atomic16_store(i16* %a, i16 0, i32 1) +; CHECK: call void @__tsan_atomic16_store(i16* %a, i16 0, i32 100501) define void @atomic16_store_monotonic(i16* %a) nounwind uwtable { entry: @@ -112,7 +112,7 @@ entry: ret void } ; CHECK: atomic16_store_monotonic -; CHECK: call void @__tsan_atomic16_store(i16* %a, i16 0, i32 1) +; CHECK: call void @__tsan_atomic16_store(i16* %a, i16 0, i32 100501) define void @atomic16_store_release(i16* %a) nounwind uwtable { entry: @@ -120,7 +120,7 @@ entry: ret void } ; CHECK: atomic16_store_release -; CHECK: call void @__tsan_atomic16_store(i16* %a, i16 0, i32 8) +; CHECK: call void @__tsan_atomic16_store(i16* %a, i16 0, i32 100508) define void @atomic16_store_seq_cst(i16* %a) nounwind uwtable { entry: @@ -128,7 +128,7 @@ entry: ret void } ; CHECK: atomic16_store_seq_cst -; CHECK: call void @__tsan_atomic16_store(i16* %a, i16 0, i32 32) +; CHECK: call void @__tsan_atomic16_store(i16* %a, i16 0, i32 100532) define i32 @atomic32_load_unordered(i32* %a) nounwind uwtable { entry: @@ -136,7 +136,7 @@ entry: ret i32 %0 } ; CHECK: atomic32_load_unordered -; CHECK: call i32 @__tsan_atomic32_load(i32* %a, i32 1) +; CHECK: call i32 @__tsan_atomic32_load(i32* %a, i32 100501) define i32 @atomic32_load_monotonic(i32* %a) nounwind uwtable { entry: @@ -144,7 +144,7 @@ entry: ret i32 %0 } ; CHECK: atomic32_load_monotonic -; CHECK: call i32 @__tsan_atomic32_load(i32* %a, i32 1) +; CHECK: call i32 @__tsan_atomic32_load(i32* %a, i32 100501) define i32 @atomic32_load_acquire(i32* %a) nounwind uwtable { entry: @@ -152,7 +152,7 @@ entry: ret i32 %0 } ; CHECK: atomic32_load_acquire -; CHECK: call i32 @__tsan_atomic32_load(i32* %a, i32 4) +; CHECK: call i32 @__tsan_atomic32_load(i32* %a, i32 100504) define i32 @atomic32_load_seq_cst(i32* %a) nounwind uwtable { entry: @@ -160,7 +160,7 @@ entry: ret i32 %0 } ; CHECK: atomic32_load_seq_cst -; CHECK: call i32 @__tsan_atomic32_load(i32* %a, i32 32) +; CHECK: call i32 @__tsan_atomic32_load(i32* %a, i32 100532) define void @atomic32_store_unordered(i32* %a) nounwind uwtable { entry: @@ -168,7 +168,7 @@ entry: ret void } ; CHECK: atomic32_store_unordered -; CHECK: call void @__tsan_atomic32_store(i32* %a, i32 0, i32 1) +; CHECK: call void @__tsan_atomic32_store(i32* %a, i32 0, i32 100501) define void @atomic32_store_monotonic(i32* %a) nounwind uwtable { entry: @@ -176,7 +176,7 @@ entry: ret void } ; CHECK: atomic32_store_monotonic -; CHECK: call void @__tsan_atomic32_store(i32* %a, i32 0, i32 1) +; CHECK: call void @__tsan_atomic32_store(i32* %a, i32 0, i32 100501) define void @atomic32_store_release(i32* %a) nounwind uwtable { entry: @@ -184,7 +184,7 @@ entry: ret void } ; CHECK: atomic32_store_release -; CHECK: call void @__tsan_atomic32_store(i32* %a, i32 0, i32 8) +; CHECK: call void @__tsan_atomic32_store(i32* %a, i32 0, i32 100508) define void @atomic32_store_seq_cst(i32* %a) nounwind uwtable { entry: @@ -192,7 +192,7 @@ entry: ret void } ; CHECK: atomic32_store_seq_cst -; CHECK: call void @__tsan_atomic32_store(i32* %a, i32 0, i32 32) +; CHECK: call void @__tsan_atomic32_store(i32* %a, i32 0, i32 100532) define i64 @atomic64_load_unordered(i64* %a) nounwind uwtable { entry: @@ -200,7 +200,7 @@ entry: ret i64 %0 } ; CHECK: atomic64_load_unordered -; CHECK: call i64 @__tsan_atomic64_load(i64* %a, i32 1) +; CHECK: call i64 @__tsan_atomic64_load(i64* %a, i32 100501) define i64 @atomic64_load_monotonic(i64* %a) nounwind uwtable { entry: @@ -208,7 +208,7 @@ entry: ret i64 %0 } ; CHECK: atomic64_load_monotonic -; CHECK: call i64 @__tsan_atomic64_load(i64* %a, i32 1) +; CHECK: call i64 @__tsan_atomic64_load(i64* %a, i32 100501) define i64 @atomic64_load_acquire(i64* %a) nounwind uwtable { entry: @@ -216,7 +216,7 @@ entry: ret i64 %0 } ; CHECK: atomic64_load_acquire -; CHECK: call i64 @__tsan_atomic64_load(i64* %a, i32 4) +; CHECK: call i64 @__tsan_atomic64_load(i64* %a, i32 100504) define i64 @atomic64_load_seq_cst(i64* %a) nounwind uwtable { entry: @@ -224,7 +224,7 @@ entry: ret i64 %0 } ; CHECK: atomic64_load_seq_cst -; CHECK: call i64 @__tsan_atomic64_load(i64* %a, i32 32) +; CHECK: call i64 @__tsan_atomic64_load(i64* %a, i32 100532) define void @atomic64_store_unordered(i64* %a) nounwind uwtable { entry: @@ -232,7 +232,7 @@ entry: ret void } ; CHECK: atomic64_store_unordered -; CHECK: call void @__tsan_atomic64_store(i64* %a, i64 0, i32 1) +; CHECK: call void @__tsan_atomic64_store(i64* %a, i64 0, i32 100501) define void @atomic64_store_monotonic(i64* %a) nounwind uwtable { entry: @@ -240,7 +240,7 @@ entry: ret void } ; CHECK: atomic64_store_monotonic -; CHECK: call void @__tsan_atomic64_store(i64* %a, i64 0, i32 1) +; CHECK: call void @__tsan_atomic64_store(i64* %a, i64 0, i32 100501) define void @atomic64_store_release(i64* %a) nounwind uwtable { entry: @@ -248,7 +248,7 @@ entry: ret void } ; CHECK: atomic64_store_release -; CHECK: call void @__tsan_atomic64_store(i64* %a, i64 0, i32 8) +; CHECK: call void @__tsan_atomic64_store(i64* %a, i64 0, i32 100508) define void @atomic64_store_seq_cst(i64* %a) nounwind uwtable { entry: @@ -256,7 +256,7 @@ entry: ret void } ; CHECK: atomic64_store_seq_cst -; CHECK: call void @__tsan_atomic64_store(i64* %a, i64 0, i32 32) +; CHECK: call void @__tsan_atomic64_store(i64* %a, i64 0, i32 100532) define i128 @atomic128_load_unordered(i128* %a) nounwind uwtable { entry: @@ -264,7 +264,7 @@ entry: ret i128 %0 } ; CHECK: atomic128_load_unordered -; CHECK: call i128 @__tsan_atomic128_load(i128* %a, i32 1) +; CHECK: call i128 @__tsan_atomic128_load(i128* %a, i32 100501) define i128 @atomic128_load_monotonic(i128* %a) nounwind uwtable { entry: @@ -272,7 +272,7 @@ entry: ret i128 %0 } ; CHECK: atomic128_load_monotonic -; CHECK: call i128 @__tsan_atomic128_load(i128* %a, i32 1) +; CHECK: call i128 @__tsan_atomic128_load(i128* %a, i32 100501) define i128 @atomic128_load_acquire(i128* %a) nounwind uwtable { entry: @@ -280,7 +280,7 @@ entry: ret i128 %0 } ; CHECK: atomic128_load_acquire -; CHECK: call i128 @__tsan_atomic128_load(i128* %a, i32 4) +; CHECK: call i128 @__tsan_atomic128_load(i128* %a, i32 100504) define i128 @atomic128_load_seq_cst(i128* %a) nounwind uwtable { entry: @@ -288,7 +288,7 @@ entry: ret i128 %0 } ; CHECK: atomic128_load_seq_cst -; CHECK: call i128 @__tsan_atomic128_load(i128* %a, i32 32) +; CHECK: call i128 @__tsan_atomic128_load(i128* %a, i32 100532) define void @atomic128_store_unordered(i128* %a) nounwind uwtable { entry: @@ -296,7 +296,7 @@ entry: ret void } ; CHECK: atomic128_store_unordered -; CHECK: call void @__tsan_atomic128_store(i128* %a, i128 0, i32 1) +; CHECK: call void @__tsan_atomic128_store(i128* %a, i128 0, i32 100501) define void @atomic128_store_monotonic(i128* %a) nounwind uwtable { entry: @@ -304,7 +304,7 @@ entry: ret void } ; CHECK: atomic128_store_monotonic -; CHECK: call void @__tsan_atomic128_store(i128* %a, i128 0, i32 1) +; CHECK: call void @__tsan_atomic128_store(i128* %a, i128 0, i32 100501) define void @atomic128_store_release(i128* %a) nounwind uwtable { entry: @@ -312,7 +312,7 @@ entry: ret void } ; CHECK: atomic128_store_release -; CHECK: call void @__tsan_atomic128_store(i128* %a, i128 0, i32 8) +; CHECK: call void @__tsan_atomic128_store(i128* %a, i128 0, i32 100508) define void @atomic128_store_seq_cst(i128* %a) nounwind uwtable { entry: @@ -320,4 +320,4 @@ entry: ret void } ; CHECK: atomic128_store_seq_cst -; CHECK: call void @__tsan_atomic128_store(i128* %a, i128 0, i32 32) +; CHECK: call void @__tsan_atomic128_store(i128* %a, i128 0, i32 100532) diff --git a/test/MC/ARM/diagnostics.s b/test/MC/ARM/diagnostics.s index ad4d9ab9b5e..d65cfd7a67a 100644 --- a/test/MC/ARM/diagnostics.s +++ b/test/MC/ARM/diagnostics.s @@ -361,3 +361,13 @@ @ CHECK-ERRORS: error: invalid operand for instruction @ CHECK-ERRORS: cps f,#1 @ CHECK-ERRORS: ^ + + @ Bad operands for msr + msr #0, #0 + msr foo, #0 +@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: msr #0, #0 +@ CHECK-ERRORS: ^ +@ CHECK-ERRORS: error: invalid operand for instruction +@ CHECK-ERRORS: msr foo, #0 +@ CHECK-ERRORS: ^ diff --git a/test/MC/Mips/mips-expansions.s b/test/MC/Mips/mips-expansions.s new file mode 100644 index 00000000000..cfc15e883a9 --- /dev/null +++ b/test/MC/Mips/mips-expansions.s @@ -0,0 +1,27 @@ +# RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding -mcpu=mips32r2 | FileCheck %s +# Check that the assembler can handle the documented syntax +# for macro instructions +# CHECK: .section __TEXT,__text,regular,pure_instructions +#------------------------------------------------------------------------------ +# Load immediate instructions +#------------------------------------------------------------------------------ +# CHECK: ori $5, $zero, 123 # encoding: [0x7b,0x00,0x05,0x34] +# CHECK: addiu $6, $zero, -2345 # encoding: [0xd7,0xf6,0x06,0x24] +# CHECK: lui $7, 1 # encoding: [0x01,0x00,0x07,0x3c] +# CHECK: ori $7, $7, 2 # encoding: [0x02,0x00,0xe7,0x34] +# CHECK: addiu $4, $zero, 20 # encoding: [0x14,0x00,0x04,0x24] +# CHECK: lui $7, 1 # encoding: [0x01,0x00,0x07,0x3c] +# CHECK: ori $7, $7, 2 # encoding: [0x02,0x00,0xe7,0x34] +# CHECK: addiu $4, $5, 20 # encoding: [0x14,0x00,0xa4,0x24] +# CHECK: lui $7, 1 # encoding: [0x01,0x00,0x07,0x3c] +# CHECK: ori $7, $7, 2 # encoding: [0x02,0x00,0xe7,0x34] +# CHECK: addu $7, $7, $8 # encoding: [0x21,0x38,0xe8,0x00] + + li $5,123 + li $6,-2345 + li $7,65538 + + la $a0, 20 + la $7,65538 + la $a0, 20($a1) + la $7,65538($8) diff --git a/test/MC/Mips/mips-fpu-instructions.s b/test/MC/Mips/mips-fpu-instructions.s index ce8024d45b5..a126c6f7188 100644 --- a/test/MC/Mips/mips-fpu-instructions.s +++ b/test/MC/Mips/mips-fpu-instructions.s @@ -149,6 +149,14 @@ # CHECK: mthi $7 # encoding: [0x11,0x00,0xe0,0x00] # CHECK: mtlo $7 # encoding: [0x13,0x00,0xe0,0x00] # CHECK: swc1 $f9, 9158($7) # encoding: [0xc6,0x23,0xe9,0xe4] +# CHECK: mfc0 $6, $7, 0 # encoding: [0x00,0x38,0x06,0x40] +# CHECK: mtc0 $9, $8, 0 # encoding: [0x00,0x40,0x89,0x40] +# CHECK: mfc2 $5, $7, 0 # encoding: [0x00,0x38,0x05,0x48] +# CHECK: mtc2 $9, $4, 0 # encoding: [0x00,0x20,0x89,0x48] +# CHECK: mfc0 $6, $7, 2 # encoding: [0x02,0x38,0x06,0x40] +# CHECK: mtc0 $9, $8, 3 # encoding: [0x03,0x40,0x89,0x40] +# CHECK: mfc2 $5, $7, 4 # encoding: [0x04,0x38,0x05,0x48] +# CHECK: mtc2 $9, $4, 5 # encoding: [0x05,0x20,0x89,0x48] cfc1 $a2,$0 mfc1 $a2,$f7 @@ -160,3 +168,11 @@ mthi $a3 mtlo $a3 swc1 $f9,9158($a3) + mfc0 $6, $7 + mtc0 $9, $8 + mfc2 $5, $7 + mtc2 $9, $4 + mfc0 $6, $7, 2 + mtc0 $9, $8, 3 + mfc2 $5, $7, 4 + mtc2 $9, $4, 5 diff --git a/test/MC/Mips/mips_directives.s b/test/MC/Mips/mips_directives.s index f9d846078bf..e2f75a827d0 100644 --- a/test/MC/Mips/mips_directives.s +++ b/test/MC/Mips/mips_directives.s @@ -1,10 +1,16 @@ # RUN: llvm-mc -triple mips-unknown-unknown %s - +#this test produces no output so there isS no FileCheck call $BB0_2: + .ent directives_test .frame $sp,0,$ra .mask 0x00000000,0 .fmask 0x00000000,0 .set noreorder .set nomacro + .set noat $JTI0_0: .gpword ($BB0_2) + .set at=$12 + .set macro + .set reorder + .end directives_test diff --git a/test/Makefile b/test/Makefile index ae7a67401f3..3c6b5b68a4f 100644 --- a/test/Makefile +++ b/test/Makefile @@ -29,11 +29,6 @@ else LIT_ARGS := -s -v endif -# -jN causes crash on Cygwin's python. -ifneq (,$(filter $(HOST_OS),Cygwin)) - LIT_ARGS += -j1 -endif - ifdef TESTSUITE LIT_TESTSUITE := $(TESTSUITE) CLEANED_TESTSUITE := $(patsubst %/,%,$(TESTSUITE)) diff --git a/test/Other/ResponseFile.ll b/test/Other/ResponseFile.ll new file mode 100644 index 00000000000..b8b3d0a9023 --- /dev/null +++ b/test/Other/ResponseFile.ll @@ -0,0 +1,9 @@ +; RUN: echo %s > %t.list +; RUN: llvm-as @%t.list -o %t.bc +; RUN: llvm-nm %t.bc 2>&1 | FileCheck %s + +; CHECK: T foobar + +define void @foobar() { + ret void +} diff --git a/test/Transforms/DeadArgElim/dbginfo.ll b/test/Transforms/DeadArgElim/dbginfo.ll new file mode 100644 index 00000000000..dcbfaaa3d77 --- /dev/null +++ b/test/Transforms/DeadArgElim/dbginfo.ll @@ -0,0 +1,64 @@ +; RUN: opt %s -deadargelim -S | FileCheck %s +; PR14016 + +; Check that debug info metadata for subprograms stores pointers to +; updated LLVM functions. + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +@x = global i32 0, align 4 + +define void @_Z3runv() uwtable { +entry: + call void @_ZN12_GLOBAL__N_18dead_argEPv(i8* null), !dbg !10 + call void (...)* @_ZN12_GLOBAL__N_111dead_varargEz(), !dbg !12 + ret void, !dbg !13 +} + +; Argument will be deleted +define internal void @_ZN12_GLOBAL__N_18dead_argEPv(i8* %foo) nounwind uwtable { +entry: + %0 = load i32* @x, align 4, !dbg !14 + %inc = add nsw i32 %0, 1, !dbg !14 + store i32 %inc, i32* @x, align 4, !dbg !14 + ret void, !dbg !16 +} + +; Vararg will be deleted +define internal void @_ZN12_GLOBAL__N_111dead_varargEz(...) nounwind uwtable { +entry: + %0 = load i32* @x, align 4, !dbg !17 + %inc = add nsw i32 %0, 1, !dbg !17 + store i32 %inc, i32* @x, align 4, !dbg !17 + ret void, !dbg !19 +} + +!llvm.dbg.cu = !{!0} + +!0 = metadata !{i32 786449, i32 0, i32 4, metadata !"test.cc", metadata !"/home/samsonov/tmp/clang-di", metadata !"clang version 3.2 (trunk 165305)", i1 true, i1 false, metadata !"", i32 0, metadata !1, metadata !1, metadata !3, metadata !1} ; [ DW_TAG_compile_unit ] [/home/samsonov/tmp/clang-di/test.cc] [DW_LANG_C_plus_plus] +!1 = metadata !{metadata !2} +!2 = metadata !{i32 0} +!3 = metadata !{metadata !4} +!4 = metadata !{metadata !5, metadata !8, metadata !9} +!5 = metadata !{i32 786478, i32 0, metadata !6, metadata !"run", metadata !"run", metadata !"", metadata !6, i32 8, metadata !7, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 false, void ()* @_Z3runv, null, null, metadata !1, i32 8} ; [ DW_TAG_subprogram ] [line 8] [def] [run] +!6 = metadata !{i32 786473, metadata !"test.cc", metadata !"/home/samsonov/tmp/clang-di", null} ; [ DW_TAG_file_type ] +!7 = metadata !{i32 786453, i32 0, metadata !"", i32 0, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !2, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!8 = metadata !{i32 786478, i32 0, metadata !6, metadata !"dead_vararg", metadata !"dead_vararg", metadata !"", metadata !6, i32 5, metadata !7, i1 true, i1 true, i32 0, i32 0, null, i32 256, i1 false, void (...)* @_ZN12_GLOBAL__N_111dead_varargEz, null, null, metadata !1, i32 5} ; [ DW_TAG_subprogram ] [line 5] [local] [def] [dead_vararg] + +; CHECK: metadata !"dead_vararg"{{.*}}void ()* @_ZN12_GLOBAL__N_111dead_varargEz + +!9 = metadata !{i32 786478, i32 0, metadata !6, metadata !"dead_arg", metadata !"dead_arg", metadata !"", metadata !6, i32 4, metadata !7, i1 true, i1 true, i32 0, i32 0, null, i32 256, i1 false, void (i8*)* @_ZN12_GLOBAL__N_18dead_argEPv, null, null, metadata !1, i32 4} ; [ DW_TAG_subprogram ] [line 4] [local] [def] [dead_arg] + +; CHECK: metadata !"dead_arg"{{.*}}void ()* @_ZN12_GLOBAL__N_18dead_argEPv + +!10 = metadata !{i32 8, i32 14, metadata !11, null} +!11 = metadata !{i32 786443, metadata !5, i32 8, i32 12, metadata !6, i32 0} ; [ DW_TAG_lexical_block ] [/home/samsonov/tmp/clang-di/test.cc] +!12 = metadata !{i32 8, i32 27, metadata !11, null} +!13 = metadata !{i32 8, i32 42, metadata !11, null} +!14 = metadata !{i32 4, i32 28, metadata !15, null} +!15 = metadata !{i32 786443, metadata !9, i32 4, i32 26, metadata !6, i32 2} ; [ DW_TAG_lexical_block ] [/home/samsonov/tmp/clang-di/test.cc] +!16 = metadata !{i32 4, i32 33, metadata !15, null} +!17 = metadata !{i32 5, i32 25, metadata !18, null} +!18 = metadata !{i32 786443, metadata !8, i32 5, i32 23, metadata !6, i32 1} ; [ DW_TAG_lexical_block ] [/home/samsonov/tmp/clang-di/test.cc] +!19 = metadata !{i32 5, i32 30, metadata !18, null} diff --git a/test/Transforms/EarlyCSE/commute.ll b/test/Transforms/EarlyCSE/commute.ll new file mode 100644 index 00000000000..f84a7dd1aae --- /dev/null +++ b/test/Transforms/EarlyCSE/commute.ll @@ -0,0 +1,66 @@ +; RUN: opt < %s -S -early-cse | FileCheck %s + +; CHECK: @test1 +define void @test1(float %A, float %B, float* %PA, float* %PB) { + ; CHECK-NEXT: fadd + ; CHECK-NEXT: store + ; CHECK-NEXT: store + ; CHECK-NEXT: ret + %C = fadd float %A, %B + store float %C, float* %PA + %D = fadd float %B, %A + store float %D, float* %PB + ret void +} + +; CHECK: @test2 +define void @test2(float %A, float %B, i1* %PA, i1* %PB) { + ; CHECK-NEXT: fcmp + ; CHECK-NEXT: store + ; CHECK-NEXT: store + ; CHECK-NEXT: ret + %C = fcmp eq float %A, %B + store i1 %C, i1* %PA + %D = fcmp eq float %B, %A + store i1 %D, i1* %PB + ret void +} + +; CHECK: @test3 +define void @test3(float %A, float %B, i1* %PA, i1* %PB) { + ; CHECK-NEXT: fcmp + ; CHECK-NEXT: store + ; CHECK-NEXT: store + ; CHECK-NEXT: ret + %C = fcmp uge float %A, %B + store i1 %C, i1* %PA + %D = fcmp ule float %B, %A + store i1 %D, i1* %PB + ret void +} + +; CHECK: @test4 +define void @test4(i32 %A, i32 %B, i1* %PA, i1* %PB) { + ; CHECK-NEXT: icmp + ; CHECK-NEXT: store + ; CHECK-NEXT: store + ; CHECK-NEXT: ret + %C = icmp eq i32 %A, %B + store i1 %C, i1* %PA + %D = icmp eq i32 %B, %A + store i1 %D, i1* %PB + ret void +} + +; CHECK: @test5 +define void @test5(i32 %A, i32 %B, i1* %PA, i1* %PB) { + ; CHECK-NEXT: icmp + ; CHECK-NEXT: store + ; CHECK-NEXT: store + ; CHECK-NEXT: ret + %C = icmp sgt i32 %A, %B + store i1 %C, i1* %PA + %D = icmp slt i32 %B, %A + store i1 %D, i1* %PB + ret void +} diff --git a/test/Transforms/IndVarSimplify/2004-04-05-InvokeCastCrash.ll b/test/Transforms/IndVarSimplify/2004-04-05-InvokeCastCrash.ll index 708a961272b..0c88e83975c 100644 --- a/test/Transforms/IndVarSimplify/2004-04-05-InvokeCastCrash.ll +++ b/test/Transforms/IndVarSimplify/2004-04-05-InvokeCastCrash.ll @@ -39,11 +39,11 @@ %"struct.llvm::SymbolTable" = type opaque %"struct.llvm::SymbolTableListTraits<llvm::Argument,llvm::Function,llvm::Function,llvm::ilist_traits<llvm::Argument> >" = type { %"struct.llvm::Function"*, %"struct.llvm::Function"* } %"struct.llvm::SymbolTableListTraits<llvm::Instruction,llvm::BasicBlock,llvm::Function,llvm::ilist_traits<llvm::Instruction> >" = type { %"struct.llvm::Function"*, %"struct.llvm::BasicBlock"* } - %"struct.llvm::TargetData" = type { %"struct.llvm::FunctionPass", i1, i8, i8, i8, i8, i8, i8, i8, i8 } + %"struct.llvm::DataLayout" = type { %"struct.llvm::FunctionPass", i1, i8, i8, i8, i8, i8, i8, i8, i8 } %"struct.llvm::TargetFrameInfo" = type { i32 (...)**, i32, i32, i32 } %"struct.llvm::TargetInstrDescriptor" = type { i8*, i32, i32, i32, i1, i32, i32, i32, i32, i32, i32*, i32* } %"struct.llvm::TargetInstrInfo" = type { i32 (...)**, %"struct.llvm::TargetInstrDescriptor"*, i32, i32 } - %"struct.llvm::TargetMachine" = type { i32 (...)**, %"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >", %"struct.llvm::TargetData", %"struct.llvm::IntrinsicLowering"* } + %"struct.llvm::TargetMachine" = type { i32 (...)**, %"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >", %"struct.llvm::DataLayout", %"struct.llvm::IntrinsicLowering"* } %"struct.llvm::TargetRegClassInfo" = type { i32 (...)**, i32, i32, i32 } %"struct.llvm::TargetRegInfo" = type { i32 (...)**, %"struct.std::vector<const llvm::TargetRegClassInfo*,std::allocator<const llvm::TargetRegClassInfo*> >", %"struct.llvm::TargetMachine"* } %"struct.llvm::Type" = type { %"struct.llvm::Value", i32, i32, i1, i32, %"struct.llvm::Type"*, %"struct.std::vector<llvm::PATypeHandle,std::allocator<llvm::PATypeHandle> >" } diff --git a/test/Transforms/IndVarSimplify/crash.ll b/test/Transforms/IndVarSimplify/crash.ll index 3335be781df..62af42b9d68 100644 --- a/test/Transforms/IndVarSimplify/crash.ll +++ b/test/Transforms/IndVarSimplify/crash.ll @@ -87,3 +87,29 @@ entry: main.f.exit: ; preds = %"3.i" unreachable } + + +; PR13967 + +define void @f() nounwind ssp { +bb: + br label %bb4 + +bb4: + %tmp = phi i64 [ %tmp5, %bb7 ], [ undef, %bb ] + %tmp5 = add nsw i64 %tmp, 1 + %extract.t1 = trunc i64 %tmp5 to i32 + br i1 false, label %bb6, label %bb7 + +bb6: + br label %bb7 + +bb7: + %.off0 = phi i32 [ undef, %bb6 ], [ %extract.t1, %bb4 ] + %tmp8 = icmp eq i32 %.off0, 0 + br i1 %tmp8, label %bb9, label %bb4 + +bb9: + ret void +} + diff --git a/test/Transforms/InstCombine/align-addr.ll b/test/Transforms/InstCombine/align-addr.ll index 27916b98603..4ea1bd9beb3 100644 --- a/test/Transforms/InstCombine/align-addr.ll +++ b/test/Transforms/InstCombine/align-addr.ll @@ -58,3 +58,19 @@ define double @test2(double* %p, double %n) nounwind { store double %n, double* %p ret double %t } + +declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) nounwind + +declare void @use(i8*) + +%struct.s = type { i32, i32, i32, i32 } + +define void @test3(%struct.s* sret %a4) { +; Check that the alignment is bumped up the alignment of the sret type. +; CHECK: @test3 + %a4.cast = bitcast %struct.s* %a4 to i8* + call void @llvm.memset.p0i8.i64(i8* %a4.cast, i8 0, i64 16, i32 1, i1 false) +; CHECK: call void @llvm.memset.p0i8.i64(i8* %a4.cast, i8 0, i64 16, i32 4, i1 false) + call void @use(i8* %a4.cast) + ret void +} diff --git a/test/Transforms/InstCombine/and-fcmp.ll b/test/Transforms/InstCombine/and-fcmp.ll index 838c2f73fb9..40c44c09a8c 100644 --- a/test/Transforms/InstCombine/and-fcmp.ll +++ b/test/Transforms/InstCombine/and-fcmp.ll @@ -10,7 +10,7 @@ define zeroext i8 @t1(float %x, float %y) nounwind { ; CHECK: fcmp oeq float %x, %y ; CHECK-NOT: fcmp ueq float %x, %y ; CHECK-NOT: fcmp ord float %x, %y -; CHECK-NOW: and +; CHECK-NOT: and } define zeroext i8 @t2(float %x, float %y) nounwind { diff --git a/test/Transforms/MemCpyOpt/2008-03-13-ReturnSlotBitcast.ll b/test/Transforms/MemCpyOpt/2008-03-13-ReturnSlotBitcast.ll index 61ba3c7e6cc..597b69dee3d 100644 --- a/test/Transforms/MemCpyOpt/2008-03-13-ReturnSlotBitcast.ll +++ b/test/Transforms/MemCpyOpt/2008-03-13-ReturnSlotBitcast.ll @@ -9,11 +9,11 @@ declare void @g(%a*) define float @f() { entry: %a_var = alloca %a - %b_var = alloca %b + %b_var = alloca %b, align 1 call void @g(%a* %a_var) %a_i8 = bitcast %a* %a_var to i8* %b_i8 = bitcast %b* %b_var to i8* - call void @llvm.memcpy.p0i8.p0i8.i32(i8* %b_i8, i8* %a_i8, i32 4, i32 4, i1 false) + call void @llvm.memcpy.p0i8.p0i8.i32(i8* %b_i8, i8* %a_i8, i32 4, i32 1, i1 false) %tmp1 = getelementptr %b* %b_var, i32 0, i32 0 %tmp2 = load float* %tmp1 ret float %tmp2 diff --git a/test/Transforms/MemCpyOpt/align.ll b/test/Transforms/MemCpyOpt/align.ll index b1f900d9da4..1b98f6ad383 100644 --- a/test/Transforms/MemCpyOpt/align.ll +++ b/test/Transforms/MemCpyOpt/align.ll @@ -1,12 +1,15 @@ -; RUN: opt < %s -S -memcpyopt | FileCheck %s +; RUN: opt < %s -S -basicaa -memcpyopt | FileCheck %s target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" +declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) nounwind +declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) nounwind + ; The resulting memset is only 4-byte aligned, despite containing ; a 16-byte aligned store in the middle. -; CHECK: call void @llvm.memset.p0i8.i64(i8* {{.*}}, i8 0, i64 16, i32 4, i1 false) - define void @foo(i32* %p) { +; CHECK: @foo +; CHECK: call void @llvm.memset.p0i8.i64(i8* {{.*}}, i8 0, i64 16, i32 4, i1 false) %a0 = getelementptr i32* %p, i64 0 store i32 0, i32* %a0, align 4 %a1 = getelementptr i32* %p, i64 1 @@ -17,3 +20,18 @@ define void @foo(i32* %p) { store i32 0, i32* %a3, align 4 ret void } + +; Replacing %a8 with %a4 in the memset requires boosting the alignment of %a4. + +define void @bar() { +; CHECK: @bar +; CHECK: %a4 = alloca i32, align 8 +; CHECK-NOT: memcpy + %a4 = alloca i32, align 4 + %a8 = alloca i32, align 8 + %a8.cast = bitcast i32* %a8 to i8* + %a4.cast = bitcast i32* %a4 to i8* + call void @llvm.memset.p0i8.i64(i8* %a8.cast, i8 0, i64 4, i32 8, i1 false) + call void @llvm.memcpy.p0i8.p0i8.i64(i8* %a4.cast, i8* %a8.cast, i64 4, i32 4, i1 false) + ret void +} diff --git a/test/Transforms/SROA/alignment.ll b/test/Transforms/SROA/alignment.ll index 4f35a8a0ee3..945ad910021 100644 --- a/test/Transforms/SROA/alignment.ll +++ b/test/Transforms/SROA/alignment.ll @@ -1,5 +1,5 @@ ; RUN: opt < %s -sroa -S | FileCheck %s -target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n8:16:32:64" +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n8:16:32:64" declare void @llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1) @@ -31,8 +31,8 @@ entry: define void @test2() { ; CHECK: @test2 ; CHECK: alloca i16 -; CHECK: load i8* %{{.*}}, align 1 -; CHECK: store i8 42, i8* %{{.*}}, align 1 +; CHECK: load i8* %{{.*}} +; CHECK: store i8 42, i8* %{{.*}} ; CHECK: ret void entry: @@ -41,8 +41,8 @@ entry: %cast1 = bitcast i8* %gep1 to i16* store volatile i16 0, i16* %cast1 %gep2 = getelementptr { i8, i8, i8, i8 }* %a, i32 0, i32 2 - %result = load i8* %gep2, align 2 - store i8 42, i8* %gep2, align 2 + %result = load i8* %gep2 + store i8 42, i8* %gep2 ret void } @@ -114,3 +114,89 @@ entry: ret void } + +define void @test5() { +; Test that we preserve underaligned loads and stores when splitting. +; CHECK: @test5 +; CHECK: alloca [9 x i8] +; CHECK: alloca [9 x i8] +; CHECK: store volatile double 0.0{{.*}}, double* %{{.*}}, align 1 +; CHECK: load i16* %{{.*}}, align 1 +; CHECK: load double* %{{.*}}, align 1 +; CHECK: store volatile double %{{.*}}, double* %{{.*}}, align 1 +; CHECK: load i16* %{{.*}}, align 1 +; CHECK: ret void + +entry: + %a = alloca [18 x i8] + %raw1 = getelementptr inbounds [18 x i8]* %a, i32 0, i32 0 + %ptr1 = bitcast i8* %raw1 to double* + store volatile double 0.0, double* %ptr1, align 1 + %weird_gep1 = getelementptr inbounds [18 x i8]* %a, i32 0, i32 7 + %weird_cast1 = bitcast i8* %weird_gep1 to i16* + %weird_load1 = load i16* %weird_cast1, align 1 + + %raw2 = getelementptr inbounds [18 x i8]* %a, i32 0, i32 9 + %ptr2 = bitcast i8* %raw2 to double* + %d1 = load double* %ptr1, align 1 + store volatile double %d1, double* %ptr2, align 1 + %weird_gep2 = getelementptr inbounds [18 x i8]* %a, i32 0, i32 16 + %weird_cast2 = bitcast i8* %weird_gep2 to i16* + %weird_load2 = load i16* %weird_cast2, align 1 + + ret void +} + +define void @test6() { +; Test that we promote alignment when the underlying alloca switches to one +; that innately provides it. +; CHECK: @test6 +; CHECK: alloca double +; CHECK: alloca double +; CHECK-NOT: align +; CHECK: ret void + +entry: + %a = alloca [16 x i8] + %raw1 = getelementptr inbounds [16 x i8]* %a, i32 0, i32 0 + %ptr1 = bitcast i8* %raw1 to double* + store volatile double 0.0, double* %ptr1, align 1 + + %raw2 = getelementptr inbounds [16 x i8]* %a, i32 0, i32 8 + %ptr2 = bitcast i8* %raw2 to double* + %val = load double* %ptr1, align 1 + store volatile double %val, double* %ptr2, align 1 + + ret void +} + +define void @test7(i8* %out) { +; Test that we properly compute the destination alignment when rewriting +; memcpys as direct loads or stores. +; CHECK: @test7 +; CHECK-NOT: alloca + +entry: + %a = alloca [16 x i8] + %raw1 = getelementptr inbounds [16 x i8]* %a, i32 0, i32 0 + %ptr1 = bitcast i8* %raw1 to double* + %raw2 = getelementptr inbounds [16 x i8]* %a, i32 0, i32 8 + %ptr2 = bitcast i8* %raw2 to double* + + call void @llvm.memcpy.p0i8.p0i8.i32(i8* %raw1, i8* %out, i32 16, i32 0, i1 false) +; CHECK: %[[val2:.*]] = load double* %{{.*}}, align 1 +; CHECK: %[[val1:.*]] = load double* %{{.*}}, align 1 + + %val1 = load double* %ptr2, align 1 + %val2 = load double* %ptr1, align 1 + + store double %val1, double* %ptr1, align 1 + store double %val2, double* %ptr2, align 1 + + call void @llvm.memcpy.p0i8.p0i8.i32(i8* %out, i8* %raw1, i32 16, i32 0, i1 false) +; CHECK: store double %[[val1]], double* %{{.*}}, align 1 +; CHECK: store double %[[val2]], double* %{{.*}}, align 1 + + ret void +; CHECK: ret void +} diff --git a/test/Transforms/SROA/basictest.ll b/test/Transforms/SROA/basictest.ll index e58cef63bad..e7767ef5e96 100644 --- a/test/Transforms/SROA/basictest.ll +++ b/test/Transforms/SROA/basictest.ll @@ -1,7 +1,7 @@ ; RUN: opt < %s -sroa -S | FileCheck %s ; RUN: opt < %s -sroa -force-ssa-updater -S | FileCheck %s -target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n8:16:32:64" +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n8:16:32:64" declare void @llvm.lifetime.start(i64, i8* nocapture) declare void @llvm.lifetime.end(i64, i8* nocapture) @@ -862,8 +862,7 @@ define void @PR13916.1() { ; Ensure that we handle overlapping memcpy intrinsics correctly, especially in ; the case where there is a directly identical value for both source and dest. ; CHECK: @PR13916.1 -; FIXME: We shouldn't leave this alloca around. -; CHECK: alloca +; CHECK-NOT: alloca ; CHECK: ret void entry: @@ -878,8 +877,7 @@ define void @PR13916.2() { ; different pointer value chains, but during rewriting we coalesce them into the ; same value. ; CHECK: @PR13916.2 -; FIXME: We shouldn't leave this alloca around. -; CHECK: alloca +; CHECK-NOT: alloca ; CHECK: ret void entry: @@ -897,3 +895,76 @@ if.end: %tmp2 = load i8* %gep ret void } + +define void @PR13990() { +; Ensure we can handle cases where processing one alloca causes the other +; alloca to become dead and get deleted. This might crash or fail under +; Valgrind if we regress. +; CHECK: @PR13990 +; CHECK-NOT: alloca +; CHECK: unreachable +; CHECK: unreachable + +entry: + %tmp1 = alloca i8* + %tmp2 = alloca i8* + br i1 undef, label %bb1, label %bb2 + +bb1: + store i8* undef, i8** %tmp2 + br i1 undef, label %bb2, label %bb3 + +bb2: + %tmp50 = select i1 undef, i8** %tmp2, i8** %tmp1 + br i1 undef, label %bb3, label %bb4 + +bb3: + unreachable + +bb4: + unreachable +} + +define double @PR13969(double %x) { +; Check that we detect when promotion will un-escape an alloca and iterate to +; re-try running SROA over that alloca. Without that, the two allocas that are +; stored into a dead alloca don't get rewritten and promoted. +; CHECK: @PR13969 + +entry: + %a = alloca double + %b = alloca double* + %c = alloca double +; CHECK-NOT: alloca + + store double %x, double* %a + store double* %c, double** %b + store double* %a, double** %b + store double %x, double* %c + %ret = load double* %a +; CHECK-NOT: store +; CHECK-NOT: load + + ret double %ret +; CHECK: ret double %x +} + +%PR14034.struct = type { { {} }, i32, %PR14034.list } +%PR14034.list = type { %PR14034.list*, %PR14034.list* } + +define void @PR14034() { +; This test case tries to form GEPs into the empty leading struct members, and +; subsequently crashed (under valgrind) before we fixed the PR. The important +; thing is to handle empty structs gracefully. +; CHECK: @PR14034 + +entry: + %a = alloca %PR14034.struct + %list = getelementptr %PR14034.struct* %a, i32 0, i32 2 + %prev = getelementptr %PR14034.list* %list, i32 0, i32 1 + store %PR14034.list* undef, %PR14034.list** %prev + %cast0 = bitcast %PR14034.struct* undef to i8* + %cast1 = bitcast %PR14034.struct* %a to i8* + call void @llvm.memcpy.p0i8.p0i8.i32(i8* %cast0, i8* %cast1, i32 12, i32 0, i1 false) + ret void +} diff --git a/test/Transforms/SROA/big-endian.ll b/test/Transforms/SROA/big-endian.ll new file mode 100644 index 00000000000..532f8690cf9 --- /dev/null +++ b/test/Transforms/SROA/big-endian.ll @@ -0,0 +1,108 @@ +; RUN: opt < %s -sroa -S | FileCheck %s +; RUN: opt < %s -sroa -force-ssa-updater -S | FileCheck %s + +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n8:16:32:64" + +define i8 @test1() { +; We fully promote these to the i24 load or store size, resulting in just masks +; and other operations that instcombine will fold, but no alloca. Note this is +; the same as test12 in basictest.ll, but here we assert big-endian byte +; ordering. +; +; CHECK: @test1 + +entry: + %a = alloca [3 x i8] + %b = alloca [3 x i8] +; CHECK-NOT: alloca + + %a0ptr = getelementptr [3 x i8]* %a, i64 0, i32 0 + store i8 0, i8* %a0ptr + %a1ptr = getelementptr [3 x i8]* %a, i64 0, i32 1 + store i8 0, i8* %a1ptr + %a2ptr = getelementptr [3 x i8]* %a, i64 0, i32 2 + store i8 0, i8* %a2ptr + %aiptr = bitcast [3 x i8]* %a to i24* + %ai = load i24* %aiptr +; CHCEK-NOT: store +; CHCEK-NOT: load +; CHECK: %[[mask0:.*]] = and i24 undef, 65535 +; CHECK-NEXT: %[[mask1:.*]] = and i24 %[[mask0]], -65281 +; CHECK-NEXT: %[[mask2:.*]] = and i24 %[[mask1]], -256 + + %biptr = bitcast [3 x i8]* %b to i24* + store i24 %ai, i24* %biptr + %b0ptr = getelementptr [3 x i8]* %b, i64 0, i32 0 + %b0 = load i8* %b0ptr + %b1ptr = getelementptr [3 x i8]* %b, i64 0, i32 1 + %b1 = load i8* %b1ptr + %b2ptr = getelementptr [3 x i8]* %b, i64 0, i32 2 + %b2 = load i8* %b2ptr +; CHCEK-NOT: store +; CHCEK-NOT: load +; CHECK: %[[shift0:.*]] = lshr i24 %[[mask2]], 16 +; CHECK-NEXT: %[[trunc0:.*]] = trunc i24 %[[shift0]] to i8 +; CHECK-NEXT: %[[shift1:.*]] = lshr i24 %[[mask2]], 8 +; CHECK-NEXT: %[[trunc1:.*]] = trunc i24 %[[shift1]] to i8 +; CHECK-NEXT: %[[trunc2:.*]] = trunc i24 %[[mask2]] to i8 + + %bsum0 = add i8 %b0, %b1 + %bsum1 = add i8 %bsum0, %b2 + ret i8 %bsum1 +; CHECK: %[[sum0:.*]] = add i8 %[[trunc0]], %[[trunc1]] +; CHECK-NEXT: %[[sum1:.*]] = add i8 %[[sum0]], %[[trunc2]] +; CHECK-NEXT: ret i8 %[[sum1]] +} + +define i64 @test2() { +; Test for various mixed sizes of integer loads and stores all getting +; promoted. +; +; CHECK: @test2 + +entry: + %a = alloca [7 x i8] +; CHECK-NOT: alloca + + %a0ptr = getelementptr [7 x i8]* %a, i64 0, i32 0 + %a1ptr = getelementptr [7 x i8]* %a, i64 0, i32 1 + %a2ptr = getelementptr [7 x i8]* %a, i64 0, i32 2 + %a3ptr = getelementptr [7 x i8]* %a, i64 0, i32 3 + +; CHCEK-NOT: store +; CHCEK-NOT: load + + %a0i16ptr = bitcast i8* %a0ptr to i16* + store i16 1, i16* %a0i16ptr +; CHECK: %[[mask:.*]] = and i56 undef, 1099511627775 +; CHECK-NEXT: %[[or:.*]] = or i56 %[[mask]], 1099511627776 + + %a1i4ptr = bitcast i8* %a1ptr to i4* + store i4 1, i4* %a1i4ptr +; CHECK: %[[mask:.*]] = and i56 %[[or]], -16492674416641 +; CHECK-NEXT: %[[or:.*]] = or i56 %[[mask]], 1099511627776 + + store i8 1, i8* %a2ptr +; CHECK-NEXT: %[[mask:.*]] = and i56 %[[or]], -1095216660481 +; CHECK-NEXT: %[[or:.*]] = or i56 %[[mask]], 4294967296 + + %a3i24ptr = bitcast i8* %a3ptr to i24* + store i24 1, i24* %a3i24ptr +; CHECK-NEXT: %[[mask:.*]] = and i56 %[[or]], -4294967041 +; CHECK-NEXT: %[[or:.*]] = or i56 %[[mask]], 256 + + %a2i40ptr = bitcast i8* %a2ptr to i40* + store i40 1, i40* %a2i40ptr +; CHECK-NEXT: %[[mask:.*]] = and i56 %[[or]], -1099511627776 +; CHECK-NEXT: %[[or:.*]] = or i56 %[[mask]], 1 + +; CHCEK-NOT: store +; CHCEK-NOT: load + + %aiptr = bitcast [7 x i8]* %a to i56* + %ai = load i56* %aiptr + %ret = zext i56 %ai to i64 + ret i64 %ret +; CHECK: %[[ret:.*]] = zext i56 %[[or]] to i64 +; CHECK-NEXT: ret i64 %[[ret]] +} diff --git a/test/Transforms/SROA/fca.ll b/test/Transforms/SROA/fca.ll index 6ddaed2f30c..c30a5cc974f 100644 --- a/test/Transforms/SROA/fca.ll +++ b/test/Transforms/SROA/fca.ll @@ -1,6 +1,6 @@ ; RUN: opt < %s -sroa -S | FileCheck %s ; RUN: opt < %s -sroa -force-ssa-updater -S | FileCheck %s -target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n8:16:32:64" +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n8:16:32:64" define { i32, i32 } @test0(i32 %x, i32 %y) { ; CHECK: @test0 diff --git a/test/Transforms/SROA/phi-and-select.ll b/test/Transforms/SROA/phi-and-select.ll index 6f5833a772f..2b0724c7fd4 100644 --- a/test/Transforms/SROA/phi-and-select.ll +++ b/test/Transforms/SROA/phi-and-select.ll @@ -1,5 +1,5 @@ ; RUN: opt < %s -sroa -S | FileCheck %s -target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n8:16:32:64" +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n8:16:32:64" define i32 @test1() { ; CHECK: @test1 diff --git a/test/Transforms/SROA/vector-promotion.ll b/test/Transforms/SROA/vector-promotion.ll index 9cbab385c21..80757475a5d 100644 --- a/test/Transforms/SROA/vector-promotion.ll +++ b/test/Transforms/SROA/vector-promotion.ll @@ -1,5 +1,5 @@ ; RUN: opt < %s -sroa -S | FileCheck %s -target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n8:16:32:64" +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n8:16:32:64" %S1 = type { i64, [42 x float] } diff --git a/test/Transforms/SimplifyCFG/phi-undef-loadstore.ll b/test/Transforms/SimplifyCFG/phi-undef-loadstore.ll index 65d888ea01e..028fb074563 100644 --- a/test/Transforms/SimplifyCFG/phi-undef-loadstore.ll +++ b/test/Transforms/SimplifyCFG/phi-undef-loadstore.ll @@ -85,3 +85,31 @@ if.end7: ; preds = %if.else, %if.then4, ; CHECK: if.end7: ; CHECK: phi i32* [ %a, %if.then ], [ null, %if.then4 ], [ null, %if.else ] } + +define i32 @test4(i32* %a, i32 %b, i32* %c, i32 %d) nounwind { +entry: + %tobool = icmp eq i32 %b, 0 + br i1 %tobool, label %if.else, label %if.then + +if.then: ; preds = %entry + tail call void @bar() nounwind + br label %if.end7 + +if.else: ; preds = %entry + %tobool3 = icmp eq i32 %d, 0 + br i1 %tobool3, label %if.end7, label %if.then4 + +if.then4: ; preds = %if.else + tail call void @bar() nounwind + br label %if.end7 + +if.end7: ; preds = %if.else, %if.then4, %if.then + %x.0 = phi i32* [ %a, %if.then ], [ null, %if.then4 ], [ null, %if.else ] + %gep = getelementptr i32* %x.0, i32 10 + %tmp9 = load i32* %gep + %tmp10 = or i32 %tmp9, 1 + store i32 %tmp10, i32* %gep + ret i32 %tmp9 +; CHECK: @test4 +; CHECK-NOT: phi +} diff --git a/test/lit.cfg b/test/lit.cfg index b7c5f3ef38c..dc37317ba95 100644 --- a/test/lit.cfg +++ b/test/lit.cfg @@ -139,6 +139,13 @@ if config.test_exec_root is None: ### +# Provide a target triple for mcjit tests +mcjit_triple = config.target_triple +# Force ELF format on Windows +if re.search(r'cygwin|mingw32|win32', mcjit_triple): + mcjit_triple += "-elf" +config.substitutions.append( ('%mcjit_triple', mcjit_triple) ) + # When running under valgrind, we mangle '-vg' or '-vg_leak' onto the end of the # triple so we can check it with XFAIL and XTARGET. config.target_triple += lit.valgrindTriple |