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Diffstat (limited to 'lib/Target/R600/SIFixSGPRCopies.cpp')
-rw-r--r--lib/Target/R600/SIFixSGPRCopies.cpp17
1 files changed, 10 insertions, 7 deletions
diff --git a/lib/Target/R600/SIFixSGPRCopies.cpp b/lib/Target/R600/SIFixSGPRCopies.cpp
index f6b8b783d02..5f714535abe 100644
--- a/lib/Target/R600/SIFixSGPRCopies.cpp
+++ b/lib/Target/R600/SIFixSGPRCopies.cpp
@@ -259,14 +259,17 @@ bool SIFixSGPRCopies::runOnMachineFunction(MachineFunction &MF) {
break;
}
case AMDGPU::INSERT_SUBREG: {
- const TargetRegisterClass *DstRC, *SrcRC;
+ const TargetRegisterClass *DstRC, *Src0RC, *Src1RC;
DstRC = MRI.getRegClass(MI.getOperand(0).getReg());
- SrcRC = MRI.getRegClass(MI.getOperand(1).getReg());
- if (!TRI->isSGPRClass(DstRC) || !TRI->hasVGPRs(SrcRC))
- break;
- DEBUG(dbgs() << " Fixing INSERT_SUBREG:\n");
- DEBUG(MI.print(dbgs()));
- TII->moveToVALU(MI);
+ Src0RC = MRI.getRegClass(MI.getOperand(1).getReg());
+ Src1RC = MRI.getRegClass(MI.getOperand(2).getReg());
+ if (TRI->isSGPRClass(DstRC) &&
+ (TRI->hasVGPRs(Src0RC) || TRI->hasVGPRs(Src1RC))) {
+ DEBUG(dbgs() << " Fixing INSERT_SUBREG:\n");
+ DEBUG(MI.print(dbgs()));
+ TII->moveToVALU(MI);
+ }
+ break;
}
}
}