1 files changed, 108 insertions, 0 deletions
diff --git a/lib/Target/AMDIL/AMDGPUInstrEnums.td b/lib/Target/AMDIL/AMDGPUInstrEnums.td
new file mode 100644
index 00000000000..c00bb66f8c8
--- /dev/null
+++ b/lib/Target/AMDIL/AMDGPUInstrEnums.td
@@ -0,0 +1,108 @@
+class AMDILInstEnums {
+  field bits<16> NONE = 0;
+  field bits<16> FEQ = 1;
+  field bits<16> FGE = 2;
+  field bits<16> FLT = 3;
+  field bits<16> FNE = 4;
+  field bits<16> MOVE_f32 = 5;
+  field bits<16> MOVE_i32 = 6;
+  field bits<16> FTOI = 7;
+  field bits<16> ITOF = 8;
+  field bits<16> CMOVLOG_f32 = 9;
+  field bits<16> UGT = 10;
+  field bits<16> IGE = 11;
+  field bits<16> INE = 12;
+  field bits<16> UGE = 13;
+  field bits<16> IEQ = 14;
+  field bits<16> BINARY_OR_i32 = 15;
+  field bits<16> BINARY_NOT_i32 = 16;
+  field bits<16> AND_i32 = 17;
+  field bits<16> SMAX_i32 = 18;
+  field bits<16> CMOVLOG_Y_i32 = 19;
+  field bits<16> CMOVLOG_Z_i32 = 20;
+  field bits<16> CMOVLOG_W_i32 = 21;
+  field bits<16> SMUL_i32 = 22;
+  field bits<16> SMULHI_i32 = 23;
+  field bits<16> SHL_i32 = 24;
+  field bits<16> SHR_i32 = 25;
+  field bits<16> SHLVEC_i32 = 26;
+  field bits<16> SHRVEC_i32 = 27;
+  field bits<16> ADD_i32 = 28;
+  field bits<16> CUSTOM_XOR_i32 = 29;
+  field bits<16> CUSTOM_ADD_i32 = 30;
+  field bits<16> EADD_i32 = 31;
+  field bits<16> INTTOANY_i32 = 32;
+  field bits<16> UMUL_i32 = 33;
+  field bits<16> UMULHI_i32 = 34;
+  field bits<16> USHR_i32 = 35;
+  field bits<16> USHRVEC_i32 = 36;
+  field bits<16> UDIV_i32 = 37;
+  field bits<16> MUL_IEEE_f32 = 38;
+  field bits<16> ADD_f32 = 39;
+  field bits<16> ABS_f32 = 40;
+  field bits<16> FRAC_f32 = 41;
+  field bits<16> PIREDUCE_f32 = 42;
+  field bits<16> ROUND_NEAREST_f32 = 43;
+  field bits<16> ROUND_NEGINF_f32 = 44;
+  field bits<16> ROUND_POSINF_f32 = 45;
+  field bits<16> ROUND_ZERO_f32 = 46;
+  field bits<16> ACOS_f32 = 47;
+  field bits<16> ATAN_f32 = 48;
+  field bits<16> ASIN_f32 = 49;
+  field bits<16> TAN_f32 = 50;
+  field bits<16> SIN_f32 = 51;
+  field bits<16> COS_f32 = 52;
+  field bits<16> SQRT_f32 = 53;
+  field bits<16> EXP_f32 = 54;
+  field bits<16> EXPVEC_f32 = 55;
+  field bits<16> SQRTVEC_f32 = 56;
+  field bits<16> COSVEC_f32 = 57;
+  field bits<16> SINVEC_f32 = 58;
+  field bits<16> LOGVEC_f32 = 59;
+  field bits<16> RSQVEC_f32 = 60;
+  field bits<16> EXN_f32 = 61;
+  field bits<16> SIGN_f32 = 62;
+  field bits<16> LENGTH_f32 = 63;
+  field bits<16> POW_f32 = 64;
+  field bits<16> MIN_f32 = 65;
+  field bits<16> MAX_f32 = 66;
+  field bits<16> MAD_f32 = 67;
+  field bits<16> LN_f32 = 68;
+  field bits<16> LOG_f32 = 69;
+  field bits<16> RSQ_f32 = 70;
+  field bits<16> DIV_f32 = 71;
+  field bits<16> CLAMP_f32 = 72;
+  field bits<16> FMA_f32 = 73;
+  field bits<16> LERP_f32 = 74;
+  field bits<16> NEG_f32 = 75;
+  field bits<16> INTTOANY_f32 = 76;
+  field bits<16> UAVARENALOAD_i32 = 77;
+  field bits<16> UAVARENALOAD_Y_i32 = 78;
+  field bits<16> UAVARENALOAD_Z_i32 = 79;
+  field bits<16> UAVARENALOAD_W_i32 = 80;
+  field bits<16> UAVRAWLOAD_i32 = 81;
+  field bits<16> UAVRAWLOADCACHED_i32 = 82;
+  field bits<16> UAVARENASTORE_i32 = 83;
+  field bits<16> UAVARENASTORE_Y_i32 = 84;
+  field bits<16> UAVARENASTORE_Z_i32 = 85;
+  field bits<16> UAVARENASTORE_W_i32 = 86;
+  field bits<16> UAVRAWSTORE_i32 = 87;
+  field bits<16> GET_PRINTF_OFFSET_i32 = 88;
+  field bits<16> GET_PRINTF_SIZE_i32 = 89;
+}
+def AMDILInst : AMDILInstEnums;
+class AMDGPUGenEnums {
+  field bits<3> R600_CAYMAN = 0;
+  field bits<3> R600 = 1;
+  field bits<3> EG = 2;
+  field bits<3> EG_CAYMAN = 3;
+  field bits<3> CAYMAN = 4;
+  field bits<3> SI = 5;
+}
+def AMDGPUGen : AMDGPUGenEnums;
+class Constants {
+int TWO_PI = 0x40c90fdb;
+int PI = 0x40490fdb;
+int TWO_PI_INV = 0x3e22f983;
+}
+def CONST : Constants;