1 files changed, 101 insertions, 0 deletions
diff --git a/lib/Target/AMDIL/AMDGPUInstrEnums.h.include b/lib/Target/AMDIL/AMDGPUInstrEnums.h.include
new file mode 100644
index 00000000000..414489e40fa
--- /dev/null
+++ b/lib/Target/AMDIL/AMDGPUInstrEnums.h.include
@@ -0,0 +1,101 @@
+unsigned GetRealAMDILOpcode(unsigned internalOpcode) const;
+enum AMDILTblgenOpcode {
+  NONE = 0,
+  FEQ = 1,
+  FGE = 2,
+  FLT = 3,
+  FNE = 4,
+  MOVE_f32 = 5,
+  MOVE_i32 = 6,
+  FTOI = 7,
+  ITOF = 8,
+  CMOVLOG_f32 = 9,
+  UGT = 10,
+  IGE = 11,
+  INE = 12,
+  UGE = 13,
+  IEQ = 14,
+  BINARY_OR_i32 = 15,
+  BINARY_NOT_i32 = 16,
+  AND_i32 = 17,
+  SMAX_i32 = 18,
+  CMOVLOG_Y_i32 = 19,
+  CMOVLOG_Z_i32 = 20,
+  CMOVLOG_W_i32 = 21,
+  SMUL_i32 = 22,
+  SMULHI_i32 = 23,
+  SHL_i32 = 24,
+  SHR_i32 = 25,
+  SHLVEC_i32 = 26,
+  SHRVEC_i32 = 27,
+  ADD_i32 = 28,
+  CUSTOM_XOR_i32 = 29,
+  CUSTOM_ADD_i32 = 30,
+  EADD_i32 = 31,
+  INTTOANY_i32 = 32,
+  UMUL_i32 = 33,
+  UMULHI_i32 = 34,
+  USHR_i32 = 35,
+  USHRVEC_i32 = 36,
+  UDIV_i32 = 37,
+  MUL_IEEE_f32 = 38,
+  ADD_f32 = 39,
+  ABS_f32 = 40,
+  FRAC_f32 = 41,
+  PIREDUCE_f32 = 42,
+  ROUND_NEAREST_f32 = 43,
+  ROUND_NEGINF_f32 = 44,
+  ROUND_POSINF_f32 = 45,
+  ROUND_ZERO_f32 = 46,
+  ACOS_f32 = 47,
+  ATAN_f32 = 48,
+  ASIN_f32 = 49,
+  TAN_f32 = 50,
+  SIN_f32 = 51,
+  COS_f32 = 52,
+  SQRT_f32 = 53,
+  EXP_f32 = 54,
+  EXPVEC_f32 = 55,
+  SQRTVEC_f32 = 56,
+  COSVEC_f32 = 57,
+  SINVEC_f32 = 58,
+  LOGVEC_f32 = 59,
+  RSQVEC_f32 = 60,
+  EXN_f32 = 61,
+  SIGN_f32 = 62,
+  LENGTH_f32 = 63,
+  POW_f32 = 64,
+  MIN_f32 = 65,
+  MAX_f32 = 66,
+  MAD_f32 = 67,
+  LN_f32 = 68,
+  LOG_f32 = 69,
+  RSQ_f32 = 70,
+  DIV_f32 = 71,
+  CLAMP_f32 = 72,
+  FMA_f32 = 73,
+  LERP_f32 = 74,
+  NEG_f32 = 75,
+  INTTOANY_f32 = 76,
+  UAVARENALOAD_i32 = 77,
+  UAVARENALOAD_Y_i32 = 78,
+  UAVARENALOAD_Z_i32 = 79,
+  UAVARENALOAD_W_i32 = 80,
+  UAVRAWLOAD_i32 = 81,
+  UAVRAWLOADCACHED_i32 = 82,
+  UAVARENASTORE_i32 = 83,
+  UAVARENASTORE_Y_i32 = 84,
+  UAVARENASTORE_Z_i32 = 85,
+  UAVARENASTORE_W_i32 = 86,
+  UAVRAWSTORE_i32 = 87,
+  GET_PRINTF_OFFSET_i32 = 88,
+  GET_PRINTF_SIZE_i32 = 89
+};
+enum AMDGPUGen {
+  R600_CAYMAN = 0,
+  R600 = 1,
+  EG = 2,
+  EG_CAYMAN = 3,
+  CAYMAN = 4,
+  SI = 5
+};