diff options
36 files changed, 423 insertions, 121 deletions
diff --git a/Makefile.config.in b/Makefile.config.in index e3bd2a207a5..b4ecea631e3 100644 --- a/Makefile.config.in +++ b/Makefile.config.in @@ -61,6 +61,7 @@ endif prefix := @prefix@ PROJ_prefix := $(prefix) +program_prefix := @program_prefix@ PROJ_VERSION := $(LLVMVersion) else ifndef PROJ_SRC_ROOT diff --git a/Makefile.rules b/Makefile.rules index 289adc2be42..f74c6f5ada6 100644 --- a/Makefile.rules +++ b/Makefile.rules @@ -1541,7 +1541,7 @@ ToolBinDir = $(DESTDIR)$(PROJ_internal_prefix)/bin else ToolBinDir = $(DESTDIR)$(PROJ_bindir) endif -DestTool = $(ToolBinDir)/$(TOOLEXENAME) +DestTool = $(ToolBinDir)/$(program_prefix)$(TOOLEXENAME) install-local:: $(DestTool) @@ -1556,7 +1556,7 @@ uninstall-local:: # TOOLALIAS install. ifdef TOOLALIAS -DestToolAlias = $(ToolBinDir)/$(TOOLALIAS)$(EXEEXT) +DestToolAlias = $(ToolBinDir)/$(program_prefix)$(TOOLALIAS)$(EXEEXT) install-local:: $(DestToolAlias) diff --git a/autoconf/configure.ac b/autoconf/configure.ac index 574a30cef9f..13b3db6200a 100644 --- a/autoconf/configure.ac +++ b/autoconf/configure.ac @@ -1709,6 +1709,11 @@ fi dnl OCaml findlib META file AC_CONFIG_FILES([bindings/ocaml/llvm/META.llvm]) +dnl Add --program-prefix value to Makefile.rules. Already an ARG variable. +test "x$program_prefix" = "xNONE" && program_prefix="" +AC_SUBST([program_prefix]) + + dnl Do special configuration of Makefiles AC_CONFIG_COMMANDS([setup],,[llvm_src="${srcdir}"]) AC_CONFIG_MAKEFILE(Makefile) diff --git a/configure b/configure index 1905537f4e1..e9ab6bc009e 100755 --- a/configure +++ b/configure @@ -790,6 +790,7 @@ OCAML_LIBDIR ENABLE_VISIBILITY_INLINES_HIDDEN RPATH RDYNAMIC +program_prefix LIBOBJS LTLIBOBJS' ac_subst_files='' @@ -10312,7 +10313,7 @@ else lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 lt_status=$lt_dlunknown cat > conftest.$ac_ext <<EOF -#line 10315 "configure" +#line 10316 "configure" #include "confdefs.h" #if HAVE_DLFCN_H @@ -21127,6 +21128,10 @@ fi ac_config_files="$ac_config_files bindings/ocaml/llvm/META.llvm" +test "x$program_prefix" = "xNONE" && program_prefix="" + + + ac_config_commands="$ac_config_commands setup" ac_config_commands="$ac_config_commands Makefile" @@ -22050,11 +22055,12 @@ OCAML_LIBDIR!$OCAML_LIBDIR$ac_delim ENABLE_VISIBILITY_INLINES_HIDDEN!$ENABLE_VISIBILITY_INLINES_HIDDEN$ac_delim RPATH!$RPATH$ac_delim RDYNAMIC!$RDYNAMIC$ac_delim +program_prefix!$program_prefix$ac_delim LIBOBJS!$LIBOBJS$ac_delim LTLIBOBJS!$LTLIBOBJS$ac_delim _ACEOF - if test `sed -n "s/.*$ac_delim\$/X/p" conf$$subs.sed | grep -c X` = 93; then + if test `sed -n "s/.*$ac_delim\$/X/p" conf$$subs.sed | grep -c X` = 94; then break elif $ac_last_try; then { { echo "$as_me:$LINENO: error: could not make $CONFIG_STATUS" >&5 diff --git a/docs/CodingStandards.rst b/docs/CodingStandards.rst index 71ddc59c5e5..de50e6eeaf5 100644 --- a/docs/CodingStandards.rst +++ b/docs/CodingStandards.rst @@ -79,10 +79,11 @@ tree. The standard header looks like this: // License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// - // - // This file contains the declaration of the Instruction class, which is the - // base class for all of the VM instructions. - // + /// + /// \file + /// \brief This file contains the declaration of the Instruction class, which is + /// the base class for all of the VM instructions. + /// //===----------------------------------------------------------------------===// A few things to note about this particular format: The "``-*- C++ -*-``" string @@ -100,10 +101,12 @@ The next section in the file is a concise note that defines the license that the file is released under. This makes it perfectly clear what terms the source code can be distributed under and should not be modified in any way. -The main body of the description does not have to be very long in most cases. -Here it's only two lines. If an algorithm is being implemented or something -tricky is going on, a reference to the paper where it is published should be -included, as well as any notes or *gotchas* in the code to watch out for. +The main body is a ``doxygen`` comment describing the purpose of the file. It +should have a ``\brief`` command that describes the file in one or two +sentences. Any additional information should be separated by a blank line. If +an algorithm is being implemented or something tricky is going on, a reference +to the paper where it is published should be included, as well as any notes or +*gotchas* in the code to watch out for. Class overviews """"""""""""""" diff --git a/include/llvm/ADT/Triple.h b/include/llvm/ADT/Triple.h index f701a793afd..7ff90552c07 100644 --- a/include/llvm/ADT/Triple.h +++ b/include/llvm/ADT/Triple.h @@ -65,7 +65,8 @@ public: nvptx, // NVPTX: 32-bit nvptx64, // NVPTX: 64-bit le32, // le32: generic little-endian 32-bit CPU (PNaCl / Emscripten) - amdil // amdil: amd IL + amdil, // amdil: amd IL + spir // SPIR: standard portable IR for OpenCL }; enum VendorType { UnknownVendor, diff --git a/include/llvm/CallingConv.h b/include/llvm/CallingConv.h index 4c5ee626709..86e4eebb827 100644 --- a/include/llvm/CallingConv.h +++ b/include/llvm/CallingConv.h @@ -94,7 +94,25 @@ namespace CallingConv { /// MBLAZE_INTR - Calling convention used for MBlaze interrupt support /// routines (i.e. GCC's save_volatiles attribute). - MBLAZE_SVOL = 74 + MBLAZE_SVOL = 74, + + /// SPIR_FUNC - Calling convention for SPIR non-kernel device functions. + /// No lowering or expansion of arguments. + /// Structures are passed as a pointer to a struct with the byval attribute. + /// Functions can only call SPIR_FUNC and SPIR_KERNEL functions. + /// Functions can only have zero or one return values. + /// Variable arguments are not allowed, except for printf. + /// How arguments/return values are lowered are not specified. + /// Functions are only visible to the devices. + SPIR_FUNC = 75, + + /// SPIR_KERNEL - Calling convention for SPIR kernel functions. + /// Inherits the restrictions of SPIR_FUNC, except + /// Cannot have non-void return values. + /// Cannot have variable arguments. + /// Can also be called by the host. + /// Is externally visible. + SPIR_KERNEL = 76 }; } // End CallingConv namespace diff --git a/include/llvm/CodeGen/CallingConvLower.h b/include/llvm/CodeGen/CallingConvLower.h index 3afe3095d4f..436918b1eb3 100644 --- a/include/llvm/CodeGen/CallingConvLower.h +++ b/include/llvm/CodeGen/CallingConvLower.h @@ -17,6 +17,7 @@ #include "llvm/ADT/SmallVector.h" #include "llvm/CodeGen/MachineFunction.h" +#include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/ValueTypes.h" #include "llvm/Target/TargetCallingConv.h" #include "llvm/CallingConv.h" @@ -288,6 +289,7 @@ public: StackOffset = ((StackOffset + Align-1) & ~(Align-1)); unsigned Result = StackOffset; StackOffset += Size; + MF.getFrameInfo()->ensureMaxAlignment(Align); return Result; } diff --git a/include/llvm/MC/MCAsmBackend.h b/include/llvm/MC/MCAsmBackend.h index 348a5f52d2a..72ed1a317c5 100644 --- a/include/llvm/MC/MCAsmBackend.h +++ b/include/llvm/MC/MCAsmBackend.h @@ -36,6 +36,7 @@ protected: // Can only create subclasses. MCAsmBackend(); unsigned HasReliableSymbolDifference : 1; + unsigned HasDataInCodeSupport : 1; public: virtual ~MCAsmBackend(); @@ -65,6 +66,12 @@ public: return HasReliableSymbolDifference; } + /// hasDataInCodeSupport - Check whether this target implements data-in-code + /// markers. If not, data region directives will be ignored. + bool hasDataInCodeSupport() const { + return HasDataInCodeSupport; + } + /// doesSectionRequireSymbols - Check whether the given section requires that /// all symbols (even temporaries) have symbol table entries. virtual bool doesSectionRequireSymbols(const MCSection &Section) const { diff --git a/include/llvm/MC/MCParser/MCParsedAsmOperand.h b/include/llvm/MC/MCParser/MCParsedAsmOperand.h index 369bc72ff61..0ce32d617ef 100644 --- a/include/llvm/MC/MCParser/MCParsedAsmOperand.h +++ b/include/llvm/MC/MCParser/MCParsedAsmOperand.h @@ -29,6 +29,8 @@ public: virtual bool isImm() const = 0; /// isReg - Is this a register operand? virtual bool isReg() const = 0; + virtual unsigned getReg() const = 0; + /// isMem - Is this a memory operand? virtual bool isMem() const = 0; diff --git a/include/llvm/MC/MCTargetAsmParser.h b/include/llvm/MC/MCTargetAsmParser.h index 2b5a672d6d1..16cf6273a5a 100644 --- a/include/llvm/MC/MCTargetAsmParser.h +++ b/include/llvm/MC/MCTargetAsmParser.h @@ -89,11 +89,11 @@ public: /// On failure, the target parser is responsible for emitting a diagnostic /// explaining the match failure. virtual bool - MatchInstruction(SMLoc IDLoc, unsigned &Kind, + MatchInstruction(SMLoc IDLoc, SmallVectorImpl<MCParsedAsmOperand*> &Operands, - SmallVectorImpl<MCInst> &MCInsts, - unsigned &OrigErrorInfo, - bool matchingInlineAsm = false) { + MCStreamer &Out, unsigned &Kind, unsigned &Opcode, + SmallVectorImpl<std::pair< unsigned, std::string > > &MapAndConstraints, + unsigned &OrigErrorInfo, bool matchingInlineAsm = false) { OrigErrorInfo = ~0x0; return true; } @@ -115,10 +115,9 @@ public: return Match_Success; } - virtual unsigned getMCInstOperandNum(unsigned Kind, + virtual void convertToMapAndConstraints(unsigned Kind, const SmallVectorImpl<MCParsedAsmOperand*> &Operands, - unsigned OperandNum, - unsigned &NumMCOperands) = 0; + SmallVectorImpl<std::pair< unsigned, std::string > > &MapAndConstraints) = 0; }; } // End llvm namespace diff --git a/lib/AsmParser/LLLexer.cpp b/lib/AsmParser/LLLexer.cpp index 6e61665443e..2ad0010fd12 100644 --- a/lib/AsmParser/LLLexer.cpp +++ b/lib/AsmParser/LLLexer.cpp @@ -525,6 +525,8 @@ lltok::Kind LLLexer::LexIdentifier() { KEYWORD(msp430_intrcc); KEYWORD(ptx_kernel); KEYWORD(ptx_device); + KEYWORD(spir_kernel); + KEYWORD(spir_func); KEYWORD(cc); KEYWORD(c); diff --git a/lib/AsmParser/LLParser.cpp b/lib/AsmParser/LLParser.cpp index 66a8e17e119..39d5660b7f5 100644 --- a/lib/AsmParser/LLParser.cpp +++ b/lib/AsmParser/LLParser.cpp @@ -1101,6 +1101,8 @@ bool LLParser::ParseOptionalVisibility(unsigned &Res) { /// ::= 'msp430_intrcc' /// ::= 'ptx_kernel' /// ::= 'ptx_device' +/// ::= 'spir_func' +/// ::= 'spir_kernel' /// ::= 'cc' UINT /// bool LLParser::ParseOptionalCallingConv(CallingConv::ID &CC) { @@ -1118,6 +1120,8 @@ bool LLParser::ParseOptionalCallingConv(CallingConv::ID &CC) { case lltok::kw_msp430_intrcc: CC = CallingConv::MSP430_INTR; break; case lltok::kw_ptx_kernel: CC = CallingConv::PTX_Kernel; break; case lltok::kw_ptx_device: CC = CallingConv::PTX_Device; break; + case lltok::kw_spir_kernel: CC = CallingConv::SPIR_KERNEL; break; + case lltok::kw_spir_func: CC = CallingConv::SPIR_FUNC; break; case lltok::kw_cc: { unsigned ArbitraryCC; Lex.Lex(); diff --git a/lib/AsmParser/LLToken.h b/lib/AsmParser/LLToken.h index 37cbf3003e7..0859f6a288f 100644 --- a/lib/AsmParser/LLToken.h +++ b/lib/AsmParser/LLToken.h @@ -81,6 +81,7 @@ namespace lltok { kw_arm_apcscc, kw_arm_aapcscc, kw_arm_aapcs_vfpcc, kw_msp430_intrcc, kw_ptx_kernel, kw_ptx_device, + kw_spir_kernel, kw_spir_func, kw_signext, kw_zeroext, diff --git a/lib/MC/MCAsmBackend.cpp b/lib/MC/MCAsmBackend.cpp index 2e447b05a41..53960e7980a 100644 --- a/lib/MC/MCAsmBackend.cpp +++ b/lib/MC/MCAsmBackend.cpp @@ -12,12 +12,9 @@ using namespace llvm; MCAsmBackend::MCAsmBackend() - : HasReliableSymbolDifference(false) -{ -} + : HasReliableSymbolDifference(false), HasDataInCodeSupport(false) {} -MCAsmBackend::~MCAsmBackend() { -} +MCAsmBackend::~MCAsmBackend() {} const MCFixupKindInfo & MCAsmBackend::getFixupKindInfo(MCFixupKind Kind) const { diff --git a/lib/MC/MCMachOStreamer.cpp b/lib/MC/MCMachOStreamer.cpp index 74f6dc62e1c..b152a8c85e2 100644 --- a/lib/MC/MCMachOStreamer.cpp +++ b/lib/MC/MCMachOStreamer.cpp @@ -139,6 +139,8 @@ void MCMachOStreamer::EmitLabel(MCSymbol *Symbol) { } void MCMachOStreamer::EmitDataRegion(DataRegionData::KindTy Kind) { + if (!getAssembler().getBackend().hasDataInCodeSupport()) + return; // Create a temporary label to mark the start of the data region. MCSymbol *Start = getContext().CreateTempSymbol(); EmitLabel(Start); @@ -149,6 +151,8 @@ void MCMachOStreamer::EmitDataRegion(DataRegionData::KindTy Kind) { } void MCMachOStreamer::EmitDataRegionEnd() { + if (!getAssembler().getBackend().hasDataInCodeSupport()) + return; std::vector<DataRegionData> &Regions = getAssembler().getDataRegions(); assert(Regions.size() && "Mismatched .end_data_region!"); DataRegionData &Data = Regions.back(); diff --git a/lib/Support/Triple.cpp b/lib/Support/Triple.cpp index d1dc7c81af0..32f4074b15f 100644 --- a/lib/Support/Triple.cpp +++ b/lib/Support/Triple.cpp @@ -42,6 +42,7 @@ const char *Triple::getArchTypeName(ArchType Kind) { case nvptx64: return "nvptx64"; case le32: return "le32"; case amdil: return "amdil"; + case spir: return "spir"; } llvm_unreachable("Invalid ArchType!"); @@ -83,6 +84,7 @@ const char *Triple::getArchTypePrefix(ArchType Kind) { case nvptx64: return "nvptx"; case le32: return "le32"; case amdil: return "amdil"; + case spir: return "spir"; } } @@ -171,6 +173,7 @@ Triple::ArchType Triple::getArchTypeForLLVMName(StringRef Name) { .Case("nvptx64", nvptx64) .Case("le32", le32) .Case("amdil", amdil) + .Case("spir", spir) .Default(UnknownArch); } @@ -202,6 +205,7 @@ Triple::ArchType Triple::getArchTypeForDarwinArchName(StringRef Str) { .Case("nvptx", Triple::nvptx) .Case("nvptx64", Triple::nvptx64) .Case("amdil", Triple::amdil) + .Case("spir", Triple::spir) .Default(Triple::UnknownArch); } @@ -226,6 +230,7 @@ const char *Triple::getArchNameForAssembler() { .Case("nvptx64", "nvptx64") .Case("le32", "le32") .Case("amdil", "amdil") + .Case("spir", "spir") .Default(NULL); } @@ -260,6 +265,7 @@ static Triple::ArchType parseArch(StringRef ArchName) { .Case("nvptx64", Triple::nvptx64) .Case("le32", Triple::le32) .Case("amdil", Triple::amdil) + .Case("spir", Triple::spir) .Default(Triple::UnknownArch); } @@ -670,6 +676,7 @@ void Triple::setOSAndEnvironmentName(StringRef Str) { static unsigned getArchPointerBitWidth(llvm::Triple::ArchType Arch) { switch (Arch) { + case llvm::Triple::spir: case llvm::Triple::UnknownArch: return 0; @@ -726,6 +733,7 @@ Triple Triple::get32BitArchVariant() const { break; case Triple::amdil: + case Triple::spir: case Triple::arm: case Triple::cellspu: case Triple::hexagon: @@ -772,6 +780,7 @@ Triple Triple::get64BitArchVariant() const { T.setArch(UnknownArch); break; + case Triple::spir: case Triple::mips64: case Triple::mips64el: case Triple::nvptx64: diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index aa5ba46ab21..9e926492179 100644 --- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -7480,8 +7480,10 @@ MatchAndEmitInstruction(SMLoc IDLoc, unsigned Kind; unsigned ErrorInfo; unsigned MatchResult; - - MatchResult = MatchInstructionImpl(Operands, Kind, Inst, ErrorInfo); + SmallVector<std::pair< unsigned, std::string >, 4> MapAndConstraints; + MatchResult = MatchInstructionImpl(Operands, Kind, Inst, + MapAndConstraints, ErrorInfo, + /*matchingInlineAsm*/ false); switch (MatchResult) { default: break; case Match_Success: diff --git a/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp b/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp index b032978da9e..1ba6ab039f2 100644 --- a/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp +++ b/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp @@ -593,7 +593,9 @@ public: const object::mach::CPUSubtypeARM Subtype; DarwinARMAsmBackend(const Target &T, const StringRef TT, object::mach::CPUSubtypeARM st) - : ARMAsmBackend(T, TT), Subtype(st) { } + : ARMAsmBackend(T, TT), Subtype(st) { + HasDataInCodeSupport = true; + } MCObjectWriter *createObjectWriter(raw_ostream &OS) const { return createARMMachObjectWriter(OS, /*Is64Bit=*/false, diff --git a/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp b/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp index 9e22fd06d17..09eb4c8cabe 100644 --- a/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp +++ b/lib/Target/MBlaze/AsmParser/MBlazeAsmParser.cpp @@ -318,8 +318,9 @@ MatchAndEmitInstruction(SMLoc IDLoc, MCInst Inst; unsigned Kind; unsigned ErrorInfo; - - switch (MatchInstructionImpl(Operands, Kind, Inst, ErrorInfo)) { + SmallVector<std::pair< unsigned, std::string >, 4> MapAndConstraints; + switch (MatchInstructionImpl(Operands, Kind, Inst, MapAndConstraints, + ErrorInfo, /*matchingInlineAsm*/ false)) { default: break; case Match_Success: Out.EmitInstruction(Inst); diff --git a/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/lib/Target/Mips/AsmParser/MipsAsmParser.cpp index b1ada100f49..349abef16be 100644 --- a/lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ b/lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -261,9 +261,12 @@ MatchAndEmitInstruction(SMLoc IDLoc, SmallVectorImpl<MCParsedAsmOperand*> &Operands, MCStreamer &Out) { MCInst Inst; - unsigned ErrorInfo; unsigned Kind; - unsigned MatchResult = MatchInstructionImpl(Operands, Kind, Inst, ErrorInfo); + unsigned ErrorInfo; + SmallVector<std::pair< unsigned, std::string >, 4> MapAndConstraints; + unsigned MatchResult = MatchInstructionImpl(Operands, Kind, Inst, + MapAndConstraints, ErrorInfo, + /*matchingInlineAsm*/ false); switch (MatchResult) { default: break; diff --git a/lib/Target/X86/AsmParser/X86AsmParser.cpp b/lib/Target/X86/AsmParser/X86AsmParser.cpp index 9263bdde20d..704d5f94261 100644 --- a/lib/Target/X86/AsmParser/X86AsmParser.cpp +++ b/lib/Target/X86/AsmParser/X86AsmParser.cpp @@ -66,12 +66,11 @@ private: bool MatchAndEmitInstruction(SMLoc IDLoc, SmallVectorImpl<MCParsedAsmOperand*> &Operands, MCStreamer &Out); - - bool MatchInstruction(SMLoc IDLoc, unsigned &Kind, + bool MatchInstruction(SMLoc IDLoc, SmallVectorImpl<MCParsedAsmOperand*> &Operands, - SmallVectorImpl<MCInst> &MCInsts, - unsigned &OrigErrorInfo, - bool matchingInlineAsm = false); + MCStreamer &Out, unsigned &Kind, unsigned &Opcode, + SmallVectorImpl<std::pair< unsigned, std::string > > &MapAndConstraints, + unsigned &OrigErrorInfo, bool matchingInlineAsm = false); /// isSrcOp - Returns true if operand is either (%rsi) or %ds:%(rsi) /// in 64bit mode or (%esi) or %es:(%esi) in 32bit mode. @@ -1521,22 +1520,20 @@ MatchAndEmitInstruction(SMLoc IDLoc, SmallVectorImpl<MCParsedAsmOperand*> &Operands, MCStreamer &Out) { unsigned Kind; + unsigned Opcode; unsigned ErrorInfo; - SmallVector<MCInst, 2> Insts; - - bool Error = MatchInstruction(IDLoc, Kind, Operands, Insts, - ErrorInfo); - if (!Error) - for (unsigned i = 0, e = Insts.size(); i != e; ++i) - Out.EmitInstruction(Insts[i]); + SmallVector<std::pair< unsigned, std::string >, 4> MapAndConstraints; + bool Error = MatchInstruction(IDLoc, Operands, Out, Kind, Opcode, + MapAndConstraints, ErrorInfo); return Error; } bool X86AsmParser:: -MatchInstruction(SMLoc IDLoc, unsigned &Kind, +MatchInstruction(SMLoc IDLoc, SmallVectorImpl<MCParsedAsmOperand*> &Operands, - SmallVectorImpl<MCInst> &MCInsts, unsigned &OrigErrorInfo, - bool matchingInlineAsm) { + MCStreamer &Out, unsigned &Kind, unsigned &Opcode, + SmallVectorImpl<std::pair< unsigned, std::string > > &MapAndConstraints, + unsigned &OrigErrorInfo, bool matchingInlineAsm) { assert(!Operands.empty() && "Unexpect empty operand list!"); X86Operand *Op = static_cast<X86Operand*>(Operands[0]); assert(Op->isToken() && "Leading operand should always be a mnemonic!"); @@ -1553,7 +1550,8 @@ MatchInstruction(SMLoc IDLoc, unsigned &Kind, MCInst Inst; Inst.setOpcode(X86::WAIT); Inst.setLoc(IDLoc); - MCInsts.push_back(Inst); + if (!matchingInlineAsm) + Out.EmitInstruction(Inst); const char *Repl = StringSwitch<const char*>(Op->getToken()) @@ -1575,18 +1573,22 @@ MatchInstruction(SMLoc IDLoc, unsigned &Kind, MCInst Inst; // First, try a direct match. - switch (MatchInstructionImpl(Operands, Kind, Inst, OrigErrorInfo, + switch (MatchInstructionImpl(Operands, Kind, Inst, MapAndConstraints, + OrigErrorInfo, matchingInlineAsm, isParsingIntelSyntax())) { default: break; case Match_Success: // Some instructions need post-processing to, for example, tweak which // encoding is selected. Loop on it while changes happen so the // individual transformations can chain off each other. - while (processInstruction(Inst, Operands)) - ; + if (!matchingInlineAsm) + while (processInstruction(Inst, Operands)) + ; Inst.setLoc(IDLoc); - MCInsts.push_back(Inst); + if (!matchingInlineAsm) + Out.EmitInstruction(Inst); + Opcode = Inst.getOpcode(); return false; case Match_MissingFeature: Error(IDLoc, "instruction requires a CPU feature not currently enabled", @@ -1625,20 +1627,21 @@ MatchInstruction(SMLoc IDLoc, unsigned &Kind, unsigned Match1, Match2, Match3, Match4; unsigned tKind; - Match1 = MatchInstructionImpl(Operands, tKind, Inst, ErrorInfoIgnore, - isParsingIntelSyntax()); + SmallVector<std::pair< unsigned, std::string >, 4> tMapAndConstraints[4]; + Match1 = MatchInstructionImpl(Operands, tKind, Inst, tMapAndConstraints[0], + ErrorInfoIgnore, isParsingIntelSyntax()); if (Match1 == Match_Success) Kind = tKind; Tmp[Base.size()] = Suffixes[1]; - Match2 = MatchInstructionImpl(Operands, tKind, Inst, ErrorInfoIgnore, - isParsingIntelSyntax()); + Match2 = MatchInstructionImpl(Operands, tKind, Inst, tMapAndConstraints[1], + ErrorInfoIgnore, isParsingIntelSyntax()); if (Match2 == Match_Success) Kind = tKind; Tmp[Base.size()] = Suffixes[2]; - Match3 = MatchInstructionImpl(Operands, tKind, Inst, ErrorInfoIgnore, - isParsingIntelSyntax()); + Match3 = MatchInstructionImpl(Operands, tKind, Inst, tMapAndConstraints[2], + ErrorInfoIgnore, isParsingIntelSyntax()); if (Match3 == Match_Success) Kind = tKind; Tmp[Base.size()] = Suffixes[3]; - Match4 = MatchInstructionImpl(Operands, tKind, Inst, ErrorInfoIgnore, - isParsingIntelSyntax()); + Match4 = MatchInstructionImpl(Operands, tKind, Inst, tMapAndConstraints[3], + ErrorInfoIgnore, isParsingIntelSyntax()); if (Match4 == Match_Success) Kind = tKind; // Restore the old token. @@ -1652,7 +1655,10 @@ MatchInstruction(SMLoc IDLoc, unsigned &Kind, (Match3 == Match_Success) + (Match4 == Match_Success); if (NumSuccessfulMatches == 1) { Inst.setLoc(IDLoc); - MCInsts.push_back(Inst); + if (!matchingInlineAsm) + Out.EmitInstruction(Inst); + Opcode = Inst.getOpcode(); + // FIXME: Handle the map and constraints. return false; } diff --git a/lib/Transforms/IPO/PassManagerBuilder.cpp b/lib/Transforms/IPO/PassManagerBuilder.cpp index 9e328b9ac97..a2862022a3b 100644 --- a/lib/Transforms/IPO/PassManagerBuilder.cpp +++ b/lib/Transforms/IPO/PassManagerBuilder.cpp @@ -41,7 +41,7 @@ UseGVNAfterVectorization("use-gvn-after-vectorization", cl::desc("Run GVN instead of Early CSE after vectorization passes")); static cl::opt<bool> UseNewSROA("use-new-sroa", - cl::init(false), cl::Hidden, + cl::init(true), cl::Hidden, cl::desc("Enable the new, experimental SROA pass")); PassManagerBuilder::PassManagerBuilder() { diff --git a/projects/sample/Makefile.llvm.rules b/projects/sample/Makefile.llvm.rules index a6553020f86..7ed1c1b4ed6 100644 --- a/projects/sample/Makefile.llvm.rules +++ b/projects/sample/Makefile.llvm.rules @@ -1437,7 +1437,7 @@ install-local:: uninstall-local:: $(Echo) Uninstall circumvented with NO_INSTALL else -DestTool = $(DESTDIR)$(PROJ_bindir)/$(TOOLEXENAME) +DestTool = $(DESTDIR)$(PROJ_bindir)/$(program_prefix)$(TOOLEXENAME) install-local:: $(DestTool) @@ -1451,7 +1451,7 @@ uninstall-local:: # TOOLALIAS install. ifdef TOOLALIAS -DestToolAlias = $(DESTDIR)$(PROJ_bindir)/$(TOOLALIAS)$(EXEEXT) +DestToolAlias = $(DESTDIR)$(PROJ_bindir)/$(program_prefix)$(TOOLALIAS)$(EXEEXT) install-local:: $(DestToolAlias) diff --git a/test/Analysis/Profiling/load-branch-weights-ifs.ll b/test/Analysis/Profiling/load-branch-weights-ifs.ll index ddbaf96916c..7ed090b7c36 100644 --- a/test/Analysis/Profiling/load-branch-weights-ifs.ll +++ b/test/Analysis/Profiling/load-branch-weights-ifs.ll @@ -1,6 +1,6 @@ ; RUN: opt -insert-edge-profiling -o %t1 < %s ; RUN: rm -f %t1.prof_data -; RUN: lli -load %llvmshlibdir/libprofile_rt%shlibext %t1 \ +; RUN: lli %defaultjit -load %llvmshlibdir/libprofile_rt%shlibext %t1 \ ; RUN: -llvmprof-output %t1.prof_data ; RUN: opt -profile-file %t1.prof_data -profile-metadata-loader -S -o - < %s \ ; RUN: | FileCheck %s diff --git a/test/Analysis/Profiling/load-branch-weights-loops.ll b/test/Analysis/Profiling/load-branch-weights-loops.ll index 476f377b47a..9d1925a2d70 100644 --- a/test/Analysis/Profiling/load-branch-weights-loops.ll +++ b/test/Analysis/Profiling/load-branch-weights-loops.ll @@ -1,6 +1,6 @@ ; RUN: opt -insert-edge-profiling -o %t1 < %s ; RUN: rm -f %t1.prof_data -; RUN: lli -load %llvmshlibdir/libprofile_rt%shlibext %t1 \ +; RUN: lli %defaultjit -load %llvmshlibdir/libprofile_rt%shlibext %t1 \ ; RUN: -llvmprof-output %t1.prof_data ; RUN: opt -profile-file %t1.prof_data -profile-metadata-loader -S -o - < %s \ ; RUN: | FileCheck %s diff --git a/test/Analysis/Profiling/load-branch-weights-switches.ll b/test/Analysis/Profiling/load-branch-weights-switches.ll index be11f040a76..5587c7172bb 100644 --- a/test/Analysis/Profiling/load-branch-weights-switches.ll +++ b/test/Analysis/Profiling/load-branch-weights-switches.ll @@ -1,6 +1,6 @@ ; RUN: opt -insert-edge-profiling -o %t1 < %s ; RUN: rm -f %t1.prof_data -; RUN: lli -load %llvmshlibdir/libprofile_rt%shlibext %t1 \ +; RUN: lli %defaultjit -load %llvmshlibdir/libprofile_rt%shlibext %t1 \ ; RUN: -llvmprof-output %t1.prof_data ; RUN: opt -profile-file %t1.prof_data -profile-metadata-loader -S -o - < %s \ ; RUN: | FileCheck %s diff --git a/test/CodeGen/Mips/stldst.ll b/test/CodeGen/Mips/stldst.ll new file mode 100644 index 00000000000..4182b9e76d6 --- /dev/null +++ b/test/CodeGen/Mips/stldst.ll @@ -0,0 +1,41 @@ +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16 + +@kkkk = global i32 67, align 4 +@llll = global i32 33, align 4 +@mmmm = global i32 44, align 4 +@nnnn = global i32 55, align 4 +@oooo = global i32 32, align 4 +@pppp = global i32 41, align 4 +@qqqq = global i32 59, align 4 +@rrrr = global i32 60, align 4 +@.str = private unnamed_addr constant [32 x i8] c"%i %i %i %i %i %i %i %i %i %i \0A\00", align 1 + +define i32 @main() nounwind { +entry: + %0 = load i32* @kkkk, align 4 + %1 = load i32* @llll, align 4 + %add = add nsw i32 %0, 10 + %add1 = add nsw i32 %1, 10 + %2 = load i32* @mmmm, align 4 + %sub = add nsw i32 %2, -3 + %3 = load i32* @nnnn, align 4 + %add2 = add nsw i32 %3, 10 + %4 = load i32* @oooo, align 4 + %add3 = add nsw i32 %4, 4 + %5 = load i32* @pppp, align 4 + %sub4 = add nsw i32 %5, -5 + %6 = load i32* @qqqq, align 4 + %sub5 = add nsw i32 %6, -10 + %7 = load i32* @rrrr, align 4 + %add6 = add nsw i32 %7, 6 + + %call = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([32 x i8]* @.str, i32 0, i32 0), i32 %sub5, i32 %add6, i32 %0, i32 %1, i32 %2, i32 %3, i32 %4, i32 %5, i32 %6, i32 %7) nounwind + %call7 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([32 x i8]* @.str, i32 0, i32 0), i32 %0, i32 %1, i32 %add, i32 %add1, i32 %sub, i32 %add2, i32 %add3, i32 %sub4, i32 %sub5, i32 %add6) nounwind + ret i32 0 +} +; 16: sw ${{[0-9]+}}, {{[0-9]+}} ( $sp ); # 4-byte Folded Spill +; 16: lw ${{[0-9]+}}, {{[0-9]+}} ( $sp ); # 4-byte Folded Reload +; 16: sw ${{[0-9]+}}, {{[0-9]+}} ( $sp ); # 4-byte Folded Spill +; 16: lw ${{[0-9]+}}, {{[0-9]+}} ( $sp ); # 4-byte Folded Reload + +declare i32 @printf(i8* nocapture, ...) nounwind diff --git a/test/CodeGen/X86/pr13899.ll b/test/CodeGen/X86/pr13899.ll new file mode 100644 index 00000000000..bc81e34d67e --- /dev/null +++ b/test/CodeGen/X86/pr13899.ll @@ -0,0 +1,58 @@ +; RUN: llc < %s -mtriple=i386-pc-win32 -mcpu=corei7 | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=core-avx2 | FileCheck %s --check-prefix=X64 + +; ModuleID = 'a.bc' +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f80:128:128-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32-S32" +target triple = "i386-pc-win32" + +%v4_varying_big_struct = type { [4 x <4 x i32>] } + +declare <4 x i32> @"foo"(%v4_varying_big_struct, <4 x i32>) nounwind + +define <4 x i32> @"bar"(%v4_varying_big_struct %s, <4 x i32> %__mask) nounwind { +allocas: + %calltmp = call <4 x i32> @"foo"(%v4_varying_big_struct %s, <4 x i32> %__mask) + ret <4 x i32> %calltmp +; CHECK: bar +; CHECK: andl +; CHECK: call +; CHECK: ret +} + +declare <8 x float> @bar64(<8 x float> %i0, <8 x float> %i1, + <8 x float> %i2, <8 x float> %i3, + <8 x float> %i4, <8 x float> %i5, + <8 x float> %i6, <8 x float> %i7, + <8 x float> %i8, <8 x float> %i9) + +define <8 x float> @foo64(<8 x float>* %p) { + %1 = load <8 x float>* %p + %idx1 = getelementptr inbounds <8 x float>* %p, i64 1 + %2 = load <8 x float>* %idx1 + %idx2 = getelementptr inbounds <8 x float>* %p, i64 2 + %3 = load <8 x float>* %idx2 + %idx3 = getelementptr inbounds <8 x float>* %p, i64 3 + %4 = load <8 x float>* %idx3 + %idx4 = getelementptr inbounds <8 x float>* %p, i64 4 + %5 = load <8 x float>* %idx4 + %idx5 = getelementptr inbounds <8 x float>* %p, i64 5 + %6 = load <8 x float>* %idx5 + %idx6 = getelementptr inbounds <8 x float>* %p, i64 6 + %7 = load <8 x float>* %idx6 + %idx7 = getelementptr inbounds <8 x float>* %p, i64 7 + %8 = load <8 x float>* %idx7 + %idx8 = getelementptr inbounds <8 x float>* %p, i64 8 + %9 = load <8 x float>* %idx8 + %idx9 = getelementptr inbounds <8 x float>* %p, i64 9 + %10 = load <8 x float>* %idx9 + %r = tail call <8 x float> @bar64(<8 x float> %1, <8 x float> %2, + <8 x float> %3, <8 x float> %4, + <8 x float> %5, <8 x float> %6, + <8 x float> %7, <8 x float> %8, + <8 x float> %9, <8 x float> %10) + ret <8 x float> %r +; X64: foo +; X64: and +; X64: call +; X64: ret +} diff --git a/test/CodeGen/X86/red-zone2.ll b/test/CodeGen/X86/red-zone2.ll index f09216319e8..3e9c7909a36 100644 --- a/test/CodeGen/X86/red-zone2.ll +++ b/test/CodeGen/X86/red-zone2.ll @@ -1,6 +1,7 @@ -; RUN: llc < %s -mcpu=generic -march=x86-64 > %t -; RUN: grep subq %t | count 1 -; RUN: grep addq %t | count 1 +; RUN: llc < %s -mcpu=generic -mtriple=x86_64-linux | FileCheck %s +; CHECK: f0: +; CHECK: subq +; CHECK: addq define x86_fp80 @f0(float %f) nounwind readnone noredzone { entry: diff --git a/test/MC/MachO/lit.local.cfg b/test/MC/MachO/lit.local.cfg index 6c49f08b749..41a8434f999 100644 --- a/test/MC/MachO/lit.local.cfg +++ b/test/MC/MachO/lit.local.cfg @@ -1,4 +1,4 @@ -config.suffixes = ['.s'] +config.suffixes = ['.s', '.ll'] targets = set(config.root.targets_to_build.split()) if not 'X86' in targets: diff --git a/test/MC/MachO/x86-data-in-code.ll b/test/MC/MachO/x86-data-in-code.ll new file mode 100644 index 00000000000..2410974c5ca --- /dev/null +++ b/test/MC/MachO/x86-data-in-code.ll @@ -0,0 +1,108 @@ +; RUN: llc -O0 -mtriple=x86_64-apple-darwin -filetype=obj -o - %s | macho-dump | FileCheck %s + +; There should not be a data-in-code load command (type 0x29) for x86_64 +; jump tables, even though they are in the text section. +; CHECK: 'num_load_commands' +; CHECK-NOT: (('command', 41) + +define void @foo(i32* %ptr) nounwind ssp { + %tmp = load i32* %ptr, align 4 + switch i32 %tmp, label %default [ + i32 11, label %bb0 + i32 10, label %bb1 + i32 8, label %bb2 + i32 4, label %bb3 + i32 2, label %bb4 + i32 6, label %bb5 + i32 9, label %bb6 + i32 15, label %bb7 + i32 1, label %bb8 + i32 3, label %bb9 + i32 5, label %bb10 + i32 30, label %bb11 + i32 31, label %bb12 + i32 13, label %bb13 + i32 14, label %bb14 + i32 20, label %bb15 + i32 19, label %bb16 + i32 17, label %bb17 + i32 18, label %bb18 + i32 21, label %bb19 + i32 22, label %bb20 + i32 16, label %bb21 + i32 24, label %bb22 + i32 25, label %bb23 + i32 26, label %bb24 + i32 27, label %bb25 + i32 28, label %bb26 + i32 23, label %bb27 + i32 12, label %bb28 + ] + +default: + br label %exit +bb0: + br label %exit +bb1: + br label %exit +bb2: + br label %exit +bb3: + br label %exit +bb4: + br label %exit +bb5: + br label %exit +bb6: + br label %exit +bb7: + br label %exit +bb8: + br label %exit +bb9: + br label %exit +bb10: + br label %exit +bb11: + br label %exit +bb12: + br label %exit +bb13: + br label %exit +bb14: + br label %exit +bb15: + br label %exit +bb16: + br label %exit +bb17: + br label %exit +bb18: + br label %exit +bb19: + br label %exit +bb20: + br label %exit +bb21: + br label %exit +bb22: + br label %exit +bb23: + br label %exit +bb24: + br label %exit +bb25: + br label %exit +bb26: + br label %exit +bb27: + br label %exit +bb28: + br label %exit + + +exit: + + ret void +} + diff --git a/test/Other/spir_cc.ll b/test/Other/spir_cc.ll new file mode 100644 index 00000000000..ffc02945de4 --- /dev/null +++ b/test/Other/spir_cc.ll @@ -0,0 +1,13 @@ +; RUN: llvm-as < %s | llvm-dis > %t1.ll +; RUN: llvm-as %t1.ll -o - | llvm-dis > %t2.ll +; RUN: diff %t1.ll %t2.ll + +define spir_func void @foo() { + ret void +} + +define spir_kernel void @bar() { + call spir_func void @foo( ) + call spir_kernel void @bar( ) + ret void +} diff --git a/test/lit.cfg b/test/lit.cfg index 6f44bb3d8c6..b7c5f3ef38c 100644 --- a/test/lit.cfg +++ b/test/lit.cfg @@ -143,6 +143,11 @@ if config.test_exec_root is None: # triple so we can check it with XFAIL and XTARGET. config.target_triple += lit.valgrindTriple +# Provide a substition for those tests that need to run the jit to obtain data +# but simply want use the currently considered most reliable jit for platform +defaultIsMCJIT='true' if 'arm' in config.target_triple else 'false' +config.substitutions.append( ('%defaultjit', '-use-mcjit='+defaultIsMCJIT) ) + # Process jit implementation option jit_impl_cfg = lit.params.get('jit_impl', None) if jit_impl_cfg == 'mcjit': diff --git a/tools/llvm-config/Makefile b/tools/llvm-config/Makefile index e8c86929e18..b20b6bf4a4b 100644 --- a/tools/llvm-config/Makefile +++ b/tools/llvm-config/Makefile @@ -63,5 +63,5 @@ ifeq ($(LLVM_CROSS_COMPILING),1) install:: $(DESTDIR)$(PROJ_bindir) $(Echo) Installing llvm-config-host $(Verb) $(ProgInstall) $(BuildLLVMToolDir)/llvm-config \ - $(DESTDIR)$(PROJ_bindir)/llvm-config-host + $(DESTDIR)$(PROJ_bindir)/$(program_prefix)llvm-config-host endif diff --git a/utils/TableGen/AsmMatcherEmitter.cpp b/utils/TableGen/AsmMatcherEmitter.cpp index 7b49723d215..87c778762a0 100644 --- a/utils/TableGen/AsmMatcherEmitter.cpp +++ b/utils/TableGen/AsmMatcherEmitter.cpp @@ -1674,9 +1674,9 @@ static unsigned getConverterOperandID(const std::string &Name, } -static void emitConvertToMCInst(CodeGenTarget &Target, StringRef ClassName, - std::vector<MatchableInfo*> &Infos, - raw_ostream &OS) { +static void emitConvertFuncs(CodeGenTarget &Target, StringRef ClassName, + std::vector<MatchableInfo*> &Infos, + raw_ostream &OS) { SetVector<std::string> OperandConversionKinds; SetVector<std::string> InstructionConversionKinds; std::vector<std::vector<uint8_t> > ConversionTable; @@ -1713,29 +1713,23 @@ static void emitConvertToMCInst(CodeGenTarget &Target, StringRef ClassName, std::string OperandFnBody; raw_string_ostream OpOS(OperandFnBody); // Start the operand number lookup function. - OpOS << "unsigned " << Target.getName() << ClassName << "::\n" - << "getMCInstOperandNum(unsigned Kind,\n" - << " const SmallVectorImpl<MCParsedAsmOperand*> " - << "&Operands,\n unsigned OperandNum, unsigned " - << "&NumMCOperands) {\n" + OpOS << "void " << Target.getName() << ClassName << "::\n" + << "convertToMapAndConstraints(unsigned Kind,\n"; + OpOS.indent(27); + OpOS << "const SmallVectorImpl<MCParsedAsmOperand*> &Operands,\n" + << " SmallVectorImpl<std::pair< unsigned, std::string > >" + << " &MapAndConstraints) {\n" << " assert(Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\");\n" - << " NumMCOperands = 0;\n" - << " unsigned MCOperandNum = 0;\n" + << " unsigned NumMCOperands = 0;\n" << " const uint8_t *Converter = ConversionTable[Kind];\n" << " for (const uint8_t *p = Converter; *p; p+= 2) {\n" - << " if (*(p + 1) > OperandNum) continue;\n" << " switch (*p) {\n" << " default: llvm_unreachable(\"invalid conversion entry!\");\n" << " case CVT_Reg:\n" - << " if (*(p + 1) == OperandNum) {\n" - << " NumMCOperands = 1;\n" - << " break;\n" - << " }\n" - << " ++MCOperandNum;\n" - << " break;\n" << " case CVT_Tied:\n" - << " // FIXME: Tied operand calculation not supported.\n" - << " assert (0 && \"getMCInstOperandNumImpl() doesn't support tied operands, yet!\");\n" + << " MapAndConstraints.push_back(std::make_pair(NumMCOperands," + << "\"r\"));\n" + << " ++NumMCOperands;\n" << " break;\n"; // Pre-populate the operand conversion kinds with the standard always @@ -1831,11 +1825,9 @@ static void emitConvertToMCInst(CodeGenTarget &Target, StringRef ClassName, // Add a handler for the operand number lookup. OpOS << " case " << Name << ":\n" - << " if (*(p + 1) == OperandNum) {\n" - << " NumMCOperands = " << OpInfo.MINumOperands << ";\n" - << " break;\n" - << " }\n" - << " MCOperandNum += " << OpInfo.MINumOperands << ";\n" + << " MapAndConstraints.push_back(std::make_pair(NumMCOperands" + << ",\"r\"));\n" + << " NumMCOperands += " << OpInfo.MINumOperands << ";\n" << " break;\n"; break; } @@ -1872,11 +1864,9 @@ static void emitConvertToMCInst(CodeGenTarget &Target, StringRef ClassName, << " break;\n"; OpOS << " case " << Name << ":\n" - << " if (*(p + 1) == OperandNum) {\n" - << " NumMCOperands = 1;\n" - << " break;\n" - << " }\n" - << " ++MCOperandNum;\n" + << " MapAndConstraints.push_back(std::make_pair(NumMCOperands" + << ",\"\"));\n" + << " ++NumMCOperands;\n" << " break;\n"; break; } @@ -1905,11 +1895,9 @@ static void emitConvertToMCInst(CodeGenTarget &Target, StringRef ClassName, << " break;\n"; OpOS << " case " << Name << ":\n" - << " if (*(p + 1) == OperandNum) {\n" - << " NumMCOperands = 1;\n" - << " break;\n" - << " }\n" - << " ++MCOperandNum;\n" + << " MapAndConstraints.push_back(std::make_pair(NumMCOperands" + << ",\"r\"));\n" + << " ++NumMCOperands;\n" << " break;\n"; } } @@ -1934,7 +1922,7 @@ static void emitConvertToMCInst(CodeGenTarget &Target, StringRef ClassName, CvtOS << " }\n }\n}\n\n"; // Finish up the operand number lookup function. - OpOS << " }\n }\n return MCOperandNum;\n}\n\n"; + OpOS << " }\n }\n}\n\n"; OS << "namespace {\n"; @@ -2615,17 +2603,21 @@ void AsmMatcherEmitter::run(raw_ostream &OS) { OS << " unsigned ComputeAvailableFeatures(uint64_t FeatureBits) const;\n"; OS << " void convertToMCInst(unsigned Kind, MCInst &Inst, " << "unsigned Opcode,\n" - << " const SmallVectorImpl<MCParsedAsmOperand*> " + << " const SmallVectorImpl<MCParsedAsmOperand*> " << "&Operands);\n"; - OS << " unsigned getMCInstOperandNum(unsigned Kind,\n" - << " const " - << "SmallVectorImpl<MCParsedAsmOperand*> &Operands,\n " - << " unsigned OperandNum, unsigned &NumMCOperands);\n"; + OS << " void convertToMapAndConstraints(unsigned Kind,\n "; + OS << " const SmallVectorImpl<MCParsedAsmOperand*> &Operands,\n" + << " SmallVectorImpl<std::pair< unsigned, std::string > >" + << " &MapAndConstraints);\n"; OS << " bool mnemonicIsValid(StringRef Mnemonic);\n"; OS << " unsigned MatchInstructionImpl(\n" - << " const SmallVectorImpl<MCParsedAsmOperand*> &Operands,\n" - << " unsigned &Kind, MCInst &Inst, " - << "unsigned &ErrorInfo,\n unsigned VariantID = 0);\n"; + << " const SmallVectorImpl<MCParsedAsmOperand*> &Operands,\n" + << " unsigned &Kind, MCInst &Inst,\n" + << " SmallVectorImpl<std::pair< unsigned, std::string > > " + << "&MapAndConstraints,\n" + << " unsigned &ErrorInfo," + << " bool matchingInlineAsm,\n" + << " unsigned VariantID = 0);\n"; if (Info.OperandMatchInfo.size()) { OS << "\n enum OperandMatchResultTy {\n"; @@ -2678,8 +2670,10 @@ void AsmMatcherEmitter::run(raw_ostream &OS) { // Generate the function that remaps for mnemonic aliases. bool HasMnemonicAliases = emitMnemonicAliases(OS, Info); - // Generate the unified function to convert operands into an MCInst. - emitConvertToMCInst(Target, ClassName, Info.Matchables, OS); + // Generate the convertToMCInst function to convert operands into an MCInst. + // Also, generate the convertToMapAndConstraints function for MS-style inline + // assembly. The latter doesn't actually generate a MCInst. + emitConvertFuncs(Target, ClassName, Info.Matchables, OS); // Emit the enumeration for classes which participate in matching. emitMatchClassEnumeration(Target, Info.Classes, OS); @@ -2813,8 +2807,9 @@ void AsmMatcherEmitter::run(raw_ostream &OS) { << Target.getName() << ClassName << "::\n" << "MatchInstructionImpl(const SmallVectorImpl<MCParsedAsmOperand*>" << " &Operands,\n"; - OS << " unsigned &Kind, MCInst &Inst, unsigned "; - OS << "&ErrorInfo,\n unsigned VariantID) {\n"; + OS << " unsigned &Kind, MCInst &Inst,\n" + << "SmallVectorImpl<std::pair< unsigned, std::string > > &MapAndConstraints,\n" + << "unsigned &ErrorInfo, bool matchingInlineAsm, unsigned VariantID) {\n"; OS << " // Eliminate obvious mismatches.\n"; OS << " if (Operands.size() > " << (MaxNumOperands+1) << ") {\n"; @@ -2908,6 +2903,13 @@ void AsmMatcherEmitter::run(raw_ostream &OS) { OS << " continue;\n"; OS << " }\n"; OS << "\n"; + OS << " if (matchingInlineAsm) {\n"; + OS << " Kind = it->ConvertFn;\n"; + OS << " Inst.setOpcode(it->Opcode);\n"; + OS << " convertToMapAndConstraints(it->ConvertFn, Operands, " + << "MapAndConstraints);\n"; + OS << " return Match_Success;\n"; + OS << " }\n\n"; OS << " // We have selected a definite instruction, convert the parsed\n" << " // operands into the appropriate MCInst.\n"; OS << " convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands);\n"; @@ -2931,7 +2933,6 @@ void AsmMatcherEmitter::run(raw_ostream &OS) { if (!InsnCleanupFn.empty()) OS << " " << InsnCleanupFn << "(Inst);\n"; - OS << " Kind = it->ConvertFn;\n"; OS << " return Match_Success;\n"; OS << " }\n\n"; |