diff options
author | Tim Northover <tnorthover@apple.com> | 2014-04-24 14:06:20 +0000 |
---|---|---|
committer | Tim Northover <tnorthover@apple.com> | 2014-04-24 14:06:20 +0000 |
commit | a05d37e1f425c1f83fa38d069957da83b7ac54d4 (patch) | |
tree | fcea3a001ddef255ea87185c775ae8932e1f827b /test/MC/Disassembler | |
parent | 23a4885f59511eb4781e534a3b2a5910733cb357 (diff) |
AArch64: print NEON lists with a space.
This matches ARM64 behaviour, which I think is clearer. It also puts all the
churn from that difference into one easily ignored commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207116 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/MC/Disassembler')
-rw-r--r-- | test/MC/Disassembler/AArch64/neon-instructions.txt | 154 |
1 files changed, 77 insertions, 77 deletions
diff --git a/test/MC/Disassembler/AArch64/neon-instructions.txt b/test/MC/Disassembler/AArch64/neon-instructions.txt index 863730ac6be..2a0b3804505 100644 --- a/test/MC/Disassembler/AArch64/neon-instructions.txt +++ b/test/MC/Disassembler/AArch64/neon-instructions.txt @@ -2008,34 +2008,34 @@ #---------------------------------------------------------------------- # Vector load/store multiple N-element structure #---------------------------------------------------------------------- -# CHECK: ld1 {v0.16b}, [x0] -# CHECK: ld1 {v15.8h, v16.8h}, [x15] -# CHECK: ld1 {v31.4s, v0.4s, v1.4s}, [sp] -# CHECK: ld1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] +# CHECK: ld1 { v0.16b }, [x0] +# CHECK: ld1 { v15.8h, v16.8h }, [x15] +# CHECK: ld1 { v31.4s, v0.4s, v1.4s }, [sp] +# CHECK: ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0] 0x00,0x70,0x40,0x4c 0xef,0xa5,0x40,0x4c 0xff,0x6b,0x40,0x4c 0x00,0x2c,0x40,0x4c -# CHECK: ld2 {v0.8b, v1.8b}, [x0] -# CHECK: ld3 {v15.4h, v16.4h, v17.4h}, [x15] -# CHECK: ld4 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] +# CHECK: ld2 { v0.8b, v1.8b }, [x0] +# CHECK: ld3 { v15.4h, v16.4h, v17.4h }, [x15] +# CHECK: ld4 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp] 0x00,0x80,0x40,0x0c 0xef,0x45,0x40,0x0c 0xff,0x0b,0x40,0x0c -# CHECK: st1 {v0.16b}, [x0] -# CHECK: st1 {v15.8h, v16.8h}, [x15] -# CHECK: st1 {v31.4s, v0.4s, v1.4s}, [sp] -# CHECK: st1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] +# CHECK: st1 { v0.16b }, [x0] +# CHECK: st1 { v15.8h, v16.8h }, [x15] +# CHECK: st1 { v31.4s, v0.4s, v1.4s }, [sp] +# CHECK: st1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0] 0x00,0x70,0x00,0x4c 0xef,0xa5,0x00,0x4c 0xff,0x6b,0x00,0x4c 0x00,0x2c,0x00,0x4c -# CHECK: st2 {v0.8b, v1.8b}, [x0] -# CHECK: st3 {v15.4h, v16.4h, v17.4h}, [x15] -# CHECK: st4 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] +# CHECK: st2 { v0.8b, v1.8b }, [x0] +# CHECK: st3 { v15.4h, v16.4h, v17.4h }, [x15] +# CHECK: st4 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp] 0x00,0x80,0x00,0x0c 0xef,0x45,0x00,0x0c 0xff,0x0b,0x00,0x0c @@ -2043,35 +2043,35 @@ #---------------------------------------------------------------------- # Vector load/store multiple N-element structure (post-index) #---------------------------------------------------------------------- -# CHECK: ld1 {v15.8h}, [x15], x2 -# CHECK: ld1 {v31.4s, v0.4s}, [sp], #32 -# CHECK: ld1 {v0.2d, v1.2d, v2.2d}, [x0], #48 -# CHECK: ld1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x3 +# CHECK: ld1 { v15.8h }, [x15], x2 +# CHECK: ld1 { v31.4s, v0.4s }, [sp], #32 +# CHECK: ld1 { v0.2d, v1.2d, v2.2d }, [x0], #48 +# CHECK: ld1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x3 0xef,0x75,0xc2,0x4c 0xff,0xab,0xdf,0x4c 0x00,0x6c,0xdf,0x4c 0x00,0x20,0xc3,0x0c -# CHECK: ld2 {v0.16b, v1.16b}, [x0], x1 -# CHECK: ld3 {v15.8h, v16.8h, v17.8h}, [x15], x2 -# CHECK: ld4 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #64 +# CHECK: ld2 { v0.16b, v1.16b }, [x0], x1 +# CHECK: ld3 { v15.8h, v16.8h, v17.8h }, [x15], x2 +# CHECK: ld4 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp], #64 0x00,0x80,0xc1,0x4c 0xef,0x45,0xc2,0x4c 0xff,0x0b,0xdf,0x4c -# CHECK: st1 {v15.8h}, [x15], x2 -# CHECK: st1 {v31.4s, v0.4s}, [sp], #32 -# CHECK: st1 {v0.2d, v1.2d, v2.2d}, [x0], #48 -# CHECK: st1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x3 +# CHECK: st1 { v15.8h }, [x15], x2 +# CHECK: st1 { v31.4s, v0.4s }, [sp], #32 +# CHECK: st1 { v0.2d, v1.2d, v2.2d }, [x0], #48 +# CHECK: st1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x3 0xef,0x75,0x82,0x4c 0xff,0xab,0x9f,0x4c 0x00,0x6c,0x9f,0x4c 0x00,0x20,0x83,0x0c -# CHECK: st2 {v0.16b, v1.16b}, [x0], x1 -# CHECK: st3 {v15.8h, v16.8h, v17.8h}, [x15], x2 -# CHECK: st4 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #64 +# CHECK: st2 { v0.16b, v1.16b }, [x0], x1 +# CHECK: st3 { v15.8h, v16.8h, v17.8h }, [x15], x2 +# CHECK: st4 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp], #64 0x00,0x80,0x81,0x4c 0xef,0x45,0x82,0x4c 0xff,0x0b,0x9f,0x4c @@ -2080,14 +2080,14 @@ # Vector load single N-element structure to all lane of N # consecutive registers (N = 1,2,3,4) #---------------------------------------------------------------------- -# CHECK: ld1r {v0.16b}, [x0] -# CHECK: ld1r {v15.8h}, [x15] -# CHECK: ld2r {v31.4s, v0.4s}, [sp] -# CHECK: ld2r {v0.2d, v1.2d}, [x0] -# CHECK: ld3r {v0.8b, v1.8b, v2.8b}, [x0] -# CHECK: ld3r {v15.4h, v16.4h, v17.4h}, [x15] -# CHECK: ld4r {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] -# CHECK: ld4r {v31.1d, v0.1d, v1.1d, v2.1d}, [sp] +# CHECK: ld1r { v0.16b }, [x0] +# CHECK: ld1r { v15.8h }, [x15] +# CHECK: ld2r { v31.4s, v0.4s }, [sp] +# CHECK: ld2r { v0.2d, v1.2d }, [x0] +# CHECK: ld3r { v0.8b, v1.8b, v2.8b }, [x0] +# CHECK: ld3r { v15.4h, v16.4h, v17.4h }, [x15] +# CHECK: ld4r { v31.2s, v0.2s, v1.2s, v2.2s }, [sp] +# CHECK: ld4r { v31.1d, v0.1d, v1.1d, v2.1d }, [sp] 0x00,0xc0,0x40,0x4d 0xef,0xc5,0x40,0x4d 0xff,0xcb,0x60,0x4d @@ -2101,14 +2101,14 @@ # Vector load/store single N-element structure to/from one lane of N # consecutive registers (N = 1,2,3,4) #---------------------------------------------------------------------- -# CHECK: ld1 {v0.b}[9], [x0] -# CHECK: ld2 {v15.h, v16.h}[7], [x15] -# CHECK: ld3 {v31.s, v0.s, v1.s}[3], [sp] -# CHECK: ld4 {v0.d, v1.d, v2.d, v3.d}[1], [x0] -# CHECK: st1 {v0.d}[1], [x0] -# CHECK: st2 {v31.s, v0.s}[3], [sp] -# CHECK: st3 {v15.h, v16.h, v17.h}[7], [x15] -# CHECK: st4 {v0.b, v1.b, v2.b, v3.b}[9], [x0] +# CHECK: ld1 { v0.b }[9], [x0] +# CHECK: ld2 { v15.h, v16.h }[7], [x15] +# CHECK: ld3 { v31.s, v0.s, v1.s }[3], [sp] +# CHECK: ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x0] +# CHECK: st1 { v0.d }[1], [x0] +# CHECK: st2 { v31.s, v0.s }[3], [sp] +# CHECK: st3 { v15.h, v16.h, v17.h }[7], [x15] +# CHECK: st4 { v0.b, v1.b, v2.b, v3.b }[9], [x0] 0x00,0x04,0x40,0x4d 0xef,0x59,0x60,0x4d 0xff,0xb3,0x40,0x4d @@ -2122,14 +2122,14 @@ # Post-index of vector load single N-element structure to all lane of N # consecutive registers (N = 1,2,3,4) #---------------------------------------------------------------------- -# CHECK: ld1r {v0.16b}, [x0], #1 -# CHECK: ld1r {v15.8h}, [x15], #2 -# CHECK: ld2r {v31.4s, v0.4s}, [sp], #8 -# CHECK: ld2r {v0.2d, v1.2d}, [x0], #16 -# CHECK: ld3r {v0.8b, v1.8b, v2.8b}, [x0], #3 -# CHECK: ld3r {v15.4h, v16.4h, v17.4h}, [x15], #6 -# CHECK: ld4r {v31.2s, v0.2s, v1.2s, v2.2s}, [sp], x30 -# CHECK: ld4r {v31.1d, v0.1d, v1.1d, v2.1d}, [sp], x7 +# CHECK: ld1r { v0.16b }, [x0], #1 +# CHECK: ld1r { v15.8h }, [x15], #2 +# CHECK: ld2r { v31.4s, v0.4s }, [sp], #8 +# CHECK: ld2r { v0.2d, v1.2d }, [x0], #16 +# CHECK: ld3r { v0.8b, v1.8b, v2.8b }, [x0], #3 +# CHECK: ld3r { v15.4h, v16.4h, v17.4h }, [x15], #6 +# CHECK: ld4r { v31.2s, v0.2s, v1.2s, v2.2s }, [sp], x30 +# CHECK: ld4r { v31.1d, v0.1d, v1.1d, v2.1d }, [sp], x7 0x00,0xc0,0xdf,0x4d 0xef,0xc5,0xdf,0x4d 0xff,0xcb,0xff,0x4d @@ -2143,15 +2143,15 @@ # Post-index of vector load/store single N-element structure to/from # one lane of N consecutive registers (N = 1,2,3,4) #---------------------------------------------------------------------- -# CHECK: ld1 {v0.b}[9], [x0], #1 -# CHECK: ld2 {v15.h, v16.h}[7], [x15], #4 -# CHECK: ld3 {v31.s, v0.s, v1.s}[3], [sp], x3 -# CHECK: ld4 {v0.d, v1.d, v2.d, v3.d}[1], [x0], #32 -# CHECK: ld4 {v0.h, v1.h, v2.h, v3.h}[7], [x0], x0 -# CHECK: st1 {v0.d}[1], [x0], #8 -# CHECK: st2 {v31.s, v0.s}[3], [sp], #8 -# CHECK: st3 {v15.h, v16.h, v17.h}[7], [x15], #6 -# CHECK: st4 {v0.b, v1.b, v2.b, v3.b}[9], [x0], x5 +# CHECK: ld1 { v0.b }[9], [x0], #1 +# CHECK: ld2 { v15.h, v16.h }[7], [x15], #4 +# CHECK: ld3 { v31.s, v0.s, v1.s }[3], [sp], x3 +# CHECK: ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x0], #32 +# CHECK: ld4 { v0.h, v1.h, v2.h, v3.h }[7], [x0], x0 +# CHECK: st1 { v0.d }[1], [x0], #8 +# CHECK: st2 { v31.s, v0.s }[3], [sp], #8 +# CHECK: st3 { v15.h, v16.h, v17.h }[7], [x15], #6 +# CHECK: st4 { v0.b, v1.b, v2.b, v3.b }[9], [x0], x5 0x00,0x04,0xdf,0x4d 0xef,0x59,0xff,0x4d 0xff,0xb3,0xc3,0x4d @@ -2497,37 +2497,37 @@ 0xf0,0x23,0x02,0x0e 0x20,0x40,0x02,0x0e 0xf0,0x62,0x02,0x0e -# CHECK: tbl v0.8b, {v1.16b}, v2.8b -# CHECK: tbl v16.8b, {v31.16b, v0.16b}, v2.8b -# CHECK: tbl v0.8b, {v1.16b, v2.16b, v3.16b}, v2.8b -# CHECK: tbl v16.8b, {v23.16b, v24.16b, v25.16b, v26.16b}, v2.8b +# CHECK: tbl v0.8b, { v1.16b }, v2.8b +# CHECK: tbl v16.8b, { v31.16b, v0.16b }, v2.8b +# CHECK: tbl v0.8b, { v1.16b, v2.16b, v3.16b }, v2.8b +# CHECK: tbl v16.8b, { v23.16b, v24.16b, v25.16b, v26.16b }, v2.8b 0x20,0x00,0x02,0x4e 0xf0,0x23,0x02,0x4e 0x20,0x40,0x02,0x4e 0xe0,0x63,0x02,0x4e -# CHECK: tbl v0.16b, {v1.16b}, v2.16b -# CHECK: tbl v16.16b, {v31.16b, v0.16b}, v2.16b -# CHECK: tbl v0.16b, {v1.16b, v2.16b, v3.16b}, v2.16b -# CHECK: tbl v0.16b, {v31.16b, v0.16b, v1.16b, v2.16b}, v2.16b +# CHECK: tbl v0.16b, { v1.16b }, v2.16b +# CHECK: tbl v16.16b, { v31.16b, v0.16b }, v2.16b +# CHECK: tbl v0.16b, { v1.16b, v2.16b, v3.16b }, v2.16b +# CHECK: tbl v0.16b, { v31.16b, v0.16b, v1.16b, v2.16b }, v2.16b 0x20,0x10,0x02,0x0e 0xf0,0x33,0x02,0x0e 0x20,0x50,0x02,0x0e 0xf0,0x72,0x02,0x0e -# CHECK: tbx v0.8b, {v1.16b}, v2.8b -# CHECK: tbx v16.8b, {v31.16b, v0.16b}, v2.8b -# CHECK: tbx v0.8b, {v1.16b, v2.16b, v3.16b}, v2.8b -# CHECK: tbx v16.8b, {v23.16b, v24.16b, v25.16b, v26.16b}, v2.8b +# CHECK: tbx v0.8b, { v1.16b }, v2.8b +# CHECK: tbx v16.8b, { v31.16b, v0.16b }, v2.8b +# CHECK: tbx v0.8b, { v1.16b, v2.16b, v3.16b }, v2.8b +# CHECK: tbx v16.8b, { v23.16b, v24.16b, v25.16b, v26.16b }, v2.8b 0x20,0x10,0x02,0x4e 0xf0,0x33,0x02,0x4e 0x20,0x50,0x02,0x4e 0xf0,0x73,0x02,0x4e -# CHECK: tbx v0.16b, {v1.16b}, v2.16b -# CHECK: tbx v16.16b, {v31.16b, v0.16b}, v2.16b -# CHECK: tbx v0.16b, {v1.16b, v2.16b, v3.16b}, v2.16b -# CHECK: tbx v16.16b, {v31.16b, v0.16b, v1.16b, v2.16b}, v2.16b +# CHECK: tbx v0.16b, { v1.16b }, v2.16b +# CHECK: tbx v16.16b, { v31.16b, v0.16b }, v2.16b +# CHECK: tbx v0.16b, { v1.16b, v2.16b, v3.16b }, v2.16b +# CHECK: tbx v16.16b, { v31.16b, v0.16b, v1.16b, v2.16b }, v2.16b #---------------------------------------------------------------------- # Scalar Floating-point Convert To Lower Precision Narrow, Rounding To |