diff options
| author | Amara Emerson <amara.emerson@arm.com> | 2013-09-19 11:59:01 +0000 |
|---|---|---|
| committer | Amara Emerson <amara.emerson@arm.com> | 2013-09-19 11:59:01 +0000 |
| commit | 5df37dab763ce377095389c4ea1cff88db369954 (patch) | |
| tree | e28c008ced1c69d4397ef1a020b186c1d9dc3cbb /test/MC/ARM/invalid-neon-v8.s | |
| parent | adadf887cb57f8281ec23f846a946fb59bd0a0d7 (diff) | |
[ARMv8] Add support for the v8 cryptography extensions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190996 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/MC/ARM/invalid-neon-v8.s')
| -rw-r--r-- | test/MC/ARM/invalid-neon-v8.s | 46 |
1 files changed, 45 insertions, 1 deletions
diff --git a/test/MC/ARM/invalid-neon-v8.s b/test/MC/ARM/invalid-neon-v8.s index 06406f3f9ca..7aaf2778a8a 100644 --- a/test/MC/ARM/invalid-neon-v8.s +++ b/test/MC/ARM/invalid-neon-v8.s @@ -1,4 +1,4 @@ -@ RUN: not llvm-mc -triple armv8 -mattr=+neon -show-encoding < %s 2>&1 | FileCheck %s +@ RUN: not llvm-mc -triple armv8 -mattr=+neon,+crypto -show-encoding < %s 2>&1 | FileCheck %s vmaxnm.f32 s4, d5, q1 @ CHECK: error: invalid operand for instruction @@ -24,3 +24,47 @@ vrintz.f32 d3, q12 @ CHECK: error: invalid operand for instruction vrintmge.f32.f32 d3, d4 @ CHECK: error: instruction 'vrintm' is not predicable, but condition code specified + +aesd.8 q0, s1 +@ CHECK: error: invalid operand for instruction +aese.8 s0, q1 +@ CHECK: error: invalid operand for instruction +aesimc.8 s0, q1 +@ CHECK: error: invalid operand for instruction +aesmc.8 q0, d1 +@ CHECK: error: invalid operand for instruction +aesdge.8 q0, q1 +@ CHECK: error: instruction 'aesd' is not predicable, but condition code specified + +sha1h.32 d0, q1 +@ CHECK: error: invalid operand for instruction +sha1su1.32 q0, s1 +@ CHECK: error: invalid operand for instruction +sha256su0.32 s0, q1 +@ CHECK: error: invalid operand for instruction +sha1heq.32 q0, q1 +@ CHECK: error: instruction 'sha1h' is not predicable, but condition code specified + +sha1c.32 s0, d1, q2 +@ CHECK: error: invalid operand for instruction +sha1m.32 q0, s1, q2 +@ CHECK: error: invalid operand for instruction +sha1p.32 s0, q1, q2 +@ CHECK: error: invalid operand for instruction +sha1su0.32 d0, q1, q2 +@ CHECK: error: invalid operand for instruction +sha256h.32 q0, s1, q2 +@ CHECK: error: invalid operand for instruction +sha256h2.32 q0, q1, s2 +@ CHECK: error: invalid operand for instruction +sha256su1.32 s0, d1, q2 +@ CHECK: error: invalid operand for instruction +sha256su1lt.32 q0, d1, q2 +@ CHECK: error: instruction 'sha256su1' is not predicable, but condition code specified + +vmull.p64 q0, s1, s3 +@ CHECK: error: invalid operand for instruction +vmull.p64 s1, d2, d3 +@ CHECK: error: invalid operand for instruction +vmullge.p64 q0, d16, d17 +@ CHECK: error: instruction 'vmull' is not predicable, but condition code specified |