summaryrefslogtreecommitdiff
path: root/lib
diff options
context:
space:
mode:
authorTim Northover <tnorthover@apple.com>2014-05-14 14:44:18 +0000
committerTim Northover <tnorthover@apple.com>2014-05-14 14:44:18 +0000
commitfcb05f0fdae1c7d1159dc0432ee7e69df819428c (patch)
treecb3aec0529d11aaf631387b7357f18c0f4d7ed9d /lib
parentc413e016723673ca93d5700c72083194ac21b766 (diff)
ARM64: remove unneeded InstPrinter hacks
Now that TableGen handles aliases, these are unneeded. Hopefully more will be able to go soon. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208781 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r--lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp32
1 files changed, 0 insertions, 32 deletions
diff --git a/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp b/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp
index 6002dc93836..304bc561a97 100644
--- a/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp
+++ b/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp
@@ -301,38 +301,6 @@ void ARM64InstPrinter::printInst(const MCInst *MI, raw_ostream &O,
printExtend(MI, 3, O);
return;
}
- // ADD WSP, Wn, #0 ==> MOV WSP, Wn
- if (Opcode == ARM64::ADDWri && (MI->getOperand(0).getReg() == ARM64::WSP ||
- MI->getOperand(1).getReg() == ARM64::WSP) &&
- MI->getOperand(2).getImm() == 0 &&
- ARM64_AM::getShiftValue(MI->getOperand(3).getImm()) == 0) {
- O << "\tmov\t" << getRegisterName(MI->getOperand(0).getReg())
- << ", " << getRegisterName(MI->getOperand(1).getReg());
- return;
- }
- // ADD XSP, Wn, #0 ==> MOV XSP, Wn
- if (Opcode == ARM64::ADDXri && (MI->getOperand(0).getReg() == ARM64::SP ||
- MI->getOperand(1).getReg() == ARM64::SP) &&
- MI->getOperand(2).getImm() == 0 &&
- ARM64_AM::getShiftValue(MI->getOperand(3).getImm()) == 0) {
- O << "\tmov\t" << getRegisterName(MI->getOperand(0).getReg())
- << ", " << getRegisterName(MI->getOperand(1).getReg());
- return;
- }
- // ORR Wn, WZR, Wm ==> MOV Wn, Wm
- if (Opcode == ARM64::ORRWrs && MI->getOperand(1).getReg() == ARM64::WZR &&
- MI->getOperand(3).getImm() == 0) {
- O << "\tmov\t" << getRegisterName(MI->getOperand(0).getReg())
- << ", " << getRegisterName(MI->getOperand(2).getReg());
- return;
- }
- // ORR Xn, XZR, Xm ==> MOV Xn, Xm
- if (Opcode == ARM64::ORRXrs && MI->getOperand(1).getReg() == ARM64::XZR &&
- MI->getOperand(3).getImm() == 0) {
- O << "\tmov\t" << getRegisterName(MI->getOperand(0).getReg())
- << ", " << getRegisterName(MI->getOperand(2).getReg());
- return;
- }
if (!printAliasInstr(MI, O))
printInstruction(MI, O);