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authorBradley Smith <bradley.smith@arm.com>2014-05-15 11:08:30 +0000
committerBradley Smith <bradley.smith@arm.com>2014-05-15 11:08:30 +0000
commit75aa5372bcf4e58c9ae4ef0b9aae86993b39c338 (patch)
treeb7980ad29264c86b362e2b2dae87981137d2a5da /lib
parente7856db5836be46ec59f5c4a2396908ccd5c011a (diff)
[ARM64] Improve load/store diagnostics and forbid 32-bit register addresses
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208864 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r--lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp13
1 files changed, 11 insertions, 2 deletions
diff --git a/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp b/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp
index a1f0c6aa3ed..a68f4db633a 100644
--- a/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp
+++ b/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp
@@ -2985,12 +2985,16 @@ bool ARM64AsmParser::parseMemory(OperandVector &Operands) {
Parser.Lex(); // Eat left bracket token.
const AsmToken &BaseRegTok = Parser.getTok();
+ SMLoc BaseRegLoc = BaseRegTok.getLoc();
if (BaseRegTok.isNot(AsmToken::Identifier))
- return Error(BaseRegTok.getLoc(), "register expected");
+ return Error(BaseRegLoc, "register expected");
int64_t Reg = tryParseRegister();
if (Reg == -1)
- return Error(BaseRegTok.getLoc(), "register expected");
+ return Error(BaseRegLoc, "register expected");
+
+ if (!ARM64MCRegisterClasses[ARM64::GPR64spRegClassID].contains(Reg))
+ return Error(BaseRegLoc, "invalid operand for instruction");
// If there is an offset expression, parse it.
const MCExpr *OffsetExpr = nullptr;
@@ -4148,6 +4152,10 @@ bool ARM64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
// diagnose.
MatchResult = Match_InvalidMemoryIndexed;
}
+ else if(Operands.size() == 3 && Operands.size() == ErrorInfo + 1 &&
+ ((ARM64Operand *)Operands[ErrorInfo])->isImm()) {
+ MatchResult = Match_InvalidLabel;
+ }
SMLoc ErrorLoc = ((ARM64Operand *)Operands[ErrorInfo])->getStartLoc();
if (ErrorLoc == SMLoc())
ErrorLoc = IDLoc;
@@ -4172,6 +4180,7 @@ bool ARM64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
case Match_InvalidMovImm32Shift:
case Match_InvalidMovImm64Shift:
case Match_InvalidFPImm:
+ case Match_InvalidMemoryIndexed:
case Match_InvalidMemoryIndexed8:
case Match_InvalidMemoryIndexed16:
case Match_InvalidMemoryIndexed32SImm7: