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author | Zoran Jovanovic <zoran.jovanovic@imgtec.com> | 2014-05-15 15:16:36 +0000 |
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committer | Zoran Jovanovic <zoran.jovanovic@imgtec.com> | 2014-05-15 15:16:36 +0000 |
commit | 1f05322d96319651c484a90eead4cebd6bd67ad3 (patch) | |
tree | 7b39d8e05c8f26c7d3f1e9269349a08c3312b356 /lib | |
parent | 75999124df3ae89f46e5a0c551dee31faa3210d0 (diff) |
[mips][mips64r6] Add CLASS.fmt instructions
Differential Revision: http://reviews.llvm.org/D3712
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208894 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r-- | lib/Target/Mips/Mips32r6InstrInfo.td | 14 |
1 files changed, 9 insertions, 5 deletions
diff --git a/lib/Target/Mips/Mips32r6InstrInfo.td b/lib/Target/Mips/Mips32r6InstrInfo.td index a2bcfe19179..41bbae105c1 100644 --- a/lib/Target/Mips/Mips32r6InstrInfo.td +++ b/lib/Target/Mips/Mips32r6InstrInfo.td @@ -92,6 +92,8 @@ class SELNEZ_D_ENC : COP1_3R_FM<0b010111, FIELD_FMT_D>; class RINT_S_ENC : COP1_2R_FM<0b011010, FIELD_FMT_S>; class RINT_D_ENC : COP1_2R_FM<0b011010, FIELD_FMT_D>; +class CLASS_S_ENC : COP1_2R_FM<0b011011, FIELD_FMT_S>; +class CLASS_D_ENC : COP1_2R_FM<0b011011, FIELD_FMT_D>; //===----------------------------------------------------------------------===// // @@ -210,15 +212,17 @@ class SELEQZ_D_DESC : SELEQNEZ_DESC_BASE<"seleqz.d", FGR64Opnd>; class SELNEZ_S_DESC : SELEQNEZ_DESC_BASE<"selnez.s", FGR32Opnd>; class SELNEZ_D_DESC : SELEQNEZ_DESC_BASE<"selnez.d", FGR64Opnd>; -class RINT_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> { +class CLASS_RINT_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> { dag OutOperandList = (outs FGROpnd:$fd); dag InOperandList = (ins FGROpnd:$fs); string AsmString = !strconcat(instr_asm, "\t$fd, $fs"); list<dag> Pattern = []; } -class RINT_S_DESC : RINT_DESC_BASE<"rint.s", FGR32Opnd>; -class RINT_D_DESC : RINT_DESC_BASE<"rint.d", FGR64Opnd>; +class RINT_S_DESC : CLASS_RINT_DESC_BASE<"rint.s", FGR32Opnd>; +class RINT_D_DESC : CLASS_RINT_DESC_BASE<"rint.d", FGR64Opnd>; +class CLASS_S_DESC : CLASS_RINT_DESC_BASE<"class.s", FGR32Opnd>; +class CLASS_D_DESC : CLASS_RINT_DESC_BASE<"class.d", FGR64Opnd>; //===----------------------------------------------------------------------===// // @@ -258,8 +262,8 @@ def BNEZALC; def BNEZC; def BNVC; def BOVC; -def CLASS_D; -def CLASS_S; +def CLASS_D : CLASS_D_ENC, CLASS_D_DESC, ISA_MIPS32R6; +def CLASS_S : CLASS_S_ENC, CLASS_S_DESC, ISA_MIPS32R6; def CMP_CC_D; def CMP_CC_S; def DIV : DIV_ENC, DIV_DESC, ISA_MIPS32R6; |