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authorTim Northover <Tim.Northover@arm.com>2013-04-19 15:44:32 +0000
committerTim Northover <Tim.Northover@arm.com>2013-04-19 15:44:32 +0000
commitd3af696c08923d4d376641b52c3b2cb5baa00487 (patch)
tree72d397c081e52da5e936067f96cb2942bc981ae6 /lib
parent143d223447cb55ae08d313078f7a5917873247ae (diff)
ARM: Permit "sp" in ARM variant of STREXD instructions
Patch from Mihail Popa git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179854 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r--lib/Target/ARM/Disassembler/ARMDisassembler.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index 631168b1539..32b47fba514 100644
--- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -3573,7 +3573,7 @@ static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
unsigned Rn = fieldFromInstruction(Insn, 16, 4);
unsigned pred = fieldFromInstruction(Insn, 28, 4);
- if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
+ if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail;
if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;