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authorAkira Hatanaka <ahatanaka@mips.com>2013-04-19 18:47:40 +0000
committerAkira Hatanaka <ahatanaka@mips.com>2013-04-19 18:47:40 +0000
commit8d99ec574849ca8266e6491ceafee6c6029692b3 (patch)
tree35b2159779811a3865c99556f3696f6973d7d96c /lib
parente43624e345bcef09d4d57dca2c27d33cb6a34edd (diff)
[mips] Fix InstAlias of XOR and OR macros. Set EmitAlias flag and change
operand type to uimm16. Patch by Vladimir Medic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179872 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r--lib/Target/Mips/MipsInstrInfo.td4
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td
index 44e9fb8dcb5..44f7ed95099 100644
--- a/lib/Target/Mips/MipsInstrInfo.td
+++ b/lib/Target/Mips/MipsInstrInfo.td
@@ -1067,10 +1067,10 @@ def : InstAlias<"negu $rt, $rs",
def : InstAlias<"slt $rs, $rt, $imm",
(SLTi CPURegsOpnd:$rs, CPURegs:$rt, simm16:$imm), 0>;
def : InstAlias<"xor $rs, $rt, $imm",
- (XORi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>,
+ (XORi CPURegsOpnd:$rs, CPURegsOpnd:$rt, uimm16:$imm), 1>,
Requires<[NotMips64]>;
def : InstAlias<"or $rs, $rt, $imm",
- (ORi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>,
+ (ORi CPURegsOpnd:$rs, CPURegsOpnd:$rt, uimm16:$imm), 1>,
Requires<[NotMips64]>;
def : InstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
def : InstAlias<"mfc0 $rt, $rd",