diff options
| author | Tom Stellard <thomas.stellard@amd.com> | 2012-09-06 15:41:59 -0400 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2012-09-21 16:41:34 +0000 |
| commit | a39b9b80e0098622a89aa020e087986164a32781 (patch) | |
| tree | cf0f3890cda5f4b7abad562d96f201836d867181 /lib | |
| parent | 6f8049970905130d046251bd0c0870197ba30865 (diff) | |
radeonsi: Move interpolation mode check into the compiler
The compiler needs to know which interpolation modes are enabled, so
it knows which values will be preloaded into the VGPRs.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/AMDGPU/SIAssignInterpRegs.cpp | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/lib/Target/AMDGPU/SIAssignInterpRegs.cpp b/lib/Target/AMDGPU/SIAssignInterpRegs.cpp index 447eff6f5ac..0e36e6b8b78 100644 --- a/lib/Target/AMDGPU/SIAssignInterpRegs.cpp +++ b/lib/Target/AMDGPU/SIAssignInterpRegs.cpp @@ -52,6 +52,7 @@ public: char SIAssignInterpRegsPass::ID = 0; #define INTERP_VALUES 16 +#define REQUIRED_VALUE_MAX_INDEX 7 struct interp_info { bool enabled; @@ -92,16 +93,26 @@ bool SIAssignInterpRegsPass::runOnMachineFunction(MachineFunction &MF) return false; } MachineRegisterInfo &MRI = MF.getRegInfo(); + bool ForceEnable = true; /* First pass, mark the interpolation values that are used. */ for (unsigned interp_idx = 0; interp_idx < INTERP_VALUES; interp_idx++) { for (unsigned reg_idx = 0; reg_idx < InterpUse[interp_idx].reg_count; reg_idx++) { - InterpUse[interp_idx].enabled = + InterpUse[interp_idx].enabled = InterpUse[interp_idx].enabled || !MRI.use_empty(InterpUse[interp_idx].regs[reg_idx]); + if (InterpUse[interp_idx].enabled && + interp_idx <= REQUIRED_VALUE_MAX_INDEX) { + ForceEnable = false; + } } } + // At least one interpolation mode must be enabled or else the GPU will hang. + if (ForceEnable) { + InterpUse[0].enabled = true; + } + unsigned used_vgprs = 0; /* Second pass, replace with VGPRs. */ |