diff options
| author | David Majnemer <david.majnemer@gmail.com> | 2014-11-22 20:00:38 +0000 |
|---|---|---|
| committer | David Majnemer <david.majnemer@gmail.com> | 2014-11-22 20:00:38 +0000 |
| commit | 89bcfdb9563494fe8bcd1a415bc8108f682dd0a9 (patch) | |
| tree | 20ad3572097e0610b105f1371e9b9356ad8c3514 /lib/Transforms/InstCombine/InstCombineMulDivRem.cpp | |
| parent | 91349eecb018508804d9e78f57703678cfaf2caf (diff) | |
InstCombine: Propagate exact for (sdiv X, Y) -> (udiv X, Y)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222624 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Transforms/InstCombine/InstCombineMulDivRem.cpp')
| -rw-r--r-- | lib/Transforms/InstCombine/InstCombineMulDivRem.cpp | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp b/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp index b79f55e1435..216177ff2b4 100644 --- a/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp +++ b/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp @@ -1097,7 +1097,9 @@ Instruction *InstCombiner::visitSDiv(BinaryOperator &I) { if (MaskedValueIsZero(Op0, Mask, 0, &I)) { if (MaskedValueIsZero(Op1, Mask, 0, &I)) { // X sdiv Y -> X udiv Y, iff X and Y don't have sign bit set - return BinaryOperator::CreateUDiv(Op0, Op1, I.getName()); + auto *BO = BinaryOperator::CreateUDiv(Op0, Op1, I.getName()); + BO->setIsExact(I.isExact()); + return BO; } if (match(Op1, m_Shl(m_Power2(), m_Value()))) { |