diff options
author | Zoran Jovanovic <zoran.jovanovic@imgtec.com> | 2014-05-15 15:04:37 +0000 |
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committer | Zoran Jovanovic <zoran.jovanovic@imgtec.com> | 2014-05-15 15:04:37 +0000 |
commit | 75999124df3ae89f46e5a0c551dee31faa3210d0 (patch) | |
tree | 6c53c96921207993c3456ae00ec3e6a349a08731 /lib/Target | |
parent | c8d4dfc48b641caefadaae9d3e1e8d8cd3e14b55 (diff) |
[mips][mips64r6] Add RINT.fmt instructions
Differential Revision: http://reviews.llvm.org/D3711
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208892 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
-rw-r--r-- | lib/Target/Mips/Mips32r6InstrFormats.td | 14 | ||||
-rw-r--r-- | lib/Target/Mips/Mips32r6InstrInfo.td | 17 |
2 files changed, 29 insertions, 2 deletions
diff --git a/lib/Target/Mips/Mips32r6InstrFormats.td b/lib/Target/Mips/Mips32r6InstrFormats.td index 505f0f9b5bf..b07b407984a 100644 --- a/lib/Target/Mips/Mips32r6InstrFormats.td +++ b/lib/Target/Mips/Mips32r6InstrFormats.td @@ -81,6 +81,20 @@ class DAUI_FM : AUI_FM { let Inst{31-26} = OPGROUP_DAUI.Value; } +class COP1_2R_FM<bits<6> funct, FIELD_FMT Format> : MipsR6Inst { + bits<5> fs; + bits<5> fd; + + bits<32> Inst; + + let Inst{31-26} = OPGROUP_COP1.Value; + let Inst{25-21} = Format.Value; + let Inst{20-16} = 0b00000; + let Inst{15-11} = fs; + let Inst{10-6} = fd; + let Inst{5-0} = funct; +} + class COP1_3R_FM<bits<6> funct, FIELD_FMT Format> : MipsR6Inst { bits<5> ft; bits<5> fs; diff --git a/lib/Target/Mips/Mips32r6InstrInfo.td b/lib/Target/Mips/Mips32r6InstrInfo.td index 8ae2635af04..a2bcfe19179 100644 --- a/lib/Target/Mips/Mips32r6InstrInfo.td +++ b/lib/Target/Mips/Mips32r6InstrInfo.td @@ -90,6 +90,9 @@ class SELEQZ_D_ENC : COP1_3R_FM<0b010100, FIELD_FMT_D>; class SELNEZ_S_ENC : COP1_3R_FM<0b010111, FIELD_FMT_S>; class SELNEZ_D_ENC : COP1_3R_FM<0b010111, FIELD_FMT_D>; +class RINT_S_ENC : COP1_2R_FM<0b011010, FIELD_FMT_S>; +class RINT_D_ENC : COP1_2R_FM<0b011010, FIELD_FMT_D>; + //===----------------------------------------------------------------------===// // // Instruction Descriptions @@ -207,6 +210,16 @@ class SELEQZ_D_DESC : SELEQNEZ_DESC_BASE<"seleqz.d", FGR64Opnd>; class SELNEZ_S_DESC : SELEQNEZ_DESC_BASE<"selnez.s", FGR32Opnd>; class SELNEZ_D_DESC : SELEQNEZ_DESC_BASE<"selnez.d", FGR64Opnd>; +class RINT_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> { + dag OutOperandList = (outs FGROpnd:$fd); + dag InOperandList = (ins FGROpnd:$fs); + string AsmString = !strconcat(instr_asm, "\t$fd, $fs"); + list<dag> Pattern = []; +} + +class RINT_S_DESC : RINT_DESC_BASE<"rint.s", FGR32Opnd>; +class RINT_D_DESC : RINT_DESC_BASE<"rint.d", FGR64Opnd>; + //===----------------------------------------------------------------------===// // // Instruction Definitions @@ -273,8 +286,8 @@ def MUHU : MUHU_ENC, MUHU_DESC, ISA_MIPS32R6; def MUL_R6 : MUL_R6_ENC, MUL_R6_DESC, ISA_MIPS32R6; def MULU : MULU_ENC, MULU_DESC, ISA_MIPS32R6; def NAL; // BAL with rd=0 -def RINT_D; -def RINT_S; +def RINT_D : RINT_D_ENC, RINT_D_DESC, ISA_MIPS32R6; +def RINT_S : RINT_S_ENC, RINT_S_DESC, ISA_MIPS32R6; def SELEQZ; def SELEQZ_D : SELEQZ_D_ENC, SELEQZ_D_DESC, ISA_MIPS32R6; def SELEQZ_S : SELEQZ_S_ENC, SELEQZ_S_DESC, ISA_MIPS32R6; |