diff options
| author | Akira Hatanaka <ahatanaka@mips.com> | 2012-12-20 04:27:52 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanaka@mips.com> | 2012-12-20 04:27:52 +0000 |
| commit | 9bf571fe2c24305aee6a930ed3b2561f6d4ff237 (patch) | |
| tree | ee3861cee93ad8b953d57db752ee7cba74f9f9d2 /lib/Target/Mips/MipsInstrInfo.td | |
| parent | c23061547de868c5971e1f7a12bc54a37a59a53f (diff) | |
[mips] Refactor SLT (set on less than) instructions. Separate encoding
information from the rest.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170664 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/MipsInstrInfo.td')
| -rw-r--r-- | lib/Target/Mips/MipsInstrInfo.td | 31 |
1 files changed, 13 insertions, 18 deletions
diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index 5fce6391b4b..af9df4ba658 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -567,21 +567,16 @@ class CBranchZero<string opstr, PatFrag cond_op, RegisterClass RC> : } // SetCC -class SetCC_R<bits<6> op, bits<6> func, string instr_asm, PatFrag cond_op, - RegisterClass RC>: - FR<op, func, (outs CPURegs:$rd), (ins RC:$rs, RC:$rt), - !strconcat(instr_asm, "\t$rd, $rs, $rt"), - [(set CPURegs:$rd, (cond_op RC:$rs, RC:$rt))], - IIAlu> { - let shamt = 0; -} +class SetCC_R<string opstr, PatFrag cond_op, RegisterClass RC> : + InstSE<(outs CPURegs:$rd), (ins RC:$rs, RC:$rt), + !strconcat(opstr, "\t$rd, $rs, $rt"), + [(set CPURegs:$rd, (cond_op RC:$rs, RC:$rt))], IIAlu, FrmR>; -class SetCC_I<bits<6> op, string instr_asm, PatFrag cond_op, Operand Od, - PatLeaf imm_type, RegisterClass RC>: - FI<op, (outs CPURegs:$rt), (ins RC:$rs, Od:$imm16), - !strconcat(instr_asm, "\t$rt, $rs, $imm16"), - [(set CPURegs:$rt, (cond_op RC:$rs, imm_type:$imm16))], - IIAlu>; +class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type, + RegisterClass RC>: + InstSE<(outs CPURegs:$rt), (ins RC:$rs, Od:$imm16), + !strconcat(opstr, "\t$rt, $rs, $imm16"), + [(set CPURegs:$rt, (cond_op RC:$rs, imm_type:$imm16))], IIAlu, FrmI>; // Jump class JumpFJ<bits<6> op, DAGOperand opnd, string instr_asm, @@ -897,8 +892,8 @@ def LoadAddr32Imm : LoadAddressImm<"la", shamt,CPURegs>; def ADDiu : ArithLogicI<"addiu", simm16, CPURegs, immSExt16, add>, ADDI_FM<0x9>, IsAsCheapAsAMove; def ADDi : ArithLogicI<"addi", simm16, CPURegs>, ADDI_FM<0x8>; -def SLTi : SetCC_I<0x0a, "slti", setlt, simm16, immSExt16, CPURegs>; -def SLTiu : SetCC_I<0x0b, "sltiu", setult, simm16, immSExt16, CPURegs>; +def SLTi : SetCC_I<"slti", setlt, simm16, immSExt16, CPURegs>, SLTI_FM<0xa>; +def SLTiu : SetCC_I<"sltiu", setult, simm16, immSExt16, CPURegs>, SLTI_FM<0xb>; def ANDi : ArithLogicI<"andi", uimm16, CPURegs, immZExt16, and>, ADDI_FM<0xc>; def ORi : ArithLogicI<"ori", uimm16, CPURegs, immZExt16, or>, ADDI_FM<0xd>; def XORi : ArithLogicI<"xori", uimm16, CPURegs, immZExt16, xor>, ADDI_FM<0xe>; @@ -909,8 +904,8 @@ def ADDu : ArithLogicR<"addu", CPURegs, 1, IIAlu, add>, ADD_FM<0, 0x21>; def SUBu : ArithLogicR<"subu", CPURegs, 0, IIAlu, sub>, ADD_FM<0, 0x23>; def ADD : ArithLogicR<"add", CPURegs>, ADD_FM<0, 0x20>; def SUB : ArithLogicR<"sub", CPURegs>, ADD_FM<0, 0x22>; -def SLT : SetCC_R<0x00, 0x2a, "slt", setlt, CPURegs>; -def SLTu : SetCC_R<0x00, 0x2b, "sltu", setult, CPURegs>; +def SLT : SetCC_R<"slt", setlt, CPURegs>, ADD_FM<0, 0x2a>; +def SLTu : SetCC_R<"sltu", setult, CPURegs>, ADD_FM<0, 0x2b>; def AND : ArithLogicR<"and", CPURegs, 1, IIAlu, and>, ADD_FM<0, 0x24>; def OR : ArithLogicR<"or", CPURegs, 1, IIAlu, or>, ADD_FM<0, 0x25>; def XOR : ArithLogicR<"xor", CPURegs, 1, IIAlu, xor>, ADD_FM<0, 0x26>; |