diff options
author | Daniel Sanders <daniel.sanders@imgtec.com> | 2014-05-12 12:28:15 +0000 |
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committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2014-05-12 12:28:15 +0000 |
commit | ea27d2f50b1666732f2345fcb39be5f71485aa83 (patch) | |
tree | b2dc00db94861ff4148ace4009e5e85f009686e0 /lib/Target/Mips/Mips.td | |
parent | d46b2e219d5d5aaf1707237ebf8dea976cd16396 (diff) |
[mips] Fold FeatureSEInReg into FeatureMips32r2
Summary: No functional change
Reviewers: vmedic
Reviewed By: vmedic
Differential Revision: http://reviews.llvm.org/D3693
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208543 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/Mips.td')
-rw-r--r-- | lib/Target/Mips/Mips.td | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/lib/Target/Mips/Mips.td b/lib/Target/Mips/Mips.td index 6fe7d26c451..66b3d742503 100644 --- a/lib/Target/Mips/Mips.td +++ b/lib/Target/Mips/Mips.td @@ -75,8 +75,6 @@ def FeatureEABI : SubtargetFeature<"eabi", "MipsABI", "EABI", "Enable eabi ABI">; def FeatureVFPU : SubtargetFeature<"vfpu", "HasVFPU", "true", "Enable vector FPU instructions.">; -def FeatureSEInReg : SubtargetFeature<"seinreg", "HasSEInReg", "true", - "Enable 'signext in register' instructions.">; def FeatureBitCount : SubtargetFeature<"bitcount", "HasBitCount", "true", "Enable 'count leading bits' instructions.">; def FeatureMips1 : SubtargetFeature<"mips1", "MipsArchVersion", "Mips1", @@ -110,8 +108,7 @@ def FeatureMips32 : SubtargetFeature<"mips32", "MipsArchVersion", "Mips32", FeatureMips4_32, FeatureBitCount]>; def FeatureMips32r2 : SubtargetFeature<"mips32r2", "MipsArchVersion", "Mips32r2", "Mips32r2 ISA Support", - [FeatureMips4_32r2, FeatureMips32, - FeatureSEInReg]>; + [FeatureMips4_32r2, FeatureMips32]>; def FeatureMips32r6 : SubtargetFeature<"mips32r6", "MipsArchVersion", "Mips32r6", "Mips32r6 ISA Support [experimental]", |