diff options
| author | Jack Carter <jack.carter@imgtec.com> | 2013-08-13 20:54:07 +0000 |
|---|---|---|
| committer | Jack Carter <jack.carter@imgtec.com> | 2013-08-13 20:54:07 +0000 |
| commit | 3f70e908c3d9de7acea462719ebf36dca1560f9c (patch) | |
| tree | 917c747b2b5e1519c65930582111be8ec27b8d74 /lib/Target/Mips/Mips.td | |
| parent | da0860f78e6e43aca3333a7815b2f9bc0f8dfac0 (diff) | |
[Mips][msa] Added initial MSA support.
* msa SubtargetFeature
* registers
* ld.[bhwd], and st.[bhwd] instructions
Does not correctly prohibit use of both 32-bit FPU registers and MSA together.
Patch by Daniel Sanders
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188313 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/Mips.td')
| -rw-r--r-- | lib/Target/Mips/Mips.td | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/lib/Target/Mips/Mips.td b/lib/Target/Mips/Mips.td index 2595e41a877..b8e3f39256d 100644 --- a/lib/Target/Mips/Mips.td +++ b/lib/Target/Mips/Mips.td @@ -78,6 +78,8 @@ def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true", "Mips DSP ASE">; def FeatureDSPR2 : SubtargetFeature<"dspr2", "HasDSPR2", "true", "Mips DSP-R2 ASE", [FeatureDSP]>; +def FeatureMSA : SubtargetFeature<"msa", "HasMSA", "true", "Mips MSA ASE">; + def FeatureMicroMips : SubtargetFeature<"micromips", "InMicroMipsMode", "true", "microMips mode">; |